[NFC][RISCV] Remove redundant pseudo instructions for vector load/store.

[HsiangKai]

Summary

Not all combinations of SEW and LMUL we need to support. For example, we
only need to support [M1, M2, M4, M8] for SEW = 64. There is no need to
define pseudos for PseudoVLSE64MF8, PseudoVLSE64MF4, and PseudoVLSE64MF2.

[khchen]

Yes, thanks for fixup!
LGTM.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

3151–3152

/*fault-only-first=*/ is correct style.

3178

Ditto.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

3151–3152

No, /*isFF=*/, it's always the name of the argument (and fault-only-first isn't even a valid identifier).

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

3151–3152

Yeah, I didn't intend to use the argument name in the comment. I use the name in the V specification for its purpose in the comments. Anyway, I will change it to /*isFF=*/.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, bits<11> EEW, bits<3> LMUL>:
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
-multiclass VPseudoUSLoad {
-  foreach lmul = MxList.m in {
+multiclass VPseudoUSLoad<bit isFF> {
+  foreach eew = EEWList in {
+    foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
+      defvar FFStr = !if(isFF, "FF", "");
       let VLMul = lmul.value in {
-      def "_V_" # LInfo : VPseudoUSLoadNoMask<vreg>;
-      def "_V_" # LInfo # "_MASK" : VPseudoUSLoadMask<vreg>;
+        def "E" # eew # FFStr # "_V_" # LInfo : VPseudoUSLoadNoMask<vreg>;
+        def "E" # eew # FFStr # "_V_" # LInfo # "_MASK" : VPseudoUSLoadMask<vreg>;
+      }
     }
   }
 }
 
 multiclass VPseudoSLoad {
-  foreach lmul = MxList.m in {
+  foreach eew = EEWList in {
+    foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
-      def "_V_" # LInfo : VPseudoSLoadNoMask<vreg>;
-      def "_V_" # LInfo # "_MASK" : VPseudoSLoadMask<vreg>;
+        def "E" # eew # "_V_" # LInfo : VPseudoSLoadNoMask<vreg>;
+        def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSLoadMask<vreg>;
+      }
     }
   }
 }
 
 multiclass VPseudoILoad {
+  foreach eew = EEWList in {
     foreach lmul = MxList.m in
-  foreach idx_lmul = MxList.m in {
+    foreach idx_lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar Vreg = lmul.vrclass;
       defvar IdxLInfo = idx_lmul.MX;
       defvar IdxVreg = idx_lmul.vrclass;
       let VLMul = lmul.value in {
-      def "_V_" # IdxLInfo # "_" # LInfo : VPseudoILoadNoMask<Vreg, IdxVreg>;
-      def "_V_" # IdxLInfo # "_" # LInfo # "_MASK" : VPseudoILoadMask<Vreg, IdxVreg>;
+        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo : VPseudoILoadNoMask<Vreg, IdxVreg>;
+        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" : VPseudoILoadMask<Vreg, IdxVreg>;
+      }
     }
   }
 }
 
 multiclass VPseudoUSStore {
-  foreach lmul = MxList.m in {
+  foreach eew = EEWList in {
+    foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
-      def "_V_" # LInfo : VPseudoUSStoreNoMask<vreg>;
-      def "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg>;
+        def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg>;
+        def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg>;
+      }
     }
   }
 }
 
 multiclass VPseudoSStore {
-  foreach lmul = MxList.m in {
+  foreach eew = EEWList in {
+    foreach lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar vreg = lmul.vrclass;
       let VLMul = lmul.value in {
-      def "_V_" # LInfo : VPseudoSStoreNoMask<vreg>;
-      def "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg>;
+        def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg>;
+        def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg>;
+      }
     }
   }
 }
 
 multiclass VPseudoIStore {
+  foreach eew = EEWList in {
     foreach lmul = MxList.m in
-  foreach idx_lmul = MxList.m in {
+    foreach idx_lmul = MxSet<eew>.m in {
       defvar LInfo = lmul.MX;
       defvar Vreg = lmul.vrclass;
       defvar IdxLInfo = idx_lmul.MX;
       defvar IdxVreg = idx_lmul.vrclass;
       let VLMul = lmul.value in {
-      def "_V_" # IdxLInfo # "_" # LInfo : VPseudoIStoreNoMask<Vreg, IdxVreg>;
-      def "_V_" # IdxLInfo # "_" # LInfo # "_MASK" : VPseudoIStoreMask<Vreg, IdxVreg>;
+        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo :
+          VPseudoIStoreNoMask<Vreg, IdxVreg>;
+        def "EI" # eew # "_V_" # IdxLInfo # "_" # LInfo # "_MASK" :
+          VPseudoIStoreMask<Vreg, IdxVreg>;
+      }
     }
   }
 }
 
 multiclass VPseudoUnaryS_M {
   foreach mti = AllMasks in
   {
     let VLMul = mti.LMul.value in {

 // 7. Vector Loads and Stores
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // 7.4 Vector Unit-Stride Instructions
 //===----------------------------------------------------------------------===//
 
 // Pseudos Unit-Stride Loads and Stores
-foreach eew = EEWList in {
-  defm PseudoVLE # eew : VPseudoUSLoad;
-  defm PseudoVSE # eew : VPseudoUSStore;
-}
+defm PseudoVL : VPseudoUSLoad</*isFF=*/false>;
+defm PseudoVS : VPseudoUSStore;
 
 //===----------------------------------------------------------------------===//
 // 7.5 Vector Strided Instructions
 //===----------------------------------------------------------------------===//
 
 // Vector Strided Loads and Stores
-foreach eew = EEWList in {
-  defm PseudoVLSE # eew : VPseudoSLoad;
-  defm PseudoVSSE # eew : VPseudoSStore;
-}
+defm PseudoVLS : VPseudoSLoad;
+defm PseudoVSS : VPseudoSStore;
 
 //===----------------------------------------------------------------------===//
 // 7.6 Vector Indexed Instructions
 //===----------------------------------------------------------------------===//
 
 // Vector Indexed Loads and Stores
-foreach eew = EEWList in {
-  defm PseudoVLUXEI # eew : VPseudoILoad;
-  defm PseudoVLOXEI # eew : VPseudoILoad;
-  defm PseudoVSOXEI # eew : VPseudoIStore;
-  defm PseudoVSUXEI # eew : VPseudoIStore;
-}
+defm PseudoVLUX : VPseudoILoad;
+defm PseudoVLOX : VPseudoILoad;
+defm PseudoVSOX : VPseudoIStore;
+defm PseudoVSUX : VPseudoIStore;
 
 //===----------------------------------------------------------------------===//
 // 7.7. Unit-stride Fault-Only-First Loads
 //===----------------------------------------------------------------------===//
 
 // vleff may update VL register
 let hasSideEffects = 1, Defs = [VL] in
-foreach eew = EEWList in {
-  defm PseudoVLE # eew # FF : VPseudoUSLoad;
-}
+defm PseudoVL : VPseudoUSLoad</*isFF=*/true>;
 
 //===----------------------------------------------------------------------===//
 // 7.8. Vector Load/Store Segment Instructions
 //===----------------------------------------------------------------------===//
-defm PseudoVLSEG : VPseudoUSSegLoad</*fault-only-first*/false>;
+defm PseudoVLSEG : VPseudoUSSegLoad</*isFF=*/false>;
 defm PseudoVLSSEG : VPseudoSSegLoad;
 defm PseudoVLOXSEG : VPseudoISegLoad;
 defm PseudoVLUXSEG : VPseudoISegLoad;
 defm PseudoVSSEG : VPseudoUSSegStore;
 defm PseudoVSSSEG : VPseudoSSegStore;
 defm PseudoVSOXSEG : VPseudoISegStore;
 defm PseudoVSUXSEG : VPseudoISegStore;
 
 // vlseg<nf>e<eew>ff.v may update VL register
 let hasSideEffects = 1, Defs = [VL] in
-defm PseudoVLSEG : VPseudoUSSegLoad</*fault-only-first*/true>;
+defm PseudoVLSEG : VPseudoUSSegLoad</*isFF=*/true>;
 
 //===----------------------------------------------------------------------===//
 // 8. Vector AMO Operations
 //===----------------------------------------------------------------------===//
 defm PseudoVAMOSWAP : VPseudoAMO;
 defm PseudoVAMOADD : VPseudoAMO;
 defm PseudoVAMOXOR : VPseudoAMO;
 defm PseudoVAMOAND : VPseudoAMO;