This is an archive of the discontinued LLVM Phabricator instance.

Differential D95404

[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
ClosedPublic

Authored by craig.topper on Jan 25 2021, 3:36 PM.

Details

Reviewers
HsiangKai
frasercrmck
evandro
rogfer01
Commits
rGbfc60acd9803: [RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions…
Summary

Move the Suffix string into the VTypeInfo class so we don't need a helper class to get to it.

Adjust pseudo naming scheme for FPRs to put F16/F32/F64 in
place of F in the pseudo instruction name rather than as a suffix.
This avoids special cases like VFMERGE from the original patch.

Diff Detail

Revision Contents

Diff 319233

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
def SCALAR_F16 : FPR_Info<FPR16, "F16">; def SCALAR_F16 : FPR_Info<FPR16, "F16">;
def SCALAR_F32 : FPR_Info<FPR32, "F32">; def SCALAR_F32 : FPR_Info<FPR32, "F32">;
def SCALAR_F64 : FPR_Info<FPR64, "F64">; def SCALAR_F64 : FPR_Info<FPR64, "F64">;
def FPList { def FPList {
list<FPR_Info> fpinfo = [SCALAR_F16, SCALAR_F32, SCALAR_F64]; list<FPR_Info> fpinfo = [SCALAR_F16, SCALAR_F32, SCALAR_F64];
} }
class getScalarSuffix<ValueType type> {
string suffix = !cond(!eq(type, XLenVT): "VX",
!eq(type, f16): "VF_F16",
!eq(type, f32): "VF_F32",
!eq(type, f64): "VF_F64");
}
class getWScalarSuffix<ValueType type> {
string suffix = !cond(!eq(type, XLenVT): "WX",
!eq(type, f16): "WF_F16",
!eq(type, f32): "WF_F32",
!eq(type, f64): "WF_F64");
}
class MxSet<int eew> { class MxSet<int eew> {
list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], list<LMULInfo> m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
!eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8],
!eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8], !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8],
!eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]); !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]);
} }
class NFSet<LMULInfo m> { class NFSet<LMULInfo m> {
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesclass VTypeInfo<ValueType Vec, ValueType Mas, int Sew, VReg Reg, LMULInfo M,
int SEW = Sew; int SEW = Sew;
VReg RegClass = Reg; VReg RegClass = Reg;
LMULInfo LMul = M; LMULInfo LMul = M;
ValueType Scalar = Scal; ValueType Scalar = Scal;
RegisterClass ScalarRegClass = ScalarReg; RegisterClass ScalarRegClass = ScalarReg;
// The pattern fragment which produces the AVL operand, representing the // The pattern fragment which produces the AVL operand, representing the
// "natural" vector length for this type. For scalable vectors this is VLMax. // "natural" vector length for this type. For scalable vectors this is VLMax.
OutPatFrag AVL = VLMax; OutPatFrag AVL = VLMax;
string ScalarSuffix = !cond(!eq(Scal, XLenVT) : "X",
!eq(Scal, f16) : "F16",
!eq(Scal, f32) : "F32",
!eq(Scal, f64) : "F64");
} }
class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew, class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
VReg Reg, LMULInfo M, ValueType Scal = XLenVT, VReg Reg, LMULInfo M, ValueType Scal = XLenVT,
RegisterClass ScalarReg = GPR> RegisterClass ScalarReg = GPR>
: VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg> : VTypeInfo<Vec, Mas, Sew, Reg, M, Scal, ScalarReg>
{ {
ValueType VectorM1 = VecM1; ValueType VectorM1 = VecM1;
▲ Show 20 Lines • Show All 265 Lines • ▼ Show 20 Lines string VInst = !subst("_M8", "",
!subst("_B1", "", !subst("_B1", "",
!subst("_B2", "", !subst("_B2", "",
!subst("_B4", "", !subst("_B4", "",
!subst("_B8", "", !subst("_B8", "",
!subst("_B16", "", !subst("_B16", "",
!subst("_B32", "", !subst("_B32", "",
!subst("_B64", "", !subst("_B64", "",
!subst("_MASK", "", !subst("_MASK", "",
!subst("_F16", "", !subst("F16", "F",
!subst("_F32", "", !subst("F32", "F",
!subst("_F64", "", !subst("F64", "F",
!subst("Pseudo", "", PseudoInst))))))))))))))))))); !subst("Pseudo", "", PseudoInst)))))))))))))))))));
} }
class ToLowerCase<string Upper> { class ToLowerCase<string Upper> {
string L = !subst("FF", "ff", string L = !subst("FF", "ff",
!subst("VLSEG", "vlseg", !subst("VLSEG", "vlseg",
!subst("VLSSEG", "vlsseg", !subst("VLSSEG", "vlsseg",
!subst("VSSEG", "vsseg", !subst("VSSEG", "vsseg",
▲ Show 20 Lines • Show All 922 Lines • ▼ Show 20 Lines
multiclass VPseudoBinaryV_VX<string Constraint = ""> { multiclass VPseudoBinaryV_VX<string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>; defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
} }
multiclass VPseudoBinaryV_VF<string Constraint = ""> { multiclass VPseudoBinaryV_VF<string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
foreach f = FPList.fpinfo in foreach f = FPList.fpinfo in
defm "_VF_" # f.FX : VPseudoBinary<m.vrclass, m.vrclass, defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass,
f.fprclass, m, Constraint>; f.fprclass, m, Constraint>;
} }
multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> { multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>; defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
} }
multiclass VPseudoBinaryM_MM { multiclass VPseudoBinaryM_MM {
Show All 20 Linesmulticlass VPseudoBinaryW_VX {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m, defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_VF { multiclass VPseudoBinaryW_VF {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
foreach f = FPList.fpinfo[0-1] in foreach f = FPList.fpinfo[0-1] in
defm "_VF_" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass, defm "_V" # f.FX : VPseudoBinary<m.wvrclass, m.vrclass,
f.fprclass, m, f.fprclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_WV { multiclass VPseudoBinaryW_WV {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m, defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_WX { multiclass VPseudoBinaryW_WX {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_WF { multiclass VPseudoBinaryW_WF {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
foreach f = FPList.fpinfo[0-1] in foreach f = FPList.fpinfo[0-1] in
defm "_WF_" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass, defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass,
f.fprclass, m, f.fprclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryV_WV { multiclass VPseudoBinaryV_WV {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m, defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
Show All 30 Lines def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
!if(!and(CarryIn, !not(CarryOut)), !if(!and(CarryIn, !not(CarryOut)),
GetVRegNoV0<m.vrclass>.R, m.vrclass)), GetVRegNoV0<m.vrclass>.R, m.vrclass)),
m.vrclass, GPR, m, CarryIn, Constraint>; m.vrclass, GPR, m, CarryIn, Constraint>;
} }
multiclass VPseudoBinaryV_FM { multiclass VPseudoBinaryV_FM {
foreach m = MxList.m in foreach m = MxList.m in
foreach f = FPList.fpinfo in foreach f = FPList.fpinfo in
def "_VFM_" # f.FX # "_" # m.MX : def "_V" # f.FX # "M_" # m.MX :
VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R, VPseudoBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">; m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">;
} }
multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1, multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> { string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX : def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
Show All 12 Lines foreach m = MxList.m in {
} }
} }
} }
multiclass VPseudoUnaryV_F_NoDummyMask { multiclass VPseudoUnaryV_F_NoDummyMask {
foreach m = MxList.m in { foreach m = MxList.m in {
foreach f = FPList.fpinfo in { foreach f = FPList.fpinfo in {
let VLMul = m.value in { let VLMul = m.value in {
def "_F_" # f.FX # "_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>; def "_" # f.FX # "_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, f.fprclass>;
} }
} }
} }
} }
multiclass VPseudoUnaryV_V { multiclass VPseudoUnaryV_V {
foreach m = MxList.m in { foreach m = MxList.m in {
let VLMul = m.value in { let VLMul = m.value in {
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesmulticlass VPseudoBinaryM_VX {
foreach m = MxList.m in foreach m = MxList.m in
defm "_VX" : defm "_VX" :
VPseudoBinary<VR, m.vrclass, GPR, m, "@earlyclobber $rd">; VPseudoBinary<VR, m.vrclass, GPR, m, "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryM_VF { multiclass VPseudoBinaryM_VF {
foreach m = MxList.m in foreach m = MxList.m in
foreach f = FPList.fpinfo in foreach f = FPList.fpinfo in
defm "_VF_" # f.FX : defm "_V" # f.FX :
VPseudoBinary<VR, m.vrclass, f.fprclass, m, "@earlyclobber $rd">; VPseudoBinary<VR, m.vrclass, f.fprclass, m, "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryM_VI { multiclass VPseudoBinaryM_VI {
foreach m = MxList.m in foreach m = MxList.m in
defm _VI : VPseudoBinary<VR, m.vrclass, simm5, m, "@earlyclobber $rd">; defm _VI : VPseudoBinary<VR, m.vrclass, simm5, m, "@earlyclobber $rd">;
} }
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> { multiclass VPseudoTernaryV_VX_AAXA<string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
defm "_VX" : VPseudoTernary<m.vrclass, GPR, m.vrclass, m, Constraint>; defm "_VX" : VPseudoTernary<m.vrclass, GPR, m.vrclass, m, Constraint>;
} }
multiclass VPseudoTernaryV_VF_AAXA<string Constraint = ""> { multiclass VPseudoTernaryV_VF_AAXA<string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
foreach f = FPList.fpinfo in foreach f = FPList.fpinfo in
defm "_VF_" # f.FX : VPseudoTernary<m.vrclass, f.fprclass, m.vrclass, defm "_V" # f.FX : VPseudoTernary<m.vrclass, f.fprclass, m.vrclass,
m, Constraint>; m, Constraint>;
} }
multiclass VPseudoTernaryW_VV { multiclass VPseudoTernaryW_VV {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>; defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>;
} }
multiclass VPseudoTernaryW_VX { multiclass VPseudoTernaryW_VX {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm "_VX" : VPseudoTernary<m.wvrclass, GPR, m.vrclass, m, constraint>; defm "_VX" : VPseudoTernary<m.wvrclass, GPR, m.vrclass, m, constraint>;
} }
multiclass VPseudoTernaryW_VF { multiclass VPseudoTernaryW_VF {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
foreach f = FPList.fpinfo[0-1] in foreach f = FPList.fpinfo[0-1] in
defm "_VF_" # f.FX : VPseudoTernary<m.wvrclass, f.fprclass, m.vrclass, m, defm "_V" # f.FX : VPseudoTernary<m.wvrclass, f.fprclass, m.vrclass, m,
constraint>; constraint>;
} }
multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> { multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList.m in foreach m = MxList.m in
defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>; defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
} }
multiclass VPseudoTernaryV_VV_VX_AAXA<string Constraint = ""> { multiclass VPseudoTernaryV_VV_VX_AAXA<string Constraint = ""> {
▲ Show 20 Lines • Show All 741 Lines • ▼ Show 20 Lines if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then {
vti.RegClass, ivti.RegClass>; vti.RegClass, ivti.RegClass>;
} }
} }
} }
multiclass VPatBinaryV_VX<string intrinsic, string instruction, multiclass VPatBinaryV_VX<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in { foreach vti = vtilist in {
defvar kind = getScalarSuffix<vti.Scalar>.suffix; defvar kind = "V"#vti.ScalarSuffix;
defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX, defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX,
vti.Vector, vti.Vector, vti.Scalar, vti.Mask, vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
vti.SEW, vti.RegClass, vti.SEW, vti.RegClass,
vti.RegClass, vti.ScalarRegClass>; vti.RegClass, vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction, multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
Show All 33 Linesmulticlass VPatBinaryW_VV<string intrinsic, string instruction,
} }
} }
multiclass VPatBinaryW_VX<string intrinsic, string instruction, multiclass VPatBinaryW_VX<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in { foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defvar kind = getScalarSuffix<Vti.Scalar>.suffix; defvar kind = "V"#Vti.ScalarSuffix;
defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask, Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask,
Vti.SEW, Wti.RegClass, Vti.SEW, Wti.RegClass,
Vti.RegClass, Vti.ScalarRegClass>; Vti.RegClass, Vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryW_WV<string intrinsic, string instruction, multiclass VPatBinaryW_WV<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in { foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX, defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
Vti.SEW, Wti.RegClass, Vti.SEW, Wti.RegClass,
Wti.RegClass, Vti.RegClass>; Wti.RegClass, Vti.RegClass>;
} }
} }
multiclass VPatBinaryW_WX<string intrinsic, string instruction, multiclass VPatBinaryW_WX<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in { foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defvar kind = getWScalarSuffix<Vti.Scalar>.suffix; defvar kind = "W"#Vti.ScalarSuffix;
defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
Vti.SEW, Wti.RegClass, Vti.SEW, Wti.RegClass,
Wti.RegClass, Vti.ScalarRegClass>; Wti.RegClass, Vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryV_WV<string intrinsic, string instruction, multiclass VPatBinaryV_WV<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in { foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX, defm : VPatBinary<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask, Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
Vti.SEW, Vti.RegClass, Vti.SEW, Vti.RegClass,
Wti.RegClass, Vti.RegClass>; Wti.RegClass, Vti.RegClass>;
} }
} }
multiclass VPatBinaryV_WX<string intrinsic, string instruction, multiclass VPatBinaryV_WX<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach VtiToWti = vtilist in { foreach VtiToWti = vtilist in {
defvar Vti = VtiToWti.Vti; defvar Vti = VtiToWti.Vti;
defvar Wti = VtiToWti.Wti; defvar Wti = VtiToWti.Wti;
defvar kind = getWScalarSuffix<Vti.Scalar>.suffix; defvar kind = "W"#Vti.ScalarSuffix;
defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX, defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask, Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
Vti.SEW, Vti.RegClass, Vti.SEW, Vti.RegClass,
Wti.RegClass, Vti.ScalarRegClass>; Wti.RegClass, Vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryV_WI<string intrinsic, string instruction, multiclass VPatBinaryV_WI<string intrinsic, string instruction,
Show All 19 Lines defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM",
vti.RegClass, vti.RegClass>; vti.RegClass, vti.RegClass>;
} }
multiclass VPatBinaryV_XM<string intrinsic, string instruction, multiclass VPatBinaryV_XM<string intrinsic, string instruction,
bit CarryOut = 0, bit CarryOut = 0,
list<VTypeInfo> vtilist = AllIntegerVectors> { list<VTypeInfo> vtilist = AllIntegerVectors> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatBinaryCarryIn<intrinsic, instruction, defm : VPatBinaryCarryIn<intrinsic, instruction,
!cond(!eq(vti.Scalar, XLenVT): "VXM", "V"#vti.ScalarSuffix#"M",
!eq(vti.Scalar, f16): "VFM_F16",
!eq(vti.Scalar, f32): "VFM_F32",
!eq(vti.Scalar, f64): "VFM_F64"),
!if(CarryOut, vti.Mask, vti.Vector), !if(CarryOut, vti.Mask, vti.Vector),
vti.Vector, vti.Scalar, vti.Mask, vti.Vector, vti.Scalar, vti.Mask,
vti.SEW, vti.LMul, vti.SEW, vti.LMul,
vti.RegClass, vti.ScalarRegClass>; vti.RegClass, vti.ScalarRegClass>;
} }
multiclass VPatBinaryV_IM<string intrinsic, string instruction, multiclass VPatBinaryV_IM<string intrinsic, string instruction,
bit CarryOut = 0> { bit CarryOut = 0> {
Show All 36 Lines defm : VPatBinary<intrinsic, instruction # "_VV_" # vti.LMul.MX,
vti.Mask, vti.Vector, vti.Vector, vti.Mask, vti.Mask, vti.Vector, vti.Vector, vti.Mask,
vti.SEW, VR, vti.SEW, VR,
vti.RegClass, vti.RegClass>; vti.RegClass, vti.RegClass>;
} }
multiclass VPatBinaryM_VX<string intrinsic, string instruction, multiclass VPatBinaryM_VX<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in { foreach vti = vtilist in {
defvar kind = getScalarSuffix<vti.Scalar>.suffix; defvar kind = "V"#vti.ScalarSuffix;
defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX, defm : VPatBinary<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX,
vti.Mask, vti.Vector, vti.Scalar, vti.Mask, vti.Mask, vti.Vector, vti.Scalar, vti.Mask,
vti.SEW, VR, vti.SEW, VR,
vti.RegClass, vti.ScalarRegClass>; vti.RegClass, vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryM_VI<string intrinsic, string instruction, multiclass VPatBinaryM_VI<string intrinsic, string instruction,
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines defm : VPatTernary<intrinsic, instruction, "VX",
vti.SEW, vti.LMul, vti.RegClass, vti.SEW, vti.LMul, vti.RegClass,
vti.RegClass, GPR>; vti.RegClass, GPR>;
} }
multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
defm : VPatTernary<intrinsic, instruction, defm : VPatTernary<intrinsic, instruction,
getScalarSuffix<vti.Scalar>.suffix, "V"#vti.ScalarSuffix,
vti.Vector, vti.Scalar, vti.Vector, vti.Mask, vti.Vector, vti.Scalar, vti.Vector, vti.Mask,
vti.SEW, vti.LMul, vti.RegClass, vti.SEW, vti.LMul, vti.RegClass,
vti.ScalarRegClass, vti.RegClass>; vti.ScalarRegClass, vti.RegClass>;
} }
multiclass VPatTernaryV_VI<string intrinsic, string instruction, multiclass VPatTernaryV_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand Imm_type> { list<VTypeInfo> vtilist, Operand Imm_type> {
foreach vti = vtilist in foreach vti = vtilist in
Show All 16 Lines
} }
multiclass VPatTernaryW_VX<string intrinsic, string instruction, multiclass VPatTernaryW_VX<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist> { list<VTypeInfoToWide> vtilist> {
foreach vtiToWti = vtilist in { foreach vtiToWti = vtilist in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
defm : VPatTernary<intrinsic, instruction, defm : VPatTernary<intrinsic, instruction,
getScalarSuffix<vti.Scalar>.suffix, "V"#vti.ScalarSuffix,
wti.Vector, vti.Scalar, vti.Vector, wti.Vector, vti.Scalar, vti.Vector,
vti.Mask, vti.SEW, vti.LMul, vti.Mask, vti.SEW, vti.LMul,
wti.RegClass, vti.ScalarRegClass, vti.RegClass>; wti.RegClass, vti.ScalarRegClass, vti.RegClass>;
} }
} }
multiclass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
▲ Show 20 Lines • Show All 768 Lines • ▼ Show 20 Lines
let Predicates = [HasStdExtV, HasStdExtF] in { let Predicates = [HasStdExtV, HasStdExtF] in {
let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1, let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1,
Uses = [VL, VTYPE] in { Uses = [VL, VTYPE] in {
foreach m = MxList.m in { foreach m = MxList.m in {
foreach f = FPList.fpinfo in { foreach f = FPList.fpinfo in {
let VLMul = m.value in { let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VFMV_F_S in let HasSEWOp = 1, BaseInstr = VFMV_F_S in
def PseudoVFMV_F_S # "_" # f.FX # "_" # m.MX : def "PseudoVFMV_" # f.FX # "_S_" # m.MX :
Pseudo<(outs f.fprclass:$rd), Pseudo<(outs f.fprclass:$rd),
(ins m.vrclass:$rs2, (ins m.vrclass:$rs2,
ixlenimm:$sew), ixlenimm:$sew),
[]>, RISCVVPseudo; []>, RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, WritesElement0 = 1, let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, WritesElement0 = 1,
Constraints = "$rd = $rs1" in Constraints = "$rd = $rs1" in
def PseudoVFMV_S_F # "_" # f.FX #"_" # m.MX : def "PseudoVFMV_S_" # f.FX # "_" # m.MX :
Pseudo<(outs m.vrclass:$rd), Pseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, f.fprclass:$rs2, (ins m.vrclass:$rs1, f.fprclass:$rs2,
GPR:$vl, ixlenimm:$sew), GPR:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo; []>, RISCVVPseudo;
} }
} }
} }
} }
▲ Show 20 Lines • Show All 499 Lines • ▼ Show 20 Linesforeach fvti = AllFloatVectors in {
// If we're splatting fpimm0, use vmv.v.x vd, x0. // If we're splatting fpimm0, use vmv.v.x vd, x0.
def : Pat<(fvti.Vector (int_riscv_vfmv_v_f def : Pat<(fvti.Vector (int_riscv_vfmv_v_f
(fvti.Scalar (fpimm0)), GPR:$vl)), (fvti.Scalar (fpimm0)), GPR:$vl)),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
0, (NoX0 GPR:$vl), fvti.SEW)>; 0, (NoX0 GPR:$vl), fvti.SEW)>;
def : Pat<(fvti.Vector (int_riscv_vfmv_v_f def : Pat<(fvti.Vector (int_riscv_vfmv_v_f
(fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)), (fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)),
(!cast<Instruction>("PseudoVFMV_V_F_" # (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #
!cond(!eq(fvti.Scalar, f16): "F16_",
!eq(fvti.Scalar, f32): "F32_",
!eq(fvti.Scalar, f64): "F64_") #
fvti.LMul.MX) fvti.LMul.MX)
(fvti.Scalar fvti.ScalarRegClass:$rs2), (fvti.Scalar fvti.ScalarRegClass:$rs2),
(NoX0 GPR:$vl), fvti.SEW)>; (NoX0 GPR:$vl), fvti.SEW)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions // 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 17.2. Floating-Point Scalar Move Instructions // 17.2. Floating-Point Scalar Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV, HasStdExtF] in { let Predicates = [HasStdExtV, HasStdExtF] in {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
defvar instr = !cast<Instruction>("PseudoVFMV_F_S_" # defvar instr = !cast<Instruction>("PseudoVFMV_"#fvti.ScalarSuffix#"_S_" #
!cond(!eq(fvti.Scalar, f16): "F16_",
!eq(fvti.Scalar, f32): "F32_",
!eq(fvti.Scalar, f64): "F64_") #
fvti.LMul.MX); fvti.LMul.MX);
def : Pat<(fvti.Scalar (int_riscv_vfmv_f_s (fvti.Vector fvti.RegClass:$rs2))), def : Pat<(fvti.Scalar (int_riscv_vfmv_f_s (fvti.Vector fvti.RegClass:$rs2))),
(instr $rs2, fvti.SEW)>; (instr $rs2, fvti.SEW)>;
def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1), def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1),
(fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)), (fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)),
(!cast<Instruction>("PseudoVFMV_S_F_" # (!cast<Instruction>("PseudoVFMV_S_"#fvti.ScalarSuffix#"_" #
!cond(!eq(fvti.Scalar, f16): "F16_",
!eq(fvti.Scalar, f32): "F32_",
!eq(fvti.Scalar, f64): "F64_") #
fvti.LMul.MX) fvti.LMul.MX)
(fvti.Vector $rs1), (fvti.Vector $rs1),
(fvti.Scalar fvti.ScalarRegClass:$rs2), (fvti.Scalar fvti.ScalarRegClass:$rs2),
(NoX0 GPR:$vl), fvti.SEW)>; (NoX0 GPR:$vl), fvti.SEW)>;
} }
} // Predicates = [HasStdExtV, HasStdExtF] } // Predicates = [HasStdExtV, HasStdExtF]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show All 26 Lines
]>; ]>;
def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>; def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>;
def riscv_trunc_vector : SDNode<"RISCVISD::TRUNCATE_VECTOR", def riscv_trunc_vector : SDNode<"RISCVISD::TRUNCATE_VECTOR",
SDTypeProfile<1, 1, SDTypeProfile<1, 1,
[SDTCisVec<0>, SDTCisVec<1>]>>; [SDTCisVec<0>, SDTCisVec<1>]>>;
class FromFPR32<DAGOperand operand, dag input_dag> {
dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)):
(INSERT_SUBREG (IMPLICIT_DEF), input_dag, sub_32),
!eq(!cast<string>(operand), !cast<string>(FPR16)):
(EXTRACT_SUBREG input_dag, sub_16),
!eq(1, 1):
input_dag);
}
// Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants // Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants
// precedence // precedence
def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>; def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>; def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
// FIXME: We only model FPR32 for V instructions in RISCVInstrInfoV.td.
// FP16/FP32/FP64 registers are alias each other. Convert FPR16 and FPR64
// to FPR32 for V instructions is enough.
class ToFPR32<ValueType type, DAGOperand operand, string name> {
dag ret = !cond(!eq(!cast<string>(operand), !cast<string>(FPR64)):
(EXTRACT_SUBREG !dag(type, [FPR64], [name]), sub_32),
!eq(!cast<string>(operand), !cast<string>(FPR16)):
(SUBREG_TO_REG (i16 -1), !dag(type, [FPR16], [name]), sub_16),
!eq(1, 1):
!dag(type, [operand], [name]));
}
class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> { class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix); dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
} }
multiclass VPatUSLoadStoreSDNode<LLVMType type, multiclass VPatUSLoadStoreSDNode<LLVMType type,
LLVMType mask_type, LLVMType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
▲ Show 20 Lines • Show All 98 Lines • ▼ Show 20 Linesclass VPatBinarySDNode_VF<SDNode vop,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
OutPatFrag avl, OutPatFrag avl,
VReg RetClass, VReg RetClass,
VReg vop_reg_class, VReg vop_reg_class,
DAGOperand xop_kind> : DAGOperand xop_kind> :
Pat<(result_type (vop (vop_type vop_reg_class:$rs1), Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
(vop_type (splat_vector xop_kind:$rs2)))), (vop_type (splat_vector xop_kind:$rs2)))),
(!cast<Instruction>(instruction_name#"_VF_F32_"#vlmul.MX) (!cast<Instruction>(instruction_name#"_"#vlmul.MX)
vop_reg_class:$rs1, vop_reg_class:$rs1,
ToFPR32<xop_type, xop_kind, "rs2">.ret, (xop_type xop_kind:$rs2),
avl, sew)>; avl, sew)>;
multiclass VPatBinaryFPSDNode_VV_VF<SDNode vop, string instruction_name> { multiclass VPatBinaryFPSDNode_VV_VF<SDNode vop, string instruction_name> {
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
def : VPatBinarySDNode_VV<vop, instruction_name, def : VPatBinarySDNode_VV<vop, instruction_name,
vti.Vector, vti.Vector, vti.Mask, vti.SEW, vti.Vector, vti.Vector, vti.Mask, vti.SEW,
vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>; vti.LMul, vti.AVL, vti.RegClass, vti.RegClass>;
def : VPatBinarySDNode_VF<vop, instruction_name, def : VPatBinarySDNode_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,
vti.Vector, vti.Vector, vti.Scalar, vti.Mask, vti.Vector, vti.Vector, vti.Scalar, vti.Mask,
vti.SEW, vti.LMul, vti.AVL, vti.RegClass, vti.RegClass, vti.SEW, vti.LMul, vti.AVL, vti.RegClass, vti.RegClass,
vti.ScalarRegClass>; vti.ScalarRegClass>;
} }
} }
multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> { multiclass VPatBinaryFPSDNode_R_VF<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in foreach fvti = AllFloatVectors in
def : Pat<(fvti.Vector (vop (fvti.Vector (splat_vector fvti.Scalar:$rs2)), def : Pat<(fvti.Vector (vop (fvti.Vector (splat_vector fvti.Scalar:$rs2)),
(fvti.Vector fvti.RegClass:$rs1))), (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_VF_F32_"#fvti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.RegClass:$rs1,
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, (fvti.Scalar fvti.ScalarRegClass:$rs2),
fvti.AVL, fvti.SEW)>; fvti.AVL, fvti.SEW)>;
} }
multiclass VPatIntegerSetCCSDNode_VV<CondCode cc, multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
string instruction_name, string instruction_name,
bit swap = 0> { bit swap = 0> {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX); defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.AVL, fvti.SEW)>; fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.AVL, fvti.SEW)>;
} }
multiclass VPatFPSetCCSDNode_VF<CondCode cc, string instruction_name> { multiclass VPatFPSetCCSDNode_VF<CondCode cc, string instruction_name> {
foreach fvti = AllFloatVectors in foreach fvti = AllFloatVectors in
def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1), def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)), (fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)),
cc)), cc)),
(!cast<Instruction>(instruction_name#"_VF_F32_"#fvti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.RegClass:$rs1,
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, (fvti.Scalar fvti.ScalarRegClass:$rs2),
fvti.AVL, fvti.SEW)>; fvti.AVL, fvti.SEW)>;
} }
multiclass VPatFPSetCCSDNode_FV<CondCode cc, string swapped_op_instruction_name> { multiclass VPatFPSetCCSDNode_FV<CondCode cc, string swapped_op_instruction_name> {
foreach fvti = AllFloatVectors in foreach fvti = AllFloatVectors in
def : Pat<(fvti.Mask (setcc (fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)), def : Pat<(fvti.Mask (setcc (fvti.Vector (splat_vector fvti.ScalarRegClass:$rs2)),
(fvti.Vector fvti.RegClass:$rs1), (fvti.Vector fvti.RegClass:$rs1),
cc)), cc)),
(!cast<Instruction>(swapped_op_instruction_name#"_VF_F32_"#fvti.LMul.MX) (!cast<Instruction>(swapped_op_instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
fvti.RegClass:$rs1, fvti.RegClass:$rs1,
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret, (fvti.Scalar fvti.ScalarRegClass:$rs2),
fvti.AVL, fvti.SEW)>; fvti.AVL, fvti.SEW)>;
} }
multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc, multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
string inst_name, string inst_name,
string swapped_op_inst_name> { string swapped_op_inst_name> {
defm : VPatFPSetCCSDNode_VV<cc, inst_name>; defm : VPatFPSetCCSDNode_VV<cc, inst_name>;
defm : VPatFPSetCCSDNode_VF<cc, inst_name>; defm : VPatFPSetCCSDNode_VF<cc, inst_name>;
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1,
fvti.RegClass:$rs2)), fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
fvti.RegClass:$rs2, fvti.RegClass:$rs1, VMV0:$vm, fvti.RegClass:$rs2, fvti.RegClass:$rs1, VMV0:$vm,
fvti.AVL, fvti.SEW)>; fvti.AVL, fvti.SEW)>;
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
(splat_vector fvti.ScalarRegClass:$rs1), (splat_vector fvti.ScalarRegClass:$rs1),
fvti.RegClass:$rs2)), fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFMERGE_VFM_F32_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)
fvti.RegClass:$rs2, fvti.RegClass:$rs2,
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret, (fvti.Scalar fvti.ScalarRegClass:$rs1),
VMV0:$vm, fvti.AVL, fvti.SEW)>; VMV0:$vm, fvti.AVL, fvti.SEW)>;
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
(splat_vector (fvti.Scalar fpimm0)), (splat_vector (fvti.Scalar fpimm0)),
fvti.RegClass:$rs2)), fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
fvti.RegClass:$rs2, 0, VMV0:$vm, fvti.AVL, fvti.SEW)>; fvti.RegClass:$rs2, 0, VMV0:$vm, fvti.AVL, fvti.SEW)>;
} }
Show All 32 Lines def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)),
simm5:$rs1, vti.AVL, vti.SEW)>; simm5:$rs1, vti.AVL, vti.SEW)>;
} }
} }
} // Predicates = [HasStdExtV, IsRV32] } // Predicates = [HasStdExtV, IsRV32]
let Predicates = [HasStdExtV, HasStdExtF] in { let Predicates = [HasStdExtV, HasStdExtF] in {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)), def : Pat<(fvti.Vector (splat_vector fvti.ScalarRegClass:$rs1)),
(!cast<Instruction>("PseudoVFMV_V_F_F32_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs1">.ret, (fvti.Scalar fvti.ScalarRegClass:$rs1),
fvti.AVL, fvti.SEW)>; fvti.AVL, fvti.SEW)>;
def : Pat<(fvti.Vector (splat_vector (fvti.Scalar fpimm0))), def : Pat<(fvti.Vector (splat_vector (fvti.Scalar fpimm0))),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
0, fvti.AVL, fvti.SEW)>; 0, fvti.AVL, fvti.SEW)>;
} }
} // Predicates = [HasStdExtV, HasStdExtF] } // Predicates = [HasStdExtV, HasStdExtF]
Show All 14 Lines : SDNode<"ISD::EXTRACT_VECTOR_ELT",
SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisPtrTy<2>]>, []>; SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, SDTCisPtrTy<2>]>, []>;
multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> { multiclass VPatInsertExtractElt_XI_Idx<bit IsFloat> {
defvar vtilist = !if(IsFloat, AllFloatVectors, AllIntegerVectors); defvar vtilist = !if(IsFloat, AllFloatVectors, AllIntegerVectors);
defvar insertelt_node = !if(IsFloat, insertelt, riscv_insert_vector_elt); defvar insertelt_node = !if(IsFloat, insertelt, riscv_insert_vector_elt);
defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt); defvar extractelt_node = !if(IsFloat, extractelt, riscv_extract_vector_elt);
foreach vti = vtilist in { foreach vti = vtilist in {
defvar MX = vti.LMul.MX; defvar MX = vti.LMul.MX;
defvar vmv_xf_s_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_F_S_F32_", defvar vmv_xf_s_inst = !cast<Instruction>(!strconcat("PseudoV",
"PseudoVMV_X_S_")#MX); !if(IsFloat, "F", ""),
defvar vmv_s_xf_inst = !cast<Instruction>(!if(IsFloat, "PseudoVFMV_S_F_F32_", "MV_",
"PseudoVMV_S_X_")#MX); vti.ScalarSuffix,
"_S_", MX));
defvar vmv_s_xf_inst = !cast<Instruction>(!strconcat("PseudoV",
!if(IsFloat, "F", ""),
"MV_S_",
vti.ScalarSuffix,
"_", MX));
// Only pattern-match insert/extract-element operations where the index is // Only pattern-match insert/extract-element operations where the index is
// 0. Any other index will have been custom-lowered to slide the vector // 0. Any other index will have been custom-lowered to slide the vector
// correctly into place (and, in the case of insert, slide it back again // correctly into place (and, in the case of insert, slide it back again
// afterwards). // afterwards).
def : Pat<(vti.Scalar (extractelt_node (vti.Vector vti.RegClass:$rs2), 0)), def : Pat<(vti.Scalar (extractelt_node (vti.Vector vti.RegClass:$rs2), 0)),
FromFPR32<vti.ScalarRegClass, (vmv_xf_s_inst vti.RegClass:$rs2, vti.SEW)>;
(vmv_xf_s_inst vti.RegClass:$rs2, vti.SEW)>.ret>;
def : Pat<(vti.Vector (insertelt_node (vti.Vector vti.RegClass:$merge), def : Pat<(vti.Vector (insertelt_node (vti.Vector vti.RegClass:$merge),
vti.ScalarRegClass:$rs1, 0)), vti.ScalarRegClass:$rs1, 0)),
(vmv_s_xf_inst vti.RegClass:$merge, (vmv_s_xf_inst vti.RegClass:$merge,
ToFPR32<vti.Scalar, vti.ScalarRegClass, "rs1">.ret, (vti.Scalar vti.ScalarRegClass:$rs1),
vti.AVL, vti.SEW)>; vti.AVL, vti.SEW)>;
} }
} }
let Predicates = [HasStdExtV] in let Predicates = [HasStdExtV] in
defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/0>; defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/0>;
let Predicates = [HasStdExtV, HasStdExtF] in let Predicates = [HasStdExtV, HasStdExtF] in
defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/1>; defm "" : VPatInsertExtractElt_XI_Idx</*IsFloat*/1>;
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) { define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) {
; CHECK-LABEL: extractelt_nxv1f16_0: ; CHECK-LABEL: extractelt_nxv1f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 0 %r = extractelement <vscale x 1 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) { define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
; CHECK-LABEL: extractelt_nxv1f16_imm: ; CHECK-LABEL: extractelt_nxv1f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vslidedown.vi v25, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 2 %r = extractelement <vscale x 1 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 %idx) { define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1f16_idx: ; CHECK-LABEL: extractelt_nxv1f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 %idx %r = extractelement <vscale x 1 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) { define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
; CHECK-LABEL: extractelt_nxv2f16_0: ; CHECK-LABEL: extractelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 0 %r = extractelement <vscale x 2 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) { define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
; CHECK-LABEL: extractelt_nxv2f16_imm: ; CHECK-LABEL: extractelt_nxv2f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vslidedown.vi v25, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 2 %r = extractelement <vscale x 2 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 %idx) { define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2f16_idx: ; CHECK-LABEL: extractelt_nxv2f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 %idx %r = extractelement <vscale x 2 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) { define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) {
; CHECK-LABEL: extractelt_nxv4f16_0: ; CHECK-LABEL: extractelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 0 %r = extractelement <vscale x 4 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) { define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
; CHECK-LABEL: extractelt_nxv4f16_imm: ; CHECK-LABEL: extractelt_nxv4f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vslidedown.vi v25, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 2 %r = extractelement <vscale x 4 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 %idx) { define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4f16_idx: ; CHECK-LABEL: extractelt_nxv4f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 %idx %r = extractelement <vscale x 4 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) { define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) {
; CHECK-LABEL: extractelt_nxv8f16_0: ; CHECK-LABEL: extractelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 0 %r = extractelement <vscale x 8 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) { define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
; CHECK-LABEL: extractelt_nxv8f16_imm: ; CHECK-LABEL: extractelt_nxv8f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vslidedown.vi v26, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v26 ; CHECK-NEXT: vfmv.f.s fa0, v26
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 2 %r = extractelement <vscale x 8 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 %idx) { define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv8f16_idx: ; CHECK-LABEL: extractelt_nxv8f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vslidedown.vx v26, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v26 ; CHECK-NEXT: vfmv.f.s fa0, v26
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 %idx %r = extractelement <vscale x 8 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) { define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) {
; CHECK-LABEL: extractelt_nxv16f16_0: ; CHECK-LABEL: extractelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 0 %r = extractelement <vscale x 16 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) { define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
; CHECK-LABEL: extractelt_nxv16f16_imm: ; CHECK-LABEL: extractelt_nxv16f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vslidedown.vi v28, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v28 ; CHECK-NEXT: vfmv.f.s fa0, v28
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 2 %r = extractelement <vscale x 16 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 %idx) { define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv16f16_idx: ; CHECK-LABEL: extractelt_nxv16f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vslidedown.vx v28, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v28 ; CHECK-NEXT: vfmv.f.s fa0, v28
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 %idx %r = extractelement <vscale x 16 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) { define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) {
; CHECK-LABEL: extractelt_nxv32f16_0: ; CHECK-LABEL: extractelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x half> %v, i32 0 %r = extractelement <vscale x 32 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) { define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) {
; CHECK-LABEL: extractelt_nxv32f16_imm: ; CHECK-LABEL: extractelt_nxv32f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x half> %v, i32 2 %r = extractelement <vscale x 32 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 %idx) { define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv32f16_idx: ; CHECK-LABEL: extractelt_nxv32f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x half> %v, i32 %idx %r = extractelement <vscale x 32 x half> %v, i32 %idx
ret half %r ret half %r
} }
define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) { define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
; CHECK-LABEL: extractelt_nxv1f32_0: ; CHECK-LABEL: extractelt_nxv1f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 285 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) { define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) {
; CHECK-LABEL: extractelt_nxv1f16_0: ; CHECK-LABEL: extractelt_nxv1f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 0 %r = extractelement <vscale x 1 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) { define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
; CHECK-LABEL: extractelt_nxv1f16_imm: ; CHECK-LABEL: extractelt_nxv1f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vslidedown.vi v25, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 2 %r = extractelement <vscale x 1 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 signext %idx) { define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv1f16_idx: ; CHECK-LABEL: extractelt_nxv1f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x half> %v, i32 %idx %r = extractelement <vscale x 1 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) { define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
; CHECK-LABEL: extractelt_nxv2f16_0: ; CHECK-LABEL: extractelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 0 %r = extractelement <vscale x 2 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) { define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
; CHECK-LABEL: extractelt_nxv2f16_imm: ; CHECK-LABEL: extractelt_nxv2f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vslidedown.vi v25, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 2 %r = extractelement <vscale x 2 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 signext %idx) { define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv2f16_idx: ; CHECK-LABEL: extractelt_nxv2f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x half> %v, i32 %idx %r = extractelement <vscale x 2 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) { define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) {
; CHECK-LABEL: extractelt_nxv4f16_0: ; CHECK-LABEL: extractelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 0 %r = extractelement <vscale x 4 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) { define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
; CHECK-LABEL: extractelt_nxv4f16_imm: ; CHECK-LABEL: extractelt_nxv4f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 2 ; CHECK-NEXT: vslidedown.vi v25, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 2 %r = extractelement <vscale x 4 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 signext %idx) { define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv4f16_idx: ; CHECK-LABEL: extractelt_nxv4f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x half> %v, i32 %idx %r = extractelement <vscale x 4 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) { define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) {
; CHECK-LABEL: extractelt_nxv8f16_0: ; CHECK-LABEL: extractelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 0 %r = extractelement <vscale x 8 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) { define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
; CHECK-LABEL: extractelt_nxv8f16_imm: ; CHECK-LABEL: extractelt_nxv8f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vi v26, v8, 2 ; CHECK-NEXT: vslidedown.vi v26, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v26 ; CHECK-NEXT: vfmv.f.s fa0, v26
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 2 %r = extractelement <vscale x 8 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 signext %idx) { define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv8f16_idx: ; CHECK-LABEL: extractelt_nxv8f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vslidedown.vx v26, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v26 ; CHECK-NEXT: vfmv.f.s fa0, v26
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x half> %v, i32 %idx %r = extractelement <vscale x 8 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) { define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) {
; CHECK-LABEL: extractelt_nxv16f16_0: ; CHECK-LABEL: extractelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 0 %r = extractelement <vscale x 16 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) { define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
; CHECK-LABEL: extractelt_nxv16f16_imm: ; CHECK-LABEL: extractelt_nxv16f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vi v28, v8, 2 ; CHECK-NEXT: vslidedown.vi v28, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v28 ; CHECK-NEXT: vfmv.f.s fa0, v28
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 2 %r = extractelement <vscale x 16 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 signext %idx) { define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv16f16_idx: ; CHECK-LABEL: extractelt_nxv16f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vslidedown.vx v28, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v28 ; CHECK-NEXT: vfmv.f.s fa0, v28
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x half> %v, i32 %idx %r = extractelement <vscale x 16 x half> %v, i32 %idx
ret half %r ret half %r
} }
define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) { define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) {
; CHECK-LABEL: extractelt_nxv32f16_0: ; CHECK-LABEL: extractelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x half> %v, i32 0 %r = extractelement <vscale x 32 x half> %v, i32 0
ret half %r ret half %r
} }
define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) { define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) {
; CHECK-LABEL: extractelt_nxv32f16_imm: ; CHECK-LABEL: extractelt_nxv32f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x half> %v, i32 2 %r = extractelement <vscale x 32 x half> %v, i32 2
ret half %r ret half %r
} }
define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 signext %idx) { define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 signext %idx) {
; CHECK-LABEL: extractelt_nxv32f16_idx: ; CHECK-LABEL: extractelt_nxv32f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x half> %v, i32 %idx %r = extractelement <vscale x 32 x half> %v, i32 %idx
ret half %r ret half %r
} }
define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) { define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
; CHECK-LABEL: extractelt_nxv1f32_0: ; CHECK-LABEL: extractelt_nxv1f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 285 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_0: ; CHECK-LABEL: insertelt_nxv1f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 0
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK-LABEL: insertelt_nxv1f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 3 ; CHECK-NEXT: vslidedown.vi v25, v8, 3
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,tu,mu
; CHECK-NEXT: vslideup.vi v8, v25, 3 ; CHECK-NEXT: vslideup.vi v8, v25, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 %idx) { define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1f16_idx: ; CHECK-LABEL: insertelt_nxv1f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,tu,mu
; CHECK-NEXT: vslideup.vx v8, v25, a0 ; CHECK-NEXT: vslideup.vx v8, v25, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_0: ; CHECK-LABEL: insertelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK-LABEL: insertelt_nxv2f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 3 ; CHECK-NEXT: vslidedown.vi v25, v8, 3
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,tu,mu
; CHECK-NEXT: vslideup.vi v8, v25, 3 ; CHECK-NEXT: vslideup.vi v8, v25, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 %idx) { define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2f16_idx: ; CHECK-LABEL: insertelt_nxv2f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,tu,mu
; CHECK-NEXT: vslideup.vx v8, v25, a0 ; CHECK-NEXT: vslideup.vx v8, v25, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_0: ; CHECK-LABEL: insertelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK-LABEL: insertelt_nxv4f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 3 ; CHECK-NEXT: vslidedown.vi v25, v8, 3
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,tu,mu
; CHECK-NEXT: vslideup.vi v8, v25, 3 ; CHECK-NEXT: vslideup.vi v8, v25, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 %idx) { define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv4f16_idx: ; CHECK-LABEL: insertelt_nxv4f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,tu,mu
; CHECK-NEXT: vslideup.vx v8, v25, a0 ; CHECK-NEXT: vslideup.vx v8, v25, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_0: ; CHECK-LABEL: insertelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK-LABEL: insertelt_nxv8f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vi v26, v8, 3 ; CHECK-NEXT: vslidedown.vi v26, v8, 3
; CHECK-NEXT: vfmv.s.f v26, fa0 ; CHECK-NEXT: vfmv.s.f v26, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,tu,mu
; CHECK-NEXT: vslideup.vi v8, v26, 3 ; CHECK-NEXT: vslideup.vi v8, v26, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 %idx) { define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv8f16_idx: ; CHECK-LABEL: insertelt_nxv8f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vslidedown.vx v26, v8, a0
; CHECK-NEXT: vfmv.s.f v26, fa0 ; CHECK-NEXT: vfmv.s.f v26, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,tu,mu
; CHECK-NEXT: vslideup.vx v8, v26, a0 ; CHECK-NEXT: vslideup.vx v8, v26, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_0: ; CHECK-LABEL: insertelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK-LABEL: insertelt_nxv16f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vi v28, v8, 3 ; CHECK-NEXT: vslidedown.vi v28, v8, 3
; CHECK-NEXT: vfmv.s.f v28, fa0 ; CHECK-NEXT: vfmv.s.f v28, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,tu,mu
; CHECK-NEXT: vslideup.vi v8, v28, 3 ; CHECK-NEXT: vslideup.vi v8, v28, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 %idx) { define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv16f16_idx: ; CHECK-LABEL: insertelt_nxv16f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vslidedown.vx v28, v8, a0
; CHECK-NEXT: vfmv.s.f v28, fa0 ; CHECK-NEXT: vfmv.s.f v28, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,tu,mu
; CHECK-NEXT: vslideup.vx v8, v28, a0 ; CHECK-NEXT: vslideup.vx v8, v28, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_0: ; CHECK-LABEL: insertelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_imm: ; CHECK-LABEL: insertelt_nxv32f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vi v16, v8, 3 ; CHECK-NEXT: vslidedown.vi v16, v8, 3
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 3
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 %idx) { define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv32f16_idx: ; CHECK-LABEL: insertelt_nxv32f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vx v16, v8, a0 ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,tu,mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
▲ Show 20 Lines • Show All 326 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_0: ; CHECK-LABEL: insertelt_nxv1f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 0
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK-LABEL: insertelt_nxv1f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 3 ; CHECK-NEXT: vslidedown.vi v25, v8, 3
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,tu,mu
; CHECK-NEXT: vslideup.vi v8, v25, 3 ; CHECK-NEXT: vslideup.vi v8, v25, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 signext %idx) { define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1f16_idx: ; CHECK-LABEL: insertelt_nxv1f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,tu,mu
; CHECK-NEXT: vslideup.vx v8, v25, a0 ; CHECK-NEXT: vslideup.vx v8, v25, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_0: ; CHECK-LABEL: insertelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK-LABEL: insertelt_nxv2f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 3 ; CHECK-NEXT: vslidedown.vi v25, v8, 3
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,tu,mu
; CHECK-NEXT: vslideup.vi v8, v25, 3 ; CHECK-NEXT: vslideup.vi v8, v25, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 signext %idx) { define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2f16_idx: ; CHECK-LABEL: insertelt_nxv2f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,tu,mu
; CHECK-NEXT: vslideup.vx v8, v25, a0 ; CHECK-NEXT: vslideup.vx v8, v25, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_0: ; CHECK-LABEL: insertelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK-LABEL: insertelt_nxv4f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 3 ; CHECK-NEXT: vslidedown.vi v25, v8, 3
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,tu,mu
; CHECK-NEXT: vslideup.vi v8, v25, 3 ; CHECK-NEXT: vslideup.vi v8, v25, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 signext %idx) { define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4f16_idx: ; CHECK-LABEL: insertelt_nxv4f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vslidedown.vx v25, v8, a0 ; CHECK-NEXT: vslidedown.vx v25, v8, a0
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m1,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,tu,mu
; CHECK-NEXT: vslideup.vx v8, v25, a0 ; CHECK-NEXT: vslideup.vx v8, v25, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_0: ; CHECK-LABEL: insertelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK-LABEL: insertelt_nxv8f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vi v26, v8, 3 ; CHECK-NEXT: vslidedown.vi v26, v8, 3
; CHECK-NEXT: vfmv.s.f v26, fa0 ; CHECK-NEXT: vfmv.s.f v26, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,tu,mu
; CHECK-NEXT: vslideup.vi v8, v26, 3 ; CHECK-NEXT: vslideup.vi v8, v26, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 3
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 signext %idx) { define <vscale x 8 x half> @insertelt_nxv8f16_idx(<vscale x 8 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8f16_idx: ; CHECK-LABEL: insertelt_nxv8f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vslidedown.vx v26, v8, a0 ; CHECK-NEXT: vslidedown.vx v26, v8, a0
; CHECK-NEXT: vfmv.s.f v26, fa0 ; CHECK-NEXT: vfmv.s.f v26, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m2,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,tu,mu
; CHECK-NEXT: vslideup.vx v8, v26, a0 ; CHECK-NEXT: vslideup.vx v8, v26, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_0: ; CHECK-LABEL: insertelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK-LABEL: insertelt_nxv16f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vi v28, v8, 3 ; CHECK-NEXT: vslidedown.vi v28, v8, 3
; CHECK-NEXT: vfmv.s.f v28, fa0 ; CHECK-NEXT: vfmv.s.f v28, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,tu,mu
; CHECK-NEXT: vslideup.vi v8, v28, 3 ; CHECK-NEXT: vslideup.vi v8, v28, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 3
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 signext %idx) { define <vscale x 16 x half> @insertelt_nxv16f16_idx(<vscale x 16 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv16f16_idx: ; CHECK-LABEL: insertelt_nxv16f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vslidedown.vx v28, v8, a0 ; CHECK-NEXT: vslidedown.vx v28, v8, a0
; CHECK-NEXT: vfmv.s.f v28, fa0 ; CHECK-NEXT: vfmv.s.f v28, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m4,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,tu,mu
; CHECK-NEXT: vslideup.vx v8, v28, a0 ; CHECK-NEXT: vslideup.vx v8, v28, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_0: ; CHECK-LABEL: insertelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_imm: ; CHECK-LABEL: insertelt_nxv32f16_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vi v16, v8, 3 ; CHECK-NEXT: vslidedown.vi v16, v8, 3
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vslideup.vi v8, v16, 3 ; CHECK-NEXT: vslideup.vi v8, v16, 3
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 3
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 signext %idx) { define <vscale x 32 x half> @insertelt_nxv32f16_idx(<vscale x 32 x half> %v, half %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv32f16_idx: ; CHECK-LABEL: insertelt_nxv32f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vslidedown.vx v16, v8, a0 ; CHECK-NEXT: vslidedown.vx v16, v8, a0
; CHECK-NEXT: vfmv.s.f v16, fa0 ; CHECK-NEXT: vfmv.s.f v16, fa0
; CHECK-NEXT: vsetvli a1, zero, e16,m8,tu,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,tu,mu
; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: vslideup.vx v8, v16, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
▲ Show 20 Lines • Show All 326 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

Show All 12 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 8 x half> %va, %vb %vc = fcmp oeq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oeq_vf_nxv8f16: ; CHECK-LABEL: fcmp_oeq_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %va, %splat %vc = fcmp oeq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oeq_fv_nxv8f16: ; CHECK-LABEL: fcmp_oeq_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %splat, %va %vc = fcmp oeq <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 8 x half> %va, %vb %vc = fcmp oeq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_oeq_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oeq_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %va, %splat %vc = fcmp oeq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ogt_vv_nxv8f16: ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ogt <vscale x 8 x half> %va, %vb %vc = fcmp ogt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ogt_vf_nxv8f16: ; CHECK-LABEL: fcmp_ogt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %va, %splat %vc = fcmp ogt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ogt_fv_nxv8f16: ; CHECK-LABEL: fcmp_ogt_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %splat, %va %vc = fcmp ogt <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ogt <vscale x 8 x half> %va, %vb %vc = fcmp ogt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ogt_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ogt_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %va, %splat %vc = fcmp ogt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_oge_vv_nxv8f16: ; CHECK-LABEL: fcmp_oge_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oge <vscale x 8 x half> %va, %vb %vc = fcmp oge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oge_vf_nxv8f16: ; CHECK-LABEL: fcmp_oge_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %va, %splat %vc = fcmp oge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oge_fv_nxv8f16: ; CHECK-LABEL: fcmp_oge_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %splat, %va %vc = fcmp oge <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oge <vscale x 8 x half> %va, %vb %vc = fcmp oge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_oge_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oge_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %va, %splat %vc = fcmp oge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_olt_vv_nxv8f16: ; CHECK-LABEL: fcmp_olt_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp olt <vscale x 8 x half> %va, %vb %vc = fcmp olt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_olt_vf_nxv8f16: ; CHECK-LABEL: fcmp_olt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %va, %splat %vc = fcmp olt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_olt_fv_nxv8f16: ; CHECK-LABEL: fcmp_olt_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %splat, %va %vc = fcmp olt <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp olt <vscale x 8 x half> %va, %vb %vc = fcmp olt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_olt_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_olt_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %va, %splat %vc = fcmp olt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ole_vv_nxv8f16: ; CHECK-LABEL: fcmp_ole_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ole <vscale x 8 x half> %va, %vb %vc = fcmp ole <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ole_vf_nxv8f16: ; CHECK-LABEL: fcmp_ole_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %va, %splat %vc = fcmp ole <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ole_fv_nxv8f16: ; CHECK-LABEL: fcmp_ole_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %splat, %va %vc = fcmp ole <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ole <vscale x 8 x half> %va, %vb %vc = fcmp ole <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ole_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ole_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %va, %splat %vc = fcmp ole <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb %vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f16: ; CHECK-LABEL: fcmp_one_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vmfgt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat %vc = fcmp one <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f16: ; CHECK-LABEL: fcmp_one_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vmflt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb %vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_one_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_one_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat %vc = fcmp one <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb %vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ord_vf_nxv8f16: ; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vf v25, v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vmfeq.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: vmand.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ord <vscale x 8 x half> %va, %splat %vc = fcmp ord <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ord_fv_nxv8f16: ; CHECK-LABEL: fcmp_ord_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vf v25, v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vmfeq.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
Show All 13 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb %vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vf v25, v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vmfeq.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: vmand.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
Show All 13 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb %vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vmfgt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat %vc = fcmp ueq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f16: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vmflt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb %vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat %vc = fcmp ueq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb %vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vmfle.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %va, %splat %vc = fcmp ugt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ugt_fv_nxv8f16: ; CHECK-LABEL: fcmp_ugt_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vmfge.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb %vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %va, %splat %vc = fcmp ugt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb %vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uge_vf_nxv8f16: ; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %va, %splat %vc = fcmp uge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uge_fv_nxv8f16: ; CHECK-LABEL: fcmp_uge_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb %vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_uge_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_uge_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %va, %splat %vc = fcmp uge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb %vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ult_vf_nxv8f16: ; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vmfge.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %va, %splat %vc = fcmp ult <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ult_fv_nxv8f16: ; CHECK-LABEL: fcmp_ult_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vmfle.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb %vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ult_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ult_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %va, %splat %vc = fcmp ult <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb %vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ule_vf_nxv8f16: ; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %va, %splat %vc = fcmp ule <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ule_fv_nxv8f16: ; CHECK-LABEL: fcmp_ule_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb %vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ule_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ule_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %va, %splat %vc = fcmp ule <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_une_vv_nxv8f16: ; CHECK-LABEL: fcmp_une_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp une <vscale x 8 x half> %va, %vb %vc = fcmp une <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_une_vf_nxv8f16: ; CHECK-LABEL: fcmp_une_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %va, %splat %vc = fcmp une <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_une_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_une_fv_nxv8f16: ; CHECK-LABEL: fcmp_une_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %splat, %va %vc = fcmp une <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp une <vscale x 8 x half> %va, %vb %vc = fcmp une <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_une_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_une_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %va, %splat %vc = fcmp une <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb %vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uno_vf_nxv8f16: ; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vf v25, v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vmfne.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uno <vscale x 8 x half> %va, %splat %vc = fcmp uno <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uno_fv_nxv8f16: ; CHECK-LABEL: fcmp_uno_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vf v25, v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vmfne.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
Show All 13 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb %vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vf v25, v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vmfne.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
▲ Show 20 Lines • Show All 1,754 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

Show All 12 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 8 x half> %va, %vb %vc = fcmp oeq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oeq_vf_nxv8f16: ; CHECK-LABEL: fcmp_oeq_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %va, %splat %vc = fcmp oeq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oeq_fv_nxv8f16: ; CHECK-LABEL: fcmp_oeq_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %splat, %va %vc = fcmp oeq <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: vmfeq.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oeq <vscale x 8 x half> %va, %vb %vc = fcmp oeq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_oeq_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oeq_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %va, %splat %vc = fcmp oeq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ogt_vv_nxv8f16: ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ogt <vscale x 8 x half> %va, %vb %vc = fcmp ogt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ogt_vf_nxv8f16: ; CHECK-LABEL: fcmp_ogt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %va, %splat %vc = fcmp ogt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ogt_fv_nxv8f16: ; CHECK-LABEL: fcmp_ogt_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %splat, %va %vc = fcmp ogt <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: vmflt.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ogt <vscale x 8 x half> %va, %vb %vc = fcmp ogt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ogt_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ogt_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %va, %splat %vc = fcmp ogt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_oge_vv_nxv8f16: ; CHECK-LABEL: fcmp_oge_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oge <vscale x 8 x half> %va, %vb %vc = fcmp oge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oge_vf_nxv8f16: ; CHECK-LABEL: fcmp_oge_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %va, %splat %vc = fcmp oge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_oge_fv_nxv8f16: ; CHECK-LABEL: fcmp_oge_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %splat, %va %vc = fcmp oge <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: vmfle.vv v0, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp oge <vscale x 8 x half> %va, %vb %vc = fcmp oge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_oge_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_oge_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %va, %splat %vc = fcmp oge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_olt_vv_nxv8f16: ; CHECK-LABEL: fcmp_olt_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp olt <vscale x 8 x half> %va, %vb %vc = fcmp olt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_olt_vf_nxv8f16: ; CHECK-LABEL: fcmp_olt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %va, %splat %vc = fcmp olt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_olt_fv_nxv8f16: ; CHECK-LABEL: fcmp_olt_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %splat, %va %vc = fcmp olt <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp olt <vscale x 8 x half> %va, %vb %vc = fcmp olt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_olt_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_olt_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %va, %splat %vc = fcmp olt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ole_vv_nxv8f16: ; CHECK-LABEL: fcmp_ole_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ole <vscale x 8 x half> %va, %vb %vc = fcmp ole <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ole_vf_nxv8f16: ; CHECK-LABEL: fcmp_ole_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %va, %splat %vc = fcmp ole <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ole_fv_nxv8f16: ; CHECK-LABEL: fcmp_ole_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %splat, %va %vc = fcmp ole <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ole <vscale x 8 x half> %va, %vb %vc = fcmp ole <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ole_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ole_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %va, %splat %vc = fcmp ole <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb %vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f16: ; CHECK-LABEL: fcmp_one_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vmfgt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat %vc = fcmp one <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f16: ; CHECK-LABEL: fcmp_one_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vmflt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb %vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_one_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_one_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat %vc = fcmp one <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb %vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ord_vf_nxv8f16: ; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vf v25, v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vmfeq.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: vmand.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ord <vscale x 8 x half> %va, %splat %vc = fcmp ord <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ord_fv_nxv8f16: ; CHECK-LABEL: fcmp_ord_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vf v25, v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vmfeq.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
Show All 13 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb %vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfeq.vf v25, v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vmfeq.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: vmand.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
Show All 13 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb %vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vmfgt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat %vc = fcmp ueq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f16: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vmflt.vf v26, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb %vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: vmfeq.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat %vc = fcmp ueq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb %vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vmfle.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %va, %splat %vc = fcmp ugt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ugt_fv_nxv8f16: ; CHECK-LABEL: fcmp_ugt_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vmfge.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb %vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ugt_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ugt_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %va, %splat %vc = fcmp ugt <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb %vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uge_vf_nxv8f16: ; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %va, %splat %vc = fcmp uge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uge_fv_nxv8f16: ; CHECK-LABEL: fcmp_uge_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb %vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_uge_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_uge_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: vmfge.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %va, %splat %vc = fcmp uge <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb %vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ult_vf_nxv8f16: ; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vmfge.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %va, %splat %vc = fcmp ult <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ult_fv_nxv8f16: ; CHECK-LABEL: fcmp_ult_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vmfle.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb %vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ult_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ult_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %va, %splat %vc = fcmp ult <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb %vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ule_vf_nxv8f16: ; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %va, %splat %vc = fcmp ule <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ule_fv_nxv8f16: ; CHECK-LABEL: fcmp_ule_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmset.m v26
; CHECK-NEXT: vmxor.mm v0, v25, v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb %vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_ule_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_ule_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: vmfle.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %va, %splat %vc = fcmp ule <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_une_vv_nxv8f16: ; CHECK-LABEL: fcmp_une_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp une <vscale x 8 x half> %va, %vb %vc = fcmp une <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_une_vf_nxv8f16: ; CHECK-LABEL: fcmp_une_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %va, %splat %vc = fcmp une <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_une_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_une_fv_nxv8f16: ; CHECK-LABEL: fcmp_une_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %splat, %va %vc = fcmp une <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans: ; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp une <vscale x 8 x half> %va, %vb %vc = fcmp une <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_une_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_une_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %va, %splat %vc = fcmp une <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb %vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uno_vf_nxv8f16: ; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vf v25, v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vmfne.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uno <vscale x 8 x half> %va, %splat %vc = fcmp uno <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_uno_fv_nxv8f16: ; CHECK-LABEL: fcmp_uno_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vf v25, v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vmfne.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
Show All 13 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb %vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans: ; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vmfne.vf v25, v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vmfne.vv v26, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
▲ Show 20 Lines • Show All 1,754 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x half> %va, %vb %vc = fadd <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv1f16: ; CHECK-LABEL: vfadd_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x half> %va, %splat %vc = fadd <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f16: ; CHECK-LABEL: vfadd_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x half> %va, %vb %vc = fadd <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv2f16: ; CHECK-LABEL: vfadd_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x half> %va, %splat %vc = fadd <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f16: ; CHECK-LABEL: vfadd_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x half> %va, %vb %vc = fadd <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv4f16: ; CHECK-LABEL: vfadd_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x half> %va, %splat %vc = fadd <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f16: ; CHECK-LABEL: vfadd_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: vfadd.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x half> %va, %vb %vc = fadd <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv8f16: ; CHECK-LABEL: vfadd_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %va, %splat %vc = fadd <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfadd_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfadd_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_fv_nxv8f16: ; CHECK-LABEL: vfadd_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %splat, %va %vc = fadd <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv16f16: ; CHECK-LABEL: vfadd_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 16 x half> %va, %vb %vc = fadd <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv16f16: ; CHECK-LABEL: vfadd_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fadd <vscale x 16 x half> %va, %splat %vc = fadd <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv32f16: ; CHECK-LABEL: vfadd_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 32 x half> %va, %vb %vc = fadd <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv32f16: ; CHECK-LABEL: vfadd_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fadd <vscale x 32 x half> %va, %splat %vc = fadd <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 1 x half> %va, %vb %vc = fadd <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfadd_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv1f16: ; CHECK-LABEL: vfadd_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fadd <vscale x 1 x half> %va, %splat %vc = fadd <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfadd_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv2f16: ; CHECK-LABEL: vfadd_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 2 x half> %va, %vb %vc = fadd <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfadd_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv2f16: ; CHECK-LABEL: vfadd_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fadd <vscale x 2 x half> %va, %splat %vc = fadd <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfadd_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv4f16: ; CHECK-LABEL: vfadd_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 4 x half> %va, %vb %vc = fadd <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfadd_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv4f16: ; CHECK-LABEL: vfadd_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fadd <vscale x 4 x half> %va, %splat %vc = fadd <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfadd_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv8f16: ; CHECK-LABEL: vfadd_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: vfadd.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 8 x half> %va, %vb %vc = fadd <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfadd_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv8f16: ; CHECK-LABEL: vfadd_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %va, %splat %vc = fadd <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfadd_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfadd_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfadd_fv_nxv8f16: ; CHECK-LABEL: vfadd_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fadd <vscale x 8 x half> %splat, %va %vc = fadd <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfadd_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv16f16: ; CHECK-LABEL: vfadd_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: vfadd.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 16 x half> %va, %vb %vc = fadd <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfadd_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv16f16: ; CHECK-LABEL: vfadd_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fadd <vscale x 16 x half> %va, %splat %vc = fadd <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfadd_vv_nxv32f16: ; CHECK-LABEL: vfadd_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: vfadd.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fadd <vscale x 32 x half> %va, %vb %vc = fadd <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfadd_vf_nxv32f16: ; CHECK-LABEL: vfadd_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fadd <vscale x 32 x half> %va, %splat %vc = fadd <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x half> %va, %vb %vc = fdiv <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f16: ; CHECK-LABEL: vfdiv_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x half> %va, %splat %vc = fdiv <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f16: ; CHECK-LABEL: vfdiv_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x half> %va, %vb %vc = fdiv <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f16: ; CHECK-LABEL: vfdiv_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x half> %va, %splat %vc = fdiv <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f16: ; CHECK-LABEL: vfdiv_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x half> %va, %vb %vc = fdiv <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f16: ; CHECK-LABEL: vfdiv_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x half> %va, %splat %vc = fdiv <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f16: ; CHECK-LABEL: vfdiv_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: vfdiv.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x half> %va, %vb %vc = fdiv <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f16: ; CHECK-LABEL: vfdiv_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %va, %splat %vc = fdiv <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfdiv_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfdiv_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f16: ; CHECK-LABEL: vfdiv_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %splat, %va %vc = fdiv <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv16f16: ; CHECK-LABEL: vfdiv_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: vfdiv.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 16 x half> %va, %vb %vc = fdiv <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv16f16: ; CHECK-LABEL: vfdiv_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fdiv <vscale x 16 x half> %va, %splat %vc = fdiv <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv32f16: ; CHECK-LABEL: vfdiv_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: vfdiv.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 32 x half> %va, %vb %vc = fdiv <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv32f16: ; CHECK-LABEL: vfdiv_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fdiv <vscale x 32 x half> %va, %splat %vc = fdiv <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 1 x half> %va, %vb %vc = fdiv <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfdiv_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv1f16: ; CHECK-LABEL: vfdiv_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fdiv <vscale x 1 x half> %va, %splat %vc = fdiv <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfdiv_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv2f16: ; CHECK-LABEL: vfdiv_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 2 x half> %va, %vb %vc = fdiv <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfdiv_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv2f16: ; CHECK-LABEL: vfdiv_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fdiv <vscale x 2 x half> %va, %splat %vc = fdiv <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfdiv_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv4f16: ; CHECK-LABEL: vfdiv_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: vfdiv.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 4 x half> %va, %vb %vc = fdiv <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfdiv_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv4f16: ; CHECK-LABEL: vfdiv_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fdiv <vscale x 4 x half> %va, %splat %vc = fdiv <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfdiv_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv8f16: ; CHECK-LABEL: vfdiv_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: vfdiv.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 8 x half> %va, %vb %vc = fdiv <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfdiv_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv8f16: ; CHECK-LABEL: vfdiv_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %va, %splat %vc = fdiv <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfdiv_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfdiv_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_fv_nxv8f16: ; CHECK-LABEL: vfdiv_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fdiv <vscale x 8 x half> %splat, %va %vc = fdiv <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfdiv_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv16f16: ; CHECK-LABEL: vfdiv_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: vfdiv.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 16 x half> %va, %vb %vc = fdiv <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfdiv_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv16f16: ; CHECK-LABEL: vfdiv_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fdiv <vscale x 16 x half> %va, %splat %vc = fdiv <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfdiv_vv_nxv32f16: ; CHECK-LABEL: vfdiv_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: vfdiv.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fdiv <vscale x 32 x half> %va, %vb %vc = fdiv <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfdiv_vf_nxv32f16: ; CHECK-LABEL: vfdiv_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fdiv <vscale x 32 x half> %va, %splat %vc = fdiv <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x half> %va, %vb %vc = fmul <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv1f16: ; CHECK-LABEL: vfmul_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x half> %va, %splat %vc = fmul <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f16: ; CHECK-LABEL: vfmul_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x half> %va, %vb %vc = fmul <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv2f16: ; CHECK-LABEL: vfmul_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x half> %va, %splat %vc = fmul <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f16: ; CHECK-LABEL: vfmul_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x half> %va, %vb %vc = fmul <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv4f16: ; CHECK-LABEL: vfmul_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x half> %va, %splat %vc = fmul <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f16: ; CHECK-LABEL: vfmul_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: vfmul.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x half> %va, %vb %vc = fmul <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv8f16: ; CHECK-LABEL: vfmul_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %va, %splat %vc = fmul <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfmul_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfmul_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_fv_nxv8f16: ; CHECK-LABEL: vfmul_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %splat, %va %vc = fmul <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv16f16: ; CHECK-LABEL: vfmul_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: vfmul.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 16 x half> %va, %vb %vc = fmul <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv16f16: ; CHECK-LABEL: vfmul_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fmul <vscale x 16 x half> %va, %splat %vc = fmul <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv32f16: ; CHECK-LABEL: vfmul_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: vfmul.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 32 x half> %va, %vb %vc = fmul <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv32f16: ; CHECK-LABEL: vfmul_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fmul <vscale x 32 x half> %va, %splat %vc = fmul <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 1 x half> %va, %vb %vc = fmul <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfmul_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv1f16: ; CHECK-LABEL: vfmul_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fmul <vscale x 1 x half> %va, %splat %vc = fmul <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfmul_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv2f16: ; CHECK-LABEL: vfmul_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 2 x half> %va, %vb %vc = fmul <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfmul_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv2f16: ; CHECK-LABEL: vfmul_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fmul <vscale x 2 x half> %va, %splat %vc = fmul <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfmul_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv4f16: ; CHECK-LABEL: vfmul_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: vfmul.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 4 x half> %va, %vb %vc = fmul <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfmul_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv4f16: ; CHECK-LABEL: vfmul_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fmul <vscale x 4 x half> %va, %splat %vc = fmul <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfmul_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv8f16: ; CHECK-LABEL: vfmul_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: vfmul.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 8 x half> %va, %vb %vc = fmul <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfmul_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv8f16: ; CHECK-LABEL: vfmul_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %va, %splat %vc = fmul <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfmul_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfmul_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfmul_fv_nxv8f16: ; CHECK-LABEL: vfmul_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fmul <vscale x 8 x half> %splat, %va %vc = fmul <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfmul_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv16f16: ; CHECK-LABEL: vfmul_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: vfmul.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 16 x half> %va, %vb %vc = fmul <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfmul_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv16f16: ; CHECK-LABEL: vfmul_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fmul <vscale x 16 x half> %va, %splat %vc = fmul <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfmul_vv_nxv32f16: ; CHECK-LABEL: vfmul_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: vfmul.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fmul <vscale x 32 x half> %va, %vb %vc = fmul <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfmul_vf_nxv32f16: ; CHECK-LABEL: vfmul_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fmul <vscale x 32 x half> %va, %splat %vc = fmul <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x half> %va, %vb %vc = fsub <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv1f16: ; CHECK-LABEL: vfsub_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x half> %va, %splat %vc = fsub <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f16: ; CHECK-LABEL: vfsub_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x half> %va, %vb %vc = fsub <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv2f16: ; CHECK-LABEL: vfsub_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x half> %va, %splat %vc = fsub <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f16: ; CHECK-LABEL: vfsub_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x half> %va, %vb %vc = fsub <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv4f16: ; CHECK-LABEL: vfsub_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x half> %va, %splat %vc = fsub <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f16: ; CHECK-LABEL: vfsub_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: vfsub.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x half> %va, %vb %vc = fsub <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv8f16: ; CHECK-LABEL: vfsub_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %va, %splat %vc = fsub <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfsub_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfsub_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_fv_nxv8f16: ; CHECK-LABEL: vfsub_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: vfrsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %splat, %va %vc = fsub <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv16f16: ; CHECK-LABEL: vfsub_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 16 x half> %va, %vb %vc = fsub <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv16f16: ; CHECK-LABEL: vfsub_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fsub <vscale x 16 x half> %va, %splat %vc = fsub <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv32f16: ; CHECK-LABEL: vfsub_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: vfsub.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 32 x half> %va, %vb %vc = fsub <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv32f16: ; CHECK-LABEL: vfsub_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fsub <vscale x 32 x half> %va, %splat %vc = fsub <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 1 x half> %va, %vb %vc = fsub <vscale x 1 x half> %va, %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b) { define <vscale x 1 x half> @vfsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv1f16: ; CHECK-LABEL: vfsub_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = fsub <vscale x 1 x half> %va, %splat %vc = fsub <vscale x 1 x half> %va, %splat
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) { define <vscale x 2 x half> @vfsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv2f16: ; CHECK-LABEL: vfsub_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 2 x half> %va, %vb %vc = fsub <vscale x 2 x half> %va, %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b) { define <vscale x 2 x half> @vfsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv2f16: ; CHECK-LABEL: vfsub_vf_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = fsub <vscale x 2 x half> %va, %splat %vc = fsub <vscale x 2 x half> %va, %splat
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) { define <vscale x 4 x half> @vfsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv4f16: ; CHECK-LABEL: vfsub_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 4 x half> %va, %vb %vc = fsub <vscale x 4 x half> %va, %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b) { define <vscale x 4 x half> @vfsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv4f16: ; CHECK-LABEL: vfsub_vf_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = fsub <vscale x 4 x half> %va, %splat %vc = fsub <vscale x 4 x half> %va, %splat
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x half> @vfsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv8f16: ; CHECK-LABEL: vfsub_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: vfsub.vv v8, v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 8 x half> %va, %vb %vc = fsub <vscale x 8 x half> %va, %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv8f16: ; CHECK-LABEL: vfsub_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %va, %splat %vc = fsub <vscale x 8 x half> %va, %splat
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfsub_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x half> @vfsub_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: vfsub_fv_nxv8f16: ; CHECK-LABEL: vfsub_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: vfrsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fsub <vscale x 8 x half> %splat, %va %vc = fsub <vscale x 8 x half> %splat, %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) { define <vscale x 16 x half> @vfsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv16f16: ; CHECK-LABEL: vfsub_vv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 16 x half> %va, %vb %vc = fsub <vscale x 16 x half> %va, %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b) { define <vscale x 16 x half> @vfsub_vf_nxv16f16(<vscale x 16 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv16f16: ; CHECK-LABEL: vfsub_vf_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = fsub <vscale x 16 x half> %va, %splat %vc = fsub <vscale x 16 x half> %va, %splat
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) { define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb) {
; CHECK-LABEL: vfsub_vv_nxv32f16: ; CHECK-LABEL: vfsub_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: vfsub.vv v8, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fsub <vscale x 32 x half> %va, %vb %vc = fsub <vscale x 32 x half> %va, %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b) { define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b) {
; CHECK-LABEL: vfsub_vf_nxv32f16: ; CHECK-LABEL: vfsub_vf_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = fsub <vscale x 32 x half> %va, %splat %vc = fsub <vscale x 32 x half> %va, %splat
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %va, <vscale x 1 x half> %vb %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %va, <vscale x 1 x half> %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfmerge_fv_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %cond) { define <vscale x 1 x half> @vfmerge_fv_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv1f16: ; CHECK-LABEL: vfmerge_fv_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %splat, <vscale x 1 x half> %va %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %splat, <vscale x 1 x half> %va
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfmerge_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %cond) { define <vscale x 2 x half> @vfmerge_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv2f16: ; CHECK-LABEL: vfmerge_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %va, <vscale x 2 x half> %vb %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %va, <vscale x 2 x half> %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfmerge_fv_nxv2f16(<vscale x 2 x half> %va, half %b, <vscale x 2 x i1> %cond) { define <vscale x 2 x half> @vfmerge_fv_nxv2f16(<vscale x 2 x half> %va, half %b, <vscale x 2 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv2f16: ; CHECK-LABEL: vfmerge_fv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %splat, <vscale x 2 x half> %va %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %splat, <vscale x 2 x half> %va
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfmerge_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %cond) { define <vscale x 4 x half> @vfmerge_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv4f16: ; CHECK-LABEL: vfmerge_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %va, <vscale x 4 x half> %vb %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %va, <vscale x 4 x half> %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfmerge_fv_nxv4f16(<vscale x 4 x half> %va, half %b, <vscale x 4 x i1> %cond) { define <vscale x 4 x half> @vfmerge_fv_nxv4f16(<vscale x 4 x half> %va, half %b, <vscale x 4 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv4f16: ; CHECK-LABEL: vfmerge_fv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %splat, <vscale x 4 x half> %va %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %splat, <vscale x 4 x half> %va
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfmerge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %cond) { define <vscale x 8 x half> @vfmerge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv8f16: ; CHECK-LABEL: vfmerge_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %va, <vscale x 8 x half> %vb %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %cond) { define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv8f16: ; CHECK-LABEL: vfmerge_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %va, <vscale x 16 x half> %vb %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %va, <vscale x 16 x half> %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfmerge_fv_nxv16f16(<vscale x 16 x half> %va, half %b, <vscale x 16 x i1> %cond) { define <vscale x 16 x half> @vfmerge_fv_nxv16f16(<vscale x 16 x half> %va, half %b, <vscale x 16 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv16f16: ; CHECK-LABEL: vfmerge_fv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %splat, <vscale x 16 x half> %va %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %splat, <vscale x 16 x half> %va
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfmerge_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %cond) { define <vscale x 32 x half> @vfmerge_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv32f16: ; CHECK-LABEL: vfmerge_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %va, <vscale x 32 x half> %vb %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %va, <vscale x 32 x half> %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfmerge_fv_nxv32f16(<vscale x 32 x half> %va, half %b, <vscale x 32 x i1> %cond) { define <vscale x 32 x half> @vfmerge_fv_nxv32f16(<vscale x 32 x half> %va, half %b, <vscale x 32 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv32f16: ; CHECK-LABEL: vfmerge_fv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %splat, <vscale x 32 x half> %va %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %splat, <vscale x 32 x half> %va
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

Show All 9 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %va, <vscale x 1 x half> %vb %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %va, <vscale x 1 x half> %vb
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 1 x half> @vfmerge_fv_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %cond) { define <vscale x 1 x half> @vfmerge_fv_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv1f16: ; CHECK-LABEL: vfmerge_fv_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x half> undef, half %b, i32 0 %head = insertelement <vscale x 1 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> undef, <vscale x 1 x i32> zeroinitializer
%vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %splat, <vscale x 1 x half> %va %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %splat, <vscale x 1 x half> %va
ret <vscale x 1 x half> %vc ret <vscale x 1 x half> %vc
} }
define <vscale x 2 x half> @vfmerge_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %cond) { define <vscale x 2 x half> @vfmerge_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv2f16: ; CHECK-LABEL: vfmerge_vv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %va, <vscale x 2 x half> %vb %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %va, <vscale x 2 x half> %vb
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 2 x half> @vfmerge_fv_nxv2f16(<vscale x 2 x half> %va, half %b, <vscale x 2 x i1> %cond) { define <vscale x 2 x half> @vfmerge_fv_nxv2f16(<vscale x 2 x half> %va, half %b, <vscale x 2 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv2f16: ; CHECK-LABEL: vfmerge_fv_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x half> undef, half %b, i32 0 %head = insertelement <vscale x 2 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> undef, <vscale x 2 x i32> zeroinitializer
%vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %splat, <vscale x 2 x half> %va %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %splat, <vscale x 2 x half> %va
ret <vscale x 2 x half> %vc ret <vscale x 2 x half> %vc
} }
define <vscale x 4 x half> @vfmerge_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %cond) { define <vscale x 4 x half> @vfmerge_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv4f16: ; CHECK-LABEL: vfmerge_vv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %va, <vscale x 4 x half> %vb %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %va, <vscale x 4 x half> %vb
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 4 x half> @vfmerge_fv_nxv4f16(<vscale x 4 x half> %va, half %b, <vscale x 4 x i1> %cond) { define <vscale x 4 x half> @vfmerge_fv_nxv4f16(<vscale x 4 x half> %va, half %b, <vscale x 4 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv4f16: ; CHECK-LABEL: vfmerge_fv_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x half> undef, half %b, i32 0 %head = insertelement <vscale x 4 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer
%vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %splat, <vscale x 4 x half> %va %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %splat, <vscale x 4 x half> %va
ret <vscale x 4 x half> %vc ret <vscale x 4 x half> %vc
} }
define <vscale x 8 x half> @vfmerge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %cond) { define <vscale x 8 x half> @vfmerge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv8f16: ; CHECK-LABEL: vfmerge_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %va, <vscale x 8 x half> %vb %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %va, <vscale x 8 x half> %vb
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %cond) { define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv8f16: ; CHECK-LABEL: vfmerge_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va
ret <vscale x 8 x half> %vc ret <vscale x 8 x half> %vc
} }
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %va, <vscale x 16 x half> %vb %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %va, <vscale x 16 x half> %vb
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 16 x half> @vfmerge_fv_nxv16f16(<vscale x 16 x half> %va, half %b, <vscale x 16 x i1> %cond) { define <vscale x 16 x half> @vfmerge_fv_nxv16f16(<vscale x 16 x half> %va, half %b, <vscale x 16 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv16f16: ; CHECK-LABEL: vfmerge_fv_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x half> undef, half %b, i32 0 %head = insertelement <vscale x 16 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> undef, <vscale x 16 x i32> zeroinitializer
%vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %splat, <vscale x 16 x half> %va %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %splat, <vscale x 16 x half> %va
ret <vscale x 16 x half> %vc ret <vscale x 16 x half> %vc
} }
define <vscale x 32 x half> @vfmerge_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %cond) { define <vscale x 32 x half> @vfmerge_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %cond) {
; CHECK-LABEL: vfmerge_vv_nxv32f16: ; CHECK-LABEL: vfmerge_vv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %va, <vscale x 32 x half> %vb %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %va, <vscale x 32 x half> %vb
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
define <vscale x 32 x half> @vfmerge_fv_nxv32f16(<vscale x 32 x half> %va, half %b, <vscale x 32 x i1> %cond) { define <vscale x 32 x half> @vfmerge_fv_nxv32f16(<vscale x 32 x half> %va, half %b, <vscale x 32 x i1> %cond) {
; CHECK-LABEL: vfmerge_fv_nxv32f16: ; CHECK-LABEL: vfmerge_fv_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x half> undef, half %b, i32 0 %head = insertelement <vscale x 32 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> undef, <vscale x 32 x i32> zeroinitializer
%vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %splat, <vscale x 32 x half> %va %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %splat, <vscale x 32 x half> %va
ret <vscale x 32 x half> %vc ret <vscale x 32 x half> %vc
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV32V ; RUN: | FileCheck %s --check-prefix=RV32V
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi lp64d -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64V ; RUN: | FileCheck %s --check-prefix=RV64V
define <vscale x 8 x half> @vsplat_nxv8f16(half %f) { define <vscale x 8 x half> @vsplat_nxv8f16(half %f) {
; RV32V-LABEL: vsplat_nxv8f16: ; RV32V-LABEL: vsplat_nxv8f16:
; RV32V: # %bb.0: ; RV32V: # %bb.0:
; RV32V-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; RV32V-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; RV32V-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; RV32V-NEXT: vfmv.v.f v8, fa0 ; RV32V-NEXT: vfmv.v.f v8, fa0
; RV32V-NEXT: ret ; RV32V-NEXT: ret
; ;
; RV64V-LABEL: vsplat_nxv8f16: ; RV64V-LABEL: vsplat_nxv8f16:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; RV64V-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; RV64V-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; RV64V-NEXT: vfmv.v.f v8, fa0 ; RV64V-NEXT: vfmv.v.f v8, fa0
; RV64V-NEXT: ret ; RV64V-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %f, i32 0 %head = insertelement <vscale x 8 x half> undef, half %f, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
ret <vscale x 8 x half> %splat ret <vscale x 8 x half> %splat
} }
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines