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- D146677: [mlir] Add support for non-f32 polynomial approximation
rGaca34da46da4: Prioritize lowering V{4|16}F32 with blend.
rGb77be0bd5468: [RISCV] Be more explicit string replacements in RISCVInstrInfoVPseudos.td. NFC
D141049: [mlir][nvvm] Add lowering of gpu.printf to nvvm
D138775: [mlir] Support SSA values in runtime op verification errors
rG91594b5b985c: [mlir][nvpu] Prevent F32ToTF32 pattern to generate illegal IR
D131902: [mlir][nvpu] Prevent F32ToTF32 pattern to generate illegal IR
rG14d79afeae63: [mlir][NVGPU] nvgpu.mmasync on F32 through TF32
D130294: [mlir][NVGPU] nvgpu.mmasync on F32 through TF32
rG7faf75bb3e3a: Introduce a new Dense Array attribute
rG508eb41d82ca: Introduce a new Dense Array attribute
D123774: Introduce a new Dense Array attribute
D120427: [mlir][Vector] Prevent AVX2 lowering for non-f32 transpose ops
rGbbddd19ec723: [mlir][math] Expand coverage of atan2 expansion
D118968: [mlir][math] Expand coverage of atan2 expansion
D107548: [mlir] create gpu memset op
D102375: [mlir][tosa] Fix tosa.cast semantics to perform rounding/clipping
D99779: [mlir] Rename linalg.pooling operations to have a FOp postfix for floating point
rGbfc60acd9803: [RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions…
D95404: [RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
D94746: [AMDGPU] Move kill lowering to WQM pass and add live mask tracking
D94604: [CodeGen] Allow parallel uses of a resource
D90738: [RISCV] Support Zfh half-precision floating-point extension.
D90411: TOSA MLIR Dialect
D89642: [VE] Add integer arithmetic vector instructions
D89643: [VE] Add vector comparison and min/max
D82671: [mlir][spirv] Add MatrixTimesMatrix operation
D81218: [mlir] Fix representation of BF16 constants
rGec2e9ce73e6c: [VE] Support I32/F32 registers in assembler parser
D80777: [VE] Support I32/F32 registers in assembler parser
D75352: Add rsqrt op to Standard dialect and lower it to LLVM dialect.
rGb08d2ddd69b4: [ARM,MVE] Add ACLE intrinsics for VCVT.F32.F16 family.
rG69441e53c9f4: [ARM,MVE] Correct MC operands in VCVT.F32.F16. (NFC)
D75253: [ARM,MVE] Correct MC operands in VCVT.F32.F16. (NFC)
rGbbe3f4d9f504: Switch rewriters for relu, relu6, placeholder_input, softmax to patterns.
rG49c4d2a630e2: Fix builder getFloatAttr of double to use F64 type and use fltSemantics in…
rZORG576640f0e32f: Encoding for ARM-mode VADD.F32 instruction.
rZORGe373592258fc: Fix a CQ regression from my patch to split F32/F64 into seperate register…
rZORG0616fa6b9b4c: The selection dag code handles the promotions from F32 to F64 for us, so we…
rG7d424aae138f: AMDGPU/NFC: Simplify VOP_MAC_F16/F32
rG45bc148093dc: AMDGPU: Fix enabling denormals by default on pre-VI targets
rG5647e89f5a63: [X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classes
rGbe9a20688347: [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classes
rG68107657d40f: AMDGPU: Fix gfx801 features
rGe993451f5c5a: [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing
rGabf88a0398d6: X86: Rework inline asm integer register specification.
rG558012a3fca0: Fix a few instances found in SelectionDAG where we were not handling F16 at…
rGb3482af34184: Set trunc store action to Expand for all X86 targets.
rG576640f0e32f: Encoding for ARM-mode VADD.F32 instruction.
rGe373592258fc: Fix a CQ regression from my patch to split F32/F64 into seperate register…
rG0616fa6b9b4c: The selection dag code handles the promotions from F32 to F64 for us, so we…
D54882: [AMDGPU] Add sdwa support for ADD|SUB U64 decomposed Pseudos
rL343254: AMDGPU/NFC: Simplify VOP_MAC_F16/F32
D50467: [SEMA] add more -Wfloat-conversion to compound assigment analysis
rL339278: AMDGPU: Fix enabling denormals by default on pre-VI targets
rC339278: AMDGPU: Fix enabling denormals by default on pre-VI targets
D50376: AMDGPU: Fix enabling denormals by default on pre-VI targets
D47954: Utilize new SDNode flag functionality to expand current support for fdiv
rL332451: [X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classes
rL332376: [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classes
rL311694: AMDGPU: Fix gfx801 features
D36981: AMDGPU: Fix gfx801 features
D25722: Improved cost model for FDIV and FSQRT
rL260560: [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing
D16995: [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsing
rL241002: X86: Rework inline asm integer register specification.
D10813: X86: Rework inline asm integer register specification.
D5125: Make sure to set trunc store action to Expand for all X86 targets.