[RISCV] Add scalable vector icmp ISel patterns

[frasercrmck]

Summary

Original patch by @rogfer01.

The RVV integer comparison instructions are defined in such a way that
many LLVM operations are defined by using the "opposite" comparison
instruction and swapping the operands. This is done in this patch in
most cases, except for the mappings where the immediate range must be
adjusted to accomodate:

• va < i --> vmsle{u}.vi vd, va, i-1, vm
• va >= i --> vmsgt{u}.vi vd, va, i-1, vm

That is left for future optimization; this patch supports all operations
but in the case of the missing mappings the immediate will be moved to
a scalar register first.

Since there are so many condition codes and operand cases to check, it
was decided to reduce the test burden by only testing the "vscale x 8"
vector types.

Authored-by: Roger Ferrer Ibanez <[e-mail]>
Co-Authored-by: Fraser Cormack <[e-mail]>

[frasercrmck]

I'm perhaps testing too many immediates here and should reduce the testing of edge-cases to those instructions that will actually make use of them.

[frasercrmck]

• clarify comment a little

[frasercrmck]

fix an operand class and fix a comment

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

237

What is the splat for VX/VI is on the LHS?

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

237

Ah, good spot. I had assumed constants were canonicalized to the RHS like they are with scalar/fixed-length vectors.

I've now updated llvm::isConstOrConstSplat to handle SPLAT_VECTOR and it "just works". I also see further optimization such as for uge v, 0:

-; CHECK-NEXT:    vmv.v.i v25, 0
-; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    vmset.m v0

That doesn't solve the problem for VX though. I'd probably suggest a custom combine for that, to avoid too much pattern complication. Any thoughts about that?

[frasercrmck]

• Support SPLAT_VECTOR in llvm::isConstOrConstSplat
• Adjust RISCV and AArch64 tests accordingly

[frasercrmck]

@c-rhodes, could you possibly check that the changes to the AArch64 tests are okay? The whilelo one is a bit confusing.

[frasercrmck]

• improve test coverage for setcc with VX/VI on LHS
• cut down on uninteresting VI test cases to compensate

[c-rhodes]

In D94168#2484564, @frasercrmck wrote:

@c-rhodes, could you possibly check that the changes to the AArch64 tests are okay? The whilelo one is a bit confusing.

LGTM! The whilelo is an all false predicate

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

9086

Any special reason this bitsEq but the build_vector code is operator==?

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

237

There's a small possibility of an infinite loop if the generic combines don't know the rule being used. They might end up converting it back and forth. For example, there's a combine that tries to canonicalize setcc with non-constant operands to have the same operand order as an existing isd::sub. Which probably only make sense for scalars where sub produces flags on some targets.

Can you add a FIXME for VX LHS? I think this patch can go in and we can address it as follow up.

[frasercrmck]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

9086

Err no, I think that's a remnant of me trying something else out. I'll fix that up.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

237

Yeah good point. I had woken up today hoping we could just do it in the same place as the constant canonicalization with a target hook (prefersSplatOnRHS(Opcode, Operand) or something) if AArch64 would also benefit from it. It appears they're doing it manually in patterns. It might still reduce their pattern load, but it has taken the impetus out of that idea somewhat.

But for now, I'll enhance the tests and add a FIXME to them like I did with the fp tests.

[frasercrmck]

• update type check
• add scalar/vector fixme to tests

[frasercrmck]

• fix an infinite loop with setcc + two constant splats
• add a regression test for it

[frasercrmck]

update comment a little

[craig.topper]

LGTM with that one auto changed.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

9082

Use EVT here instead of auto.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

bool llvm::isBitwiseNot(SDValue V, bool AllowUndefs) {
   return C && (C->getAPIntValue().countTrailingOnes() >= NumBits);
 }
 
 ConstantSDNode *llvm::isConstOrConstSplat(SDValue N, bool AllowUndefs,
                                           bool AllowTruncation) {
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
     return CN;
 
+  // SplatVectors can truncate their operands. Ignore that case here unless
+  // AllowTruncation is set.
+  if (N->getOpcode() == ISD::SPLAT_VECTOR) {
+    auto VecEltVT = N->getValueType(0).getVectorElementType();
+    if (auto *CN = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
+      EVT CVT = CN->getValueType(0);
+      assert(CVT.bitsGE(VecEltVT) && "Illegal splat_vector element extension");
+      if (AllowTruncation || CVT == VecEltVT)
+        return CN;
+    }
+  }
+
   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
     BitVector UndefElements;
     ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
 
     // BuildVectors can truncate their operands. Ignore that case here unless
     // AllowTruncation is set.
     if (CN && (UndefElements.none() || AllowUndefs)) {
       EVT CVT = CN->getValueType(0);

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
   EVT OpVT = N0.getValueType();
 
   // Constant fold or commute setcc.
   if (SDValue Fold = DAG.FoldSetCC(VT, N0, N1, Cond, dl))
     return Fold;
 
   // Ensure that the constant occurs on the RHS and fold constant comparisons.
   // TODO: Handle non-splat vector constants. All undef causes trouble.
+  // FIXME: We can't yet fold constant scalable vector splats, so avoid an
+  // infinite loop here when we encounter one.
   ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
   if (isConstOrConstSplat(N0) &&
+      (!OpVT.isScalableVector() || !isConstOrConstSplat(N1)) &&
       (DCI.isBeforeLegalizeOps() ||
        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
 
   // If we have a subtract with the same 2 non-constant operands as this setcc
   // -- but in reverse order -- then try to commute the operands of this setcc
   // to match. A matching pair of setcc (cmp) and sub may be combined into 1
   // instruction on some targets.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
 def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
 
 // A mask-vector version of the standard 'vnot' fragment but using splat_vector
 // rather than (the implicit) build_vector
 def riscv_m_vnot : PatFrag<(ops node:$in),
                            (xor node:$in, (splat_vector (XLenVT 1)))>;
 
+class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
+   dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
+}
+
 multiclass VPatUSLoadStoreSDNode<LLVMType type,
                                  LLVMType mask_type,
                                  int sew,
                                  LMULInfo vlmul,
                                  RegisterClass reg_rs1,
                                  VReg reg_class>
 {
   defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
foreach vti = AllIntegerVectors in {
     def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
                               vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
                               vti.LMul, vti.RegClass, vti.RegClass,
                               !cast<ComplexPattern>(SplatPat#_#ImmType),
                               ImmType>;
   }
 }
 
+multiclass VPatIntegerSetCCSDNode_VV<CondCode cc,
+                                     string instruction_name,
+                                     bit swap = 0> {
+  foreach vti = AllIntegerVectors in {
+    defvar instruction = !cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX);
+    def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
+                               (vti.Vector vti.RegClass:$rs2), cc)),
+              SwapHelper<(instruction),
+                         (instruction vti.RegClass:$rs1),
+                         (instruction vti.RegClass:$rs2),
+                         (instruction VLMax, vti.SEW),
+                         swap>.Value>;
+  }
+}
+
+multiclass VPatIntegerSetCCSDNode_XI<CondCode cc,
+                                     string instruction_name,
+                                     string kind,
+                                     ComplexPattern SplatPatKind,
+                                     DAGOperand xop_kind,
+                                     bit swap = 0> {
+  foreach vti = AllIntegerVectors in {
+    defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
+    def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
+                               (vti.Vector (SplatPatKind xop_kind:$rs2)), cc)),
+              SwapHelper<(instruction),
+                         (instruction vti.RegClass:$rs1),
+                         (instruction xop_kind:$rs2),
+                         (instruction VLMax, vti.SEW),
+                         swap>.Value>;
+  }
+}
+
+multiclass VPatIntegerSetCCSDNode_VV_VX_VI<CondCode cc,
+                                           string instruction_name,
+                                           bit swap = 0> {
+  defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
+  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
+                                   SplatPat, GPR, swap>;
+  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
+                                   SplatPat_simm5, simm5, swap>;
+}
+
+multiclass VPatIntegerSetCCSDNode_VV_VX<CondCode cc,
+                                        string instruction_name,
+                                        bit swap = 0> {
+  defm : VPatIntegerSetCCSDNode_VV<cc, instruction_name, swap>;
+  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
+                                   SplatPat, GPR, swap>;
+}
+
+multiclass VPatIntegerSetCCSDNode_VX_VI<CondCode cc,
+                                        string instruction_name,
+                                        bit swap = 0> {
+  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
+                                   SplatPat, GPR, swap>;
+  defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
+                                   SplatPat_simm5, simm5, swap>;
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
 
 // 7.4. Vector Unit-Stride Instructions
 defm "" : VPatUSLoadStoreSDNodes<GPR>;

 defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
 defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
 
 // 12.6. Vector Single-Width Bit Shift Instructions
 defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
 defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
 defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
 
+// 12.8. Vector Integer Comparison Instructions
+defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ,  "PseudoVMSEQ">;
+defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE,  "PseudoVMSNE">;
+
+// FIXME: Support immediate forms of these by choosing SLE decrementing the
+// immediate
+defm "" : VPatIntegerSetCCSDNode_VV_VX<SETLT,  "PseudoVMSLT">;
+defm "" : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
+
+defm "" : VPatIntegerSetCCSDNode_VV<SETGT,  "PseudoVMSLT", /*swap*/1>;
+defm "" : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>;
+defm "" : VPatIntegerSetCCSDNode_VX_VI<SETGT,  "PseudoVMSGT">;
+defm "" : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">;
+
+defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE,  "PseudoVMSLE">;
+defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">;
+
+// FIXME: Support immediate forms of these by choosing SGT and decrementing the
+// immediate
+defm "" : VPatIntegerSetCCSDNode_VV<SETGE,  "PseudoVMSLE", /*swap*/1>;
+defm "" : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
+
 // 12.9. Vector Integer Min/Max Instructions
 defm "" : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
 defm "" : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
 defm "" : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
 defm "" : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
 
 // 12.10. Vector Single-Width Integer Multiply Instructions
 defm "" : VPatBinarySDNode_VV_VX<mul, "PseudoVMUL">;

llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll

; CHECK-NEXT: ret
   %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1> %pg,
                                                                       <vscale x 16 x i8> %a,
                                                                       <vscale x 2 x i64> %splat)
   ret <vscale x 16 x i1> %out
 }
 
 define <vscale x 8 x i1> @ir_cmphi_h(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: ir_cmphi_h
-; CHECK: cmphi p0.h, p0/z, z0.h, #0
+; CHECK: cmpne p0.h, p0/z, z0.h, #0
 ; CHECK-NEXT: ret
   %elt   = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %out = icmp ugt <vscale x 8 x i16> %a, %splat
   ret <vscale x 8 x i1> %out
 }
 
 define <vscale x 8 x i1> @int_cmphi_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
; CHECK-NEXT: ret
   %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmphs.wide.nxv16i8(<vscale x 16 x i1> %pg,
                                                                       <vscale x 16 x i8> %a,
                                                                       <vscale x 2 x i64> %splat)
   ret <vscale x 16 x i1> %out
 }
 
 define <vscale x 8 x i1> @ir_cmphs_h(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: ir_cmphs_h
-; CHECK: cmphs p0.h, p0/z, z0.h, #0
+; CHECK: ptrue p0.h
 ; CHECK-NEXT: ret
   %elt   = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %out = icmp uge <vscale x 8 x i16> %a, %splat
   ret <vscale x 8 x i1> %out
 }
 
 define <vscale x 8 x i1> @int_cmphs_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {
; CHECK-NEXT: ret
   %out = call <vscale x 16 x i1> @llvm.aarch64.sve.cmplo.wide.nxv16i8(<vscale x 16 x i1> %pg,
                                                                       <vscale x 16 x i8> %a,
                                                                       <vscale x 2 x i64> %splat)
   ret <vscale x 16 x i1> %out
 }
 
 define <vscale x 8 x i1> @ir_cmplo_h(<vscale x 8 x i16> %a) {
 ; CHECK-LABEL: ir_cmplo_h
-; CHECK: cmplo p0.h, p0/z, z0.h, #0
+; CHECK: whilelo p0.h, xzr, xzr
 ; CHECK-NEXT: ret
   %elt   = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
   %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %out = icmp ult <vscale x 8 x i16> %a, %splat
   ret <vscale x 8 x i1> %out
 }
 
 define <vscale x 8 x i1> @int_cmplo_h(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) {

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+; FIXME: The scalar/vector operations ('xv' and 'iv' tests) should swap
+; operands and condition codes accordingly in order to generate a 'vx' or 'vi'
+; instruction.
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmseq.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsne.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgtu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsltu.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -16
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 15
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 1
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -15
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsltu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmslt.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -16
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -15
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmslt.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmseq.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsne.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsne.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsne.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgtu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsltu.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -16
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 15
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -15
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsltu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmslt.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -16
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -15
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmslt.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmseq.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsne.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsne.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsne.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgtu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsltu.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -16
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 15
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -15
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsltu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmslt.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -16
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -15
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmslt.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmseq.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmseq.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmseq.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsne.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsne.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsne.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsltu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsltu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsltu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsleu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -16
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 15
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 1
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -15
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsltu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsltu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsltu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsleu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsleu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmslt.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmslt.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmslt.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsle.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -16
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -15
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmslt.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmslt.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmslt.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsle.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsle.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+; Check a setcc with two constant splats, which would previously get stuck in
+; an infinite loop. DAGCombine isn't clever enough to constant-fold
+; splat_vectors but could continuously swap the operands, trying to put the
+; splat on the RHS.
+define <vscale x 8 x i1> @icmp_eq_ii_nxv8i8() {
+; CHECK-LABEL: icmp_eq_ii_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 5
+; CHECK-NEXT:    vmseq.vi v0, v25, 2
+; CHECK-NEXT:    ret
+  %heada = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splata = shufflevector <vscale x 8 x i8> %heada, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %headb = insertelement <vscale x 8 x i8> undef, i8 2, i32 0
+  %splatb = shufflevector <vscale x 8 x i8> %headb, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %splata, %splatb
+  ret <vscale x 8 x i1> %vc
+}
+

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+; FIXME: The scalar/vector operations ('xv' and 'iv' tests) should swap
+; operands and condition codes accordingly in order to generate a 'vx' or 'vi'
+; instruction.
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmseq.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsne.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgtu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsltu.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -16
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 15
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 1
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -15
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i8_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsltu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i8_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsleu.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmslt.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v17, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -16
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -15
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmslt.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v16, v17
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i8> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a0
+; CHECK-NEXT:    vmsle.vv v0, v25, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i8> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 5, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmseq.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsne.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsne.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsne.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgtu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsltu.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -16
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 15
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 1
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -15
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i16_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsltu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i16_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsleu.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmslt.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v18, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -16
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, -15
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.i v26, 0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmslt.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i16_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v16, v18
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i16> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vmsle.vv v0, v26, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i16> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 5, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmseq.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsne.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsne.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsne.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgtu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsltu.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -16
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 15
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 1
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -15
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i32_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsltu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i32_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsleu.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmslt.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v20, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -16
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, -15
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.i v28, 0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmslt.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i32_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vv v0, v16, v20
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i32> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vmsle.vv v0, v28, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i32> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 5, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_eq_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmseq.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp eq <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_eq_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_eq_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmseq.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_eq_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_eq_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_eq_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp eq <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ne_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsne.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp ne <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ne_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsne.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ne_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsne.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ne_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ne_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsne.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ne <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ugt_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsltu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp ugt <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ugt_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgtu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ugt_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsltu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ugt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_uge_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp uge <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_uge_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_uge_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsleu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -16
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 15
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 1
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -15
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_uge_vi_nxv8i64_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp uge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ult_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsltu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp ult <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ult_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ult_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsltu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgtu.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmseq.vi v0, v16, 0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ult_vi_nxv8i64_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsltu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ult <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_ule_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsleu.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp ule <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ule_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsleu.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_ule_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsleu.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_ule_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_ule_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsleu.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp ule <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_sgt_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmslt.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sgt <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sgt_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sgt_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmslt.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sgt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_sge_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %vc = icmp sge <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sge_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sge_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsle.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -16
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, -15
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sge_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sge <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_slt_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmslt.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp slt <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_slt_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_slt_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmslt.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -15
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_iv_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsgt.vi v0, v16, -15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, zero
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_slt_vi_nxv8i64_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmslt.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp slt <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: icmp_sle_vv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmsle.vv v0, v16, v8
+; CHECK-NEXT:    ret
+  %vc = icmp sle <vscale x 8 x i64> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sle_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsle.vx v0, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: icmp_sle_xv_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vmsle.vv v0, v8, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i64> %splat, %va
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 8 x i1> @icmp_sle_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: icmp_sle_vi_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmsle.vi v0, v16, 5
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 5, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = icmp sle <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i1> %vc
+}
+