[RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates

[frasercrmck]

Summary

This patch adds more optimized codegen for the above SETCC forms,
by matching the '.vi' vector forms when the immediate is a 5-bit signed
immediate plus 1. The immediate can be decremented and the corresponding
SET[U]LE or SET[U]GT forms can be matched.

This work was left as a TODO from D94168.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

1156–1161

I was unsure of this function pointer approach but duplicating all of what was selectVSplatSimm5 felt silly. It seemed to generate better code than using std::function<bool(int64_t)> but my X86 isn't where it should be.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

436

Are we confident that we'll never see SETULT/SETUGE with a 0 splat? It doesn't happen for simple cases, but I wonder if the constant can appear later and our target specific nodes like RISCVISD::VMV_V_X_VL or RISCVISD::SPLAT_VECTOR_I64 can prevent setcc optimizations from seeing it.

[frasercrmck]

• rebase
• test and fix for unsigned comparisons with 0

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

436

Yes, you're right. I've fixed that now, and added a couple of tests using the vmv.v.x intrinsic to check it's not misoptimized.

[craig.topper]

LGTM