[RISCV] Set dependency on floating point CSRs, 2/3

[sepavloff]

Summary

This change continues implementation of implicit defs/uses for FP
instructions. It implements the support for binary operations.

[sepavloff]

Reduced number of instruction variants from 3 to 2 (generic and default)

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 multiclass FPFMAD_mc<RISCVOpcode opcode, string OpcodeStr> {
   def _gen : FPFMA_gen<opcode, OpcodeStr, 0b01, FPR64>;
   def _def : FPFMA_def<opcode, OpcodeStr, 0b01, FPR64>;
   def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
                        (!cast<Instruction>(NAME # "_gen")
                         FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
 }
 
+multiclass FPALUD_mc<bits<7> funct7, string OpcodeStr> {
+  def _gen : FPALU_gen<funct7, OpcodeStr, FPR64>;
+  def _def : FPALU_def<funct7, OpcodeStr, FPR64>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                       (!cast<Instruction>(NAME # "_gen")
+                        FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
               (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPALUD_rr_frm<bits<7> funct7, string opcodestr>
-    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd),
-                (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
-                 "$rd, $rs1, $rs2, $funct3">;
-
-class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr>
-    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
-                (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpD_rr<bits<3> funct3, string opcodestr>
     : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
               (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">,
       Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
defm FMADD_D  : FPFMAD_mc<OPC_MADD, "fmadd.d">,
                 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
 defm FMSUB_D  : FPFMAD_mc<OPC_MSUB, "fmsub.d">,
                 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
 defm FNMSUB_D : FPFMAD_mc<OPC_NMSUB, "fnmsub.d">,
                 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
 defm FNMADD_D : FPFMAD_mc<OPC_NMADD, "fnmadd.d">,
                 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
 
-def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">,
+defm FADD_D : FPALUD_mc<0b0000001, "fadd.d">,
               Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def        : FPALUDDynFrmAlias<FADD_D, "fadd.d">;
-def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">,
+defm FSUB_D : FPALUD_mc<0b0000101, "fsub.d">,
               Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def        : FPALUDDynFrmAlias<FSUB_D, "fsub.d">;
-def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">,
+defm FMUL_D : FPALUD_mc<0b0001001, "fmul.d">,
               Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
-def        : FPALUDDynFrmAlias<FMUL_D, "fmul.d">;
-def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">,
+defm FDIV_D : FPALUD_mc<0b0001101, "fdiv.d">,
               Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
-def        : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">;
 
 def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d">,
               Sched<[WriteFSqrt64, ReadFSqrt64]> {
   let rs2 = 0b00000;
 }
 def         : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
 
 def FSGNJ_D  : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">,

 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
-
 let Predicates = [HasStdExtD] in {
 
 /// Float conversion operations
 
 // f64 -> f32, f32 -> f64
 def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
 def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
 
 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
 
-def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
-def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
-def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
-def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
+def : Pat<(fadd FPR64:$rs1, FPR64:$rs2), (FADD_D_def $rs1, $rs2)>;
+def : Pat<(fsub FPR64:$rs1, FPR64:$rs2), (FSUB_D_def $rs1, $rs2)>;
+def : Pat<(fmul FPR64:$rs1, FPR64:$rs2), (FMUL_D_def $rs1, $rs2)>;
+def : Pat<(fdiv FPR64:$rs1, FPR64:$rs2), (FDIV_D_def $rs1, $rs2)>;
 
 def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
 
 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
 
 def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
                        (!cast<Instruction>(NAME # "_gen")
                         FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
 }
 
 class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd),
               (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPALUS_rr_frm<bits<7> funct7, string opcodestr>
-    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR32:$rd),
-                 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr,
-                  "$rd, $rs1, $rs2, $funct3">;
-
-class FPALUSDynFrmAlias<FPALUS_rr_frm Inst, string OpcodeStr>
-    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
-                (Inst FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  class FPALU_gen<bits<7> funct7, string opcodestr, RegisterClass rty>
+      : RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
+                   (ins rty:$rs1, rty:$rs2, frmarg:$funct3), opcodestr,
+                   "$rd, $rs1, $rs2, $funct3"> {
+    let Defs = [FFLAGSReg];
+    let Uses = [FRMReg];
+  }
+
+  class FPALU_def<bits<7> funct7, string opcodestr, RegisterClass rty>
+      : RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
+                   (ins rty:$rs1, rty:$rs2), opcodestr,
+                   "$rd, $rs1, $rs2, rne"> {
+    let funct3 = 0b000;
+  }
+}
+
+multiclass FPALUS_mc<bits<7> funct7, string OpcodeStr> {
+  def _gen : FPALU_gen<funct7, OpcodeStr, FPR32>;
+  def _def : FPALU_def<funct7, OpcodeStr, FPR32>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                       (!cast<Instruction>(NAME # "_gen")
+                        FPR32:$rd, FPR32:$rs1, FPR32:$rs2, 0b111)>;
+}
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
                 RegisterClass rs1ty, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd), (ins rs1ty:$rs1),
               opcodestr, "$rd, $rs1">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
defm FMADD_S  : FPFMAS_mc<OPC_MADD, "fmadd.s">,
                 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
 defm FMSUB_S  : FPFMAS_mc<OPC_MSUB, "fmsub.s">,
                 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
 defm FNMSUB_S : FPFMAS_mc<OPC_NMSUB, "fnmsub.s">,
                 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
 defm FNMADD_S : FPFMAS_mc<OPC_NMADD, "fnmadd.s">,
                 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
 
-def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,
+defm FADD_S : FPALUS_mc<0b0000000, "fadd.s">,
               Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def        : FPALUSDynFrmAlias<FADD_S, "fadd.s">;
-def FSUB_S : FPALUS_rr_frm<0b0000100, "fsub.s">,
+defm FSUB_S : FPALUS_mc<0b0000100, "fsub.s">,
               Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def        : FPALUSDynFrmAlias<FSUB_S, "fsub.s">;
-def FMUL_S : FPALUS_rr_frm<0b0001000, "fmul.s">,
+defm FMUL_S : FPALUS_mc<0b0001000, "fmul.s">,
               Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
-def        : FPALUSDynFrmAlias<FMUL_S, "fmul.s">;
-def FDIV_S : FPALUS_rr_frm<0b0001100, "fdiv.s">,
+defm FDIV_S : FPALUS_mc<0b0001100, "fdiv.s">,
               Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
-def        : FPALUSDynFrmAlias<FDIV_S, "fdiv.s">;
 
 def FSQRT_S : FPUnaryOp_r_frm<0b0101100, FPR32, FPR32, "fsqrt.s">,
               Sched<[WriteFSqrt32, ReadFSqrt32]> {
   let rs2 = 0b00000;
 }
 def         : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>;
 
 def FSGNJ_S  : FPALUS_rr<0b0010000, 0b000, "fsgnj.s">,

 
 /// Floating point constants
 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 
 /// Generic pattern classes
 class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>;
-
 let Predicates = [HasStdExtF] in {
 
 /// Float constants
 def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
 
 /// Float conversion operations
 
 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
 
-def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
-def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
-def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
-def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
+def : Pat<(fadd FPR32:$rs1, FPR32:$rs2), (FADD_S_def $rs1, $rs2)>;
+def : Pat<(fsub FPR32:$rs1, FPR32:$rs2), (FSUB_S_def $rs1, $rs2)>;
+def : Pat<(fmul FPR32:$rs1, FPR32:$rs2), (FMUL_S_def $rs1, $rs2)>;
+def : Pat<(fdiv FPR32:$rs1, FPR32:$rs2), (FDIV_S_def $rs1, $rs2)>;
 
 def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
 
 def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
 def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
 
 def : PatFpr32Fpr32<fcopysign, FSGNJ_S>;
 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

 multiclass FPFMAH_mc<RISCVOpcode opcode, string OpcodeStr> {
   def _gen : FPFMA_gen<opcode, OpcodeStr, 0b10, FPR16>;
   def _def : FPFMA_def<opcode, OpcodeStr, 0b10, FPR16>;
   def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
                        (!cast<Instruction>(NAME # "_gen")
                         FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
 }
 
+multiclass FPALUH_mc<bits<7> funct7, string OpcodeStr> {
+  def _gen : FPALU_gen<funct7, OpcodeStr, FPR16>;
+  def _def : FPALU_def<funct7, OpcodeStr, FPR16>;
+  def      : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
+                       (!cast<Instruction>(NAME # "_gen")
+                        FPR16:$rd, FPR16:$rs1, FPR16:$rs2, 0b111)>;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPALUH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16:$rd),
               (ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPALUH_rr_frm<bits<7> funct7, string opcodestr>
-    : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR16:$rd),
-                 (ins FPR16:$rs1, FPR16:$rs2, frmarg:$funct3), opcodestr,
-                  "$rd, $rs1, $rs2, $funct3">;
-
-class FPALUHDynFrmAlias<FPALUH_rr_frm Inst, string OpcodeStr>
-    : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
-                (Inst FPR16:$rd, FPR16:$rs1, FPR16:$rs2, 0b111)>;
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class FPCmpH_rr<bits<3> funct3, string opcodestr>
     : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
               (ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">,
       Sched<[]>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
defm FMADD_H  : FPFMAH_mc<OPC_MADD, "fmadd.h">,
                 Sched<[]>;
 defm FMSUB_H  : FPFMAH_mc<OPC_MSUB, "fmsub.h">,
                 Sched<[]>;
 defm FNMSUB_H : FPFMAH_mc<OPC_NMSUB, "fnmsub.h">,
                 Sched<[]>;
 defm FNMADD_H : FPFMAH_mc<OPC_NMADD, "fnmadd.h">,
                 Sched<[]>;
 
-def FADD_H : FPALUH_rr_frm<0b0000010, "fadd.h">,
+defm FADD_H : FPALUH_mc<0b0000010, "fadd.h">,
               Sched<[]>;
-def        : FPALUHDynFrmAlias<FADD_H, "fadd.h">;
-def FSUB_H : FPALUH_rr_frm<0b0000110, "fsub.h">,
+defm FSUB_H : FPALUH_mc<0b0000110, "fsub.h">,
               Sched<[]>;
-def        : FPALUHDynFrmAlias<FSUB_H, "fsub.h">;
-def FMUL_H : FPALUH_rr_frm<0b0001010, "fmul.h">,
+defm FMUL_H : FPALUH_mc<0b0001010, "fmul.h">,
               Sched<[]>;
-def        : FPALUHDynFrmAlias<FMUL_H, "fmul.h">;
-def FDIV_H : FPALUH_rr_frm<0b0001110, "fdiv.h">,
+defm FDIV_H : FPALUH_mc<0b0001110, "fdiv.h">,
               Sched<[]>;
-def        : FPALUHDynFrmAlias<FDIV_H, "fdiv.h">;
 
 def FSQRT_H : FPUnaryOp_r_frm<0b0101110, FPR16, FPR16, "fsqrt.h">,
               Sched<[]> {
   let rs2 = 0b00000;
 }
 def         : FPUnaryOpDynFrmAlias<FSQRT_H, "fsqrt.h", FPR16, FPR16>;
 
 def FSGNJ_H  : FPALUH_rr<0b0010010, 0b000, "fsgnj.h">,

 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 /// Generic pattern classes
 class PatFpr16Fpr16<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr16Fpr16DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2, 0b111)>;
-
 let Predicates = [HasStdExtZfh] in {
 
 /// Float constants
 def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>;
 
 /// Float conversion operations
 
 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
 
-def : PatFpr16Fpr16DynFrm<fadd, FADD_H>;
-def : PatFpr16Fpr16DynFrm<fsub, FSUB_H>;
-def : PatFpr16Fpr16DynFrm<fmul, FMUL_H>;
-def : PatFpr16Fpr16DynFrm<fdiv, FDIV_H>;
+def : Pat<(fadd FPR16:$rs1, FPR16:$rs2), (FADD_H_def $rs1, $rs2)>;
+def : Pat<(fsub FPR16:$rs1, FPR16:$rs2), (FSUB_H_def $rs1, $rs2)>;
+def : Pat<(fmul FPR16:$rs1, FPR16:$rs2), (FMUL_H_def $rs1, $rs2)>;
+def : Pat<(fdiv FPR16:$rs1, FPR16:$rs2), (FDIV_H_def $rs1, $rs2)>;
 
 def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>;
 
 def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>;
 def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>;
 
 def : PatFpr16Fpr16<fcopysign, FSGNJ_H>;
 def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>;

llvm/test/CodeGen/RISCV/double-arith.ll

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fadd_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fadd double %a, %b
   ret double %1
 }
 
 define double @fsub_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fsub_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fsub.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fsub.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fsub_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fsub.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fsub.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fsub double %a, %b
   ret double %1
 }
 
 define double @fmul_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fmul_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fmul.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fmul.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fmul_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fmul.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fmul.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fmul double %a, %b
   ret double %1
 }
 
 define double @fdiv_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fdiv_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fdiv.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fdiv.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fdiv_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fdiv.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fdiv.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fdiv double %a, %b
   ret double %1
 }
 
 declare double @llvm.sqrt.f64(double)
 

 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fneg_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft0, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft0, ft0, rne
 ; RV32IFD-NEXT:    fneg.d ft1, ft0
 ; RV32IFD-NEXT:    feq.d a0, ft0, ft1
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fneg_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft0, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft0, ft0, rne
 ; RV64IFD-NEXT:    fneg.d ft1, ft0
 ; RV64IFD-NEXT:    feq.d a0, ft0, ft1
 ; RV64IFD-NEXT:    ret
   %1 = fadd double %a, %a
   %2 = fneg double %1
   %3 = fcmp oeq double %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4

 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fabs.d ft1, ft0
-; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV32IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
-; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fabs.d ft1, ft0
-; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
+; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %1 = fadd double %a, %b
   %2 = call double @llvm.fabs.f64(double %1)
   %3 = fadd double %2, %1
   ret double %3
 }
 

 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fmsub_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a2
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %c_ = fadd double 0.0, %c ; avoid negation using xor
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
   ret double %1
 }
 
 define double @fnmadd_d(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmadd_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV32IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmadd_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a2
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %a_ = fadd double 0.0, %a
   %c_ = fadd double 0.0, %c
   %nega = fsub double -0.0, %a_
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %nega, double %b, double %negc)

 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV32IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmadd_d_2:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fmv.d.x ft1, a2
 ; RV64IFD-NEXT:    fmv.d.x ft2, a1
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %b_ = fadd double 0.0, %b
   %c_ = fadd double 0.0, %c
   %negb = fsub double -0.0, %b_
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %a, double %negb, double %negc)

 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmsub_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %a_ = fadd double 0.0, %a
   %nega = fsub double -0.0, %a_
   %1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
   ret double %1
 }
 
 define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmsub_d_2:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmsub_d_2:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a1
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %b_ = fadd double 0.0, %b
   %negb = fsub double -0.0, %b_
   %1 = call double @llvm.fma.f64(double %a, double %negb, double %c)
   ret double %1
 }

 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV32IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fmsub_d_contract:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a2
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
 ; RV64IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %c_ = fadd double 0.0, %c ; avoid negation using xor
   %1 = fmul contract double %a, %b
   %2 = fsub contract double %1, %c_
   ret double %2
 }
 
 define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmadd_d_contract:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw a4, 8(sp)
 ; RV32IFD-NEXT:    sw a5, 12(sp)
 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
-; RV32IFD-NEXT:    fadd.d ft0, ft0, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft0, ft0, ft3, rne
 ; RV32IFD-NEXT:    fnmadd.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmadd_d_contract:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
-; RV64IFD-NEXT:    fadd.d ft0, ft0, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft0, ft0, ft3, rne
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %a_ = fadd double 0.0, %a ; avoid negation using xor
   %b_ = fadd double 0.0, %b ; avoid negation using xor
   %c_ = fadd double 0.0, %c ; avoid negation using xor
   %1 = fmul contract double %a_, %b_
   %2 = fneg double %1

 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    sw a2, 8(sp)
 ; RV32IFD-NEXT:    sw a3, 12(sp)
 ; RV32IFD-NEXT:    fld ft1, 8(sp)
 ; RV32IFD-NEXT:    sw a0, 8(sp)
 ; RV32IFD-NEXT:    sw a1, 12(sp)
 ; RV32IFD-NEXT:    fld ft2, 8(sp)
 ; RV32IFD-NEXT:    fcvt.d.w ft3, zero
-; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV32IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV32IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV32IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fnmsub_d_contract:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
-; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
-; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
+; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3, rne
+; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3, rne
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0, rne
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
   %a_ = fadd double 0.0, %a ; avoid negation using xor
   %b_ = fadd double 0.0, %b ; avoid negation using xor
   %1 = fmul contract double %a_, %b_
   %2 = fsub contract double %c, %1
   ret double %2
 }

llvm/test/CodeGen/RISCV/float-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction. Most
 ; other files in this folder exercise LLVM IR instructions that don't directly
 ; match a RISC-V instruction.
 
 define float @fadd_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fadd_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fadd_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %b
   ret float %1
 }
 
 define float @fsub_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fsub_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fsub.s ft0, ft1, ft0
+; RV32IF-NEXT:    fsub.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fsub_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fsub.s ft0, ft1, ft0
+; RV64IF-NEXT:    fsub.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fsub float %a, %b
   ret float %1
 }
 
 define float @fmul_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fmul_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fmul.s ft0, ft1, ft0
+; RV32IF-NEXT:    fmul.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmul_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fmul.s ft0, ft1, ft0
+; RV64IF-NEXT:    fmul.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fmul float %a, %b
   ret float %1
 }
 
 define float @fdiv_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fdiv_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fdiv.s ft0, ft1, ft0
+; RV32IF-NEXT:    fdiv.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fdiv_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fdiv.s ft0, ft1, ft0
+; RV64IF-NEXT:    fdiv.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fdiv float %a, %b
   ret float %1
 }
 
 declare float @llvm.sqrt.f32(float)
 

 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fneg_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
-; RV32IF-NEXT:    fadd.s ft0, ft0, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft0, ft0, rne
 ; RV32IF-NEXT:    fneg.s ft1, ft0
 ; RV32IF-NEXT:    feq.s a0, ft0, ft1
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fneg_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
-; RV64IF-NEXT:    fadd.s ft0, ft0, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft0, ft0, rne
 ; RV64IF-NEXT:    fneg.s ft1, ft0
 ; RV64IF-NEXT:    feq.s a0, ft0, ft1
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %a
   %2 = fneg float %1
   %3 = fcmp oeq float %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define float @fsgnjn_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fsgnjn_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fsgnjn.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fsgnjn_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fsgnjn.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = fneg float %1
   %3 = call float @llvm.copysign.f32(float %a, float %2)
   ret float %3
 }
 
 declare float @llvm.fabs.f32(float)
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define float @fabs_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fabs_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fabs.s ft1, ft0
-; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV32IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fabs_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fabs.s ft1, ft0
-; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
+; RV64IF-NEXT:    fadd.s ft0, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = call float @llvm.fabs.f32(float %1)
   %3 = fadd float %2, %1
   ret float %3
 }
 

 
 define float @fmsub_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fmsub_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fmv.w.x ft2, a2
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmsub_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a2
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmadd_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a2
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV32IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmadd_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a2
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %c_ = fadd float 0.0, %c
   %nega = fsub float -0.0, %a_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmadd_s_2:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fmv.w.x ft1, a2
 ; RV32IF-NEXT:    fmv.w.x ft2, a1
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV32IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmadd_s_2:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fmv.w.x ft1, a2
 ; RV64IF-NEXT:    fmv.w.x ft2, a1
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %b_ = fadd float 0.0, %b
   %c_ = fadd float 0.0, %c
   %negb = fsub float -0.0, %b_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
   ret float %1
 }
 
 define float @fnmsub_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmsub_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a2
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmsub_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %a_ = fadd float 0.0, %a
   %nega = fsub float -0.0, %a_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmsub_s_2:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a2
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fmv.w.x ft2, a1
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmsub_s_2:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a1
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %b_ = fadd float 0.0, %b
   %negb = fsub float -0.0, %b_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
   ret float %1
 }

 
 define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fmsub_s_contract:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fmv.w.x ft2, a2
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV32IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmsub_s_contract:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a2
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
 ; RV64IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a, %b
   %2 = fsub contract float %1, %c_
   ret float %2
 }
 
 define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmadd_s_contract:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a2
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
-; RV32IF-NEXT:    fadd.s ft0, ft0, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
+; RV32IF-NEXT:    fadd.s ft0, ft0, ft3, rne
 ; RV32IF-NEXT:    fnmadd.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmadd_s_contract:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
-; RV64IF-NEXT:    fadd.s ft0, ft0, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
+; RV64IF-NEXT:    fadd.s ft0, ft0, ft3, rne
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %a_ = fadd float 0.0, %a ; avoid negation using xor
   %b_ = fadd float 0.0, %b ; avoid negation using xor
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a_, %b_
   %2 = fneg float %1
   %3 = fsub contract float %2, %c_
   ret float %3
 }
 
 define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmsub_s_contract:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a2
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmv.w.x ft3, zero
-; RV32IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV32IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV32IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV32IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV32IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fnmsub_s_contract:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
-; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
-; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
+; RV64IF-NEXT:    fadd.s ft2, ft2, ft3, rne
+; RV64IF-NEXT:    fadd.s ft1, ft1, ft3, rne
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0, rne
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
   %a_ = fadd float 0.0, %a ; avoid negation using xor
   %b_ = fadd float 0.0, %b ; avoid negation using xor
   %1 = fmul contract float %a_, %b_
   %2 = fsub contract float %c, %1
   ret float %2
 }

llvm/test/CodeGen/RISCV/half-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IZFH %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction. Most
 ; other files in this folder exercise LLVM IR instructions that don't directly
 ; match a RISC-V instruction.
 
 define half @fadd_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fadd_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fadd.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fadd_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %b
   ret half %1
 }
 
 define half @fsub_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fsub_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fsub.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fsub.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fsub_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fsub.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fsub.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fsub half %a, %b
   ret half %1
 }
 
 define half @fmul_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fmul_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fmul.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fmul.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fmul_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fmul.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fmul.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fmul half %a, %b
   ret half %1
 }
 
 define half @fdiv_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fdiv_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fdiv.h fa0, fa0, fa1
+; RV32IZFH-NEXT:    fdiv.h fa0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fdiv_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fdiv.h fa0, fa0, fa1
+; RV64IZFH-NEXT:    fdiv.h fa0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fdiv half %a, %b
   ret half %1
 }
 
 declare half @llvm.sqrt.f16(half)
 
 define half @fsqrt_s(half %a) nounwind {
; RV64IZFH-NEXT:    ret
   ret half %1
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define i32 @fneg_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fneg_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa0
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa0, rne
 ; RV32IZFH-NEXT:    fneg.h ft1, ft0
 ; RV32IZFH-NEXT:    feq.h a0, ft0, ft1
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fneg_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa0
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa0, rne
 ; RV64IZFH-NEXT:    fneg.h ft1, ft0
 ; RV64IZFH-NEXT:    feq.h a0, ft0, ft1
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %a
   %2 = fneg half %1
   %3 = fcmp oeq half %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define half @fsgnjn_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fsgnjn_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    fsgnjn.h fa0, fa0, ft0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fsgnjn_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    fsgnjn.h fa0, fa0, ft0
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = fneg half %1
   %3 = call half @llvm.copysign.f16(half %a, half %2)
   ret half %3
 }
 
 declare half @llvm.fabs.f16(half)
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
 define half @fabs_s(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: fabs_s:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV32IZFH-NEXT:    fabs.h ft1, ft0
-; RV32IZFH-NEXT:    fadd.h fa0, ft1, ft0
+; RV32IZFH-NEXT:    fadd.h fa0, ft1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fabs_s:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, fa1, rne
 ; RV64IZFH-NEXT:    fabs.h ft1, ft0
-; RV64IZFH-NEXT:    fadd.h fa0, ft1, ft0
+; RV64IZFH-NEXT:    fadd.h fa0, ft1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = call half @llvm.fabs.f16(half %1)
   %3 = fadd half %2, %1
   ret half %3
 }
 
 declare half @llvm.minnum.f16(half, half)
; RV64IZFH-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 define half @fmsub_s(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fmsub_s:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fmsub_s:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
   ret half %1
 }
 
 define half @fnmadd_s(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmadd_s:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmadd_s:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %c_ = fadd half 0.0, %c
   %nega = fsub half -0.0, %a_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %negc)
   ret half %1
 }
 
 define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmadd_s_2:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa1, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmadd_s_2:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa1, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa1, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, fa0, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %c_ = fadd half 0.0, %c
   %negb = fsub half -0.0, %b_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
   ret half %1
 }
 
 define half @fnmsub_s(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmsub_s:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa0, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa0, ft0, rne
 ; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmsub_s:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa0, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa0, ft0, rne
 ; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa1, fa2, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %nega = fsub half -0.0, %a_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
   ret half %1
 }
 
 define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmsub_s_2:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmsub_s_2:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    fnmsub.h fa0, ft0, fa0, fa2, rne
 ; RV64IZFH-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %negb = fsub half -0.0, %b_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
   ret half %1
 }
 
; RV64IZFH-NEXT:    ret
   %2 = fadd contract half %1, %c
   ret half %2
 }
 
 define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fmsub_s_contract:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fmsub_s_contract:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fmsub.h fa0, fa0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a, %b
   %2 = fsub contract half %1, %c_
   ret half %2
 }
 
 define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmadd_s_contract:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft2, fa1, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft2, fa1, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV32IZFH-NEXT:    fnmadd.h fa0, ft1, ft2, ft0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmadd_s_contract:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft2, fa1, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft2, fa1, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa2, ft0, rne
 ; RV64IZFH-NEXT:    fnmadd.h fa0, ft1, ft2, ft0, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor
   %b_ = fadd half 0.0, %b ; avoid negation using xor
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a_, %b_
   %2 = fneg half %1
   %3 = fsub contract half %2, %c_
   ret half %3
 }
 
 define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmsub_s_contract:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x ft0, zero
-; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV32IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV32IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV32IZFH-NEXT:    fnmsub.h fa0, ft1, ft0, fa2, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmsub_s_contract:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x ft0, zero
-; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0
-; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0
+; RV64IZFH-NEXT:    fadd.h ft1, fa0, ft0, rne
+; RV64IZFH-NEXT:    fadd.h ft0, fa1, ft0, rne
 ; RV64IZFH-NEXT:    fnmsub.h fa0, ft1, ft0, fa2, rne
 ; RV64IZFH-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor
   %b_ = fadd half 0.0, %b ; avoid negation using xor
   %1 = fmul contract half %a_, %b_
   %2 = fsub contract half %c, %1
   ret half %2
 }