[AArch64] Lower fptrunc/fpext from/to FP128t to/from FP16

[zatrazz]

Summary

The compiler-rt part which adds the emitted symbols is handled in
a subsequent patch.

[ostannard]

LGTM

llvm/include/llvm/IR/RuntimeLibcalls.def

 HANDLE_LIBCALL(LLRINT_PPCF128, "llrintl")
 
 // Conversion
 HANDLE_LIBCALL(FPEXT_F32_PPCF128, "__gcc_stoq")
 HANDLE_LIBCALL(FPEXT_F64_PPCF128, "__gcc_dtoq")
 HANDLE_LIBCALL(FPEXT_F80_F128, "__extendxftf2")
 HANDLE_LIBCALL(FPEXT_F64_F128, "__extenddftf2")
 HANDLE_LIBCALL(FPEXT_F32_F128, "__extendsftf2")
+HANDLE_LIBCALL(FPEXT_F16_F128, "__extendhftf2")
 HANDLE_LIBCALL(FPEXT_F32_F64, "__extendsfdf2")
 HANDLE_LIBCALL(FPEXT_F16_F32, "__gnu_h2f_ieee")
 HANDLE_LIBCALL(FPROUND_F32_F16, "__gnu_f2h_ieee")
 HANDLE_LIBCALL(FPROUND_F64_F16, "__truncdfhf2")
 HANDLE_LIBCALL(FPROUND_F80_F16, "__truncxfhf2")
 HANDLE_LIBCALL(FPROUND_F128_F16, "__trunctfhf2")
 HANDLE_LIBCALL(FPROUND_PPCF128_F16, "__trunctfhf2")
 HANDLE_LIBCALL(FPROUND_F64_F32, "__truncdfsf2")

llvm/lib/CodeGen/TargetLoweringBase.cpp

 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 }
 
 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
 /// UNKNOWN_LIBCALL if there is none.
 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
   if (OpVT == MVT::f16) {
     if (RetVT == MVT::f32)
       return FPEXT_F16_F32;
+    if (RetVT == MVT::f128)
+      return FPEXT_F16_F128;
   } else if (OpVT == MVT::f32) {
     if (RetVT == MVT::f64)
       return FPEXT_F32_F64;
     if (RetVT == MVT::f128)
       return FPEXT_F32_F128;
     if (RetVT == MVT::ppcf128)
       return FPEXT_F32_PPCF128;
   } else if (OpVT == MVT::f64) {

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation  ----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
   setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i128, Custom);
   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
   setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
+  setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
   setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
   setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
+  setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
 
   // Variable arguments.
   setOperationAction(ISD::VASTART, MVT::Other, Custom);
   setOperationAction(ISD::VAARG, MVT::Other, Custom);
   setOperationAction(ISD::VACOPY, MVT::Other, Custom);
   setOperationAction(ISD::VAEND, MVT::Other, Expand);

llvm/test/CodeGen/AArch64/arm64-fp128.ll

 ; CHECK-NEXT: %bb.
 ; CHECK-NEXT: mov v[[VAL:[0-9]+]].16b, v0.16b
 ; CHECK-NEXT: [[IFFALSE]]:
 ; CHECK: str q[[VAL]], [{{x[0-9]+}}, :lo12:lhs]
   ret void
 ; CHECK: ret
 }
 
+@varhalf = global half 0.0, align 2
 @varfloat = global float 0.0, align 4
 @vardouble = global double 0.0, align 8
 
 define void @test_round() {
 ; CHECK-LABEL: test_round:
 
   %val = load fp128, fp128* @lhs, align 16
 
+  %half = fptrunc fp128 %val to half
+  store half %half, half* @varhalf, align 2
+; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
+; CHECK: bl __trunctfhf2
+; CHECK: str h0, [{{x[0-9]+}}, :lo12:varhalf]
+
   %float = fptrunc fp128 %val to float
   store float %float, float* @varfloat, align 4
 ; CHECK: bl __trunctfsf2
 ; CHECK: str s0, [{{x[0-9]+}}, :lo12:varfloat]
 
   %double = fptrunc fp128 %val to double
   store double %double, double* @vardouble, align 8
 ; CHECK: bl __trunctfdf2
 ; CHECK: str d0, [{{x[0-9]+}}, :lo12:vardouble]
 
   ret void
 }
 
 define void @test_extend() {
 ; CHECK-LABEL: test_extend:
 
   %val = load fp128, fp128* @lhs, align 16
 
+  %half = load half, half* @varhalf
+  %fromhalf = fpext half %half to fp128
+  store volatile fp128 %fromhalf, fp128* @lhs, align 16
+; CHECK: ldr h0, [{{x[0-9]+}}, :lo12:varhalf]
+; CHECK: bl __extendhftf2
+; CHECK: str q0, [{{x[0-9]+}}, :lo12:lhs]
+
   %float = load float, float* @varfloat
   %fromfloat = fpext float %float to fp128
   store volatile fp128 %fromfloat, fp128* @lhs, align 16
 ; CHECK: bl __extendsftf2
 ; CHECK: str q0, [{{x[0-9]+}}, :lo12:lhs]
 
   %double = load double, double* @vardouble
   %fromdouble = fpext double %double to fp128