Page MenuHomePhabricator

[PowerPC] Add paired vector load and store builtins and intrinsics
ClosedPublic

Authored by bsaleil on Nov 4 2020, 2:08 PM.

Details

Summary

This patch adds the Clang builtins and LLVM intrinsics to load and store vector pairs.

Depends on D90616

Diff Detail

Event Timeline

bsaleil created this revision.Nov 4 2020, 2:08 PM
bsaleil requested review of this revision.Nov 4 2020, 2:08 PM
bsaleil updated this revision to Diff 302983.Nov 4 2020, 3:28 PM

Add builtin tests

bsaleil updated this revision to Diff 303132.Nov 5 2020, 8:42 AM

Add support for the paired load/store intrinsics in PPCLoopInstrFormPrep

bsaleil updated this revision to Diff 303152.Nov 5 2020, 10:00 AM

Rebase patch and add Sema check test case for the builtins

bsaleil updated this revision to Diff 303540.Nov 6 2020, 1:48 PM

Fix unaligned load/store select

lei added inline comments.Nov 9 2020, 6:51 AM
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
2658

There's alot of nested ifs, would it be possible to refactor to have some early exits instead?

llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll
3

BE test?
Can we add -ppc-asm-full-reg-names and update the checks to also ensure the reg info is accurate?

5

is this needed since we have the triple on the run line?

llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
4

BE test?

bsaleil updated this revision to Diff 303973.Nov 9 2020, 1:25 PM

Simplify control flow and improve test cases

bsaleil marked 4 inline comments as done.Nov 9 2020, 1:25 PM
amyk accepted this revision.Nov 10 2020, 7:02 AM

Thanks for fixing for tests and formatting. LGTM if there are no other concerns.

This revision is now accepted and ready to land.Nov 10 2020, 7:02 AM
saghir accepted this revision.Nov 11 2020, 6:50 AM

LGTM.

This revision was landed with ongoing or failed builds.Nov 13 2020, 10:35 AM
This revision was automatically updated to reflect the committed changes.