[AArch64] No NEON instructions to support vector of i64 reductions

[cameron.mcinally]

Summary

There are no NEON instructions to support vector of i64 reductions.

It could be possible to support v2i64 ISD::VECREDUC_ADD with AArch64ISD::UADDLV, but that's probably better left for a separate patch.

Does this change need an XFAIL test? They're not currently tested, so wasn't sure on the protocol for that.

[efriedma]

It appears lowering for v2i64 VECREDUCE_ADD currently works correctly; it produces an addp. It appears v2i64 VECREDUCE_SMAX is currently broken. Does this patch change either of those?

[cameron.mcinally]

You're right about v2i64 UADDV. The existing test didn't catch my regression, so I added a new CHECK line to that test. Also added a line to Custom lower that as before.

v2i64 *MAXV currently gives a Cannot select. That makes sense since *MAXP also doesn't support i64.

[efriedma]

v2i64 *MAXV currently gives a Cannot select. That makes sense since *MAXP also doesn't support i64.

What happens if someone tries to use llvm.experimental.vector.reduce.smax.v2i64 with this patch? I guess this change stops us from generating MAXV, but what happens instead? Can we write a test for that?

[cameron.mcinally]

How about something like this? Not really exhaustive coverage, but it matches the current legalization tests for the reduce intrinsics.

[efriedma]

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasNEON()) {
 
     // AArch64 doesn't have MUL.2d:
     setOperationAction(ISD::MUL, MVT::v2i64, Expand);
     // Custom handling for some quad-vector types to detect MULL.
     setOperationAction(ISD::MUL, MVT::v8i16, Custom);
     setOperationAction(ISD::MUL, MVT::v4i32, Custom);
     setOperationAction(ISD::MUL, MVT::v2i64, Custom);
 
+    // Saturates
     for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
                     MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
-      // Vector reductions
+      setOperationAction(ISD::SADDSAT, VT, Legal);
+      setOperationAction(ISD::UADDSAT, VT, Legal);
+      setOperationAction(ISD::SSUBSAT, VT, Legal);
+      setOperationAction(ISD::USUBSAT, VT, Legal);
+    }
+
+    for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
+                    MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
       setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
       setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
-
-      // Saturates
-      setOperationAction(ISD::SADDSAT, VT, Legal);
-      setOperationAction(ISD::UADDSAT, VT, Legal);
-      setOperationAction(ISD::SSUBSAT, VT, Legal);
-      setOperationAction(ISD::USUBSAT, VT, Legal);
     }
     for (MVT VT : { MVT::v4f16, MVT::v2f32,
                     MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
       setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
     }
 
     setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);