[AArch64] No NEON instructions to support vector of i64 reductions

[cameron.mcinally]

Summary

There are no NEON instructions to support vector of i64 reductions.

It could be possible to support v2i64 ISD::VECREDUC_ADD with AArch64ISD::UADDLV, but that's probably better left for a separate patch.

Does this change need an XFAIL test? They're not currently tested, so wasn't sure on the protocol for that.

[efriedma]

It appears lowering for v2i64 VECREDUCE_ADD currently works correctly; it produces an addp. It appears v2i64 VECREDUCE_SMAX is currently broken. Does this patch change either of those?

[cameron.mcinally]

You're right about v2i64 UADDV. The existing test didn't catch my regression, so I added a new CHECK line to that test. Also added a line to Custom lower that as before.

v2i64 *MAXV currently gives a Cannot select. That makes sense since *MAXP also doesn't support i64.

[efriedma]

v2i64 *MAXV currently gives a Cannot select. That makes sense since *MAXP also doesn't support i64.

What happens if someone tries to use llvm.experimental.vector.reduce.smax.v2i64 with this patch? I guess this change stops us from generating MAXV, but what happens instead? Can we write a test for that?

[cameron.mcinally]

How about something like this? Not really exhaustive coverage, but it matches the current legalization tests for the reduce intrinsics.

[efriedma]

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (Subtarget->hasNEON()) {
 
     // AArch64 doesn't have MUL.2d:
     setOperationAction(ISD::MUL, MVT::v2i64, Expand);
     // Custom handling for some quad-vector types to detect MULL.
     setOperationAction(ISD::MUL, MVT::v8i16, Custom);
     setOperationAction(ISD::MUL, MVT::v4i32, Custom);
     setOperationAction(ISD::MUL, MVT::v2i64, Custom);
 
+    // Saturates
     for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
                     MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
-      // Vector reductions
-      setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
-      setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
-      setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
-      setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
-      setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
-
-      // Saturates
       setOperationAction(ISD::SADDSAT, VT, Legal);
       setOperationAction(ISD::UADDSAT, VT, Legal);
       setOperationAction(ISD::SSUBSAT, VT, Legal);
       setOperationAction(ISD::USUBSAT, VT, Legal);
     }
+
+    // Vector reductions
     for (MVT VT : { MVT::v4f16, MVT::v2f32,
                     MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
       setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
     }
+    for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
+                    MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
+      setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
+    }
+    setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom);
 
     setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
     setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
     // Likewise, narrowing and extending vector loads/stores aren't handled
     // directly.
     for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
       setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
 

llvm/test/CodeGen/AArch64/aarch64-addv.ll

; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
   %bin.rdx = load <4 x i32>, <4 x i32>* %arr
   %r = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %bin.rdx)
   ret i32 %r
 }
 
 define i64 @add_D(<2 x i64>* %arr)  {
 ; CHECK-LABEL: add_D
 ; CHECK-NOT: addv
+; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
   %bin.rdx = load <2 x i64>, <2 x i64>* %arr
   %r = call i64 @llvm.experimental.vector.reduce.add.v2i64(<2 x i64> %bin.rdx)
   ret i64 %r
 }
 
 declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
 
 define i32 @oversized_ADDV_256(i8* noalias nocapture readonly %arg1, i8* noalias nocapture readonly %arg2) {

llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
 
 declare i1 @llvm.experimental.vector.reduce.umax.v1i1(<1 x i1> %a)
 declare i8 @llvm.experimental.vector.reduce.umax.v1i8(<1 x i8> %a)
 declare i16 @llvm.experimental.vector.reduce.umax.v1i16(<1 x i16> %a)
 declare i24 @llvm.experimental.vector.reduce.umax.v1i24(<1 x i24> %a)
 declare i32 @llvm.experimental.vector.reduce.umax.v1i32(<1 x i32> %a)
 declare i64 @llvm.experimental.vector.reduce.umax.v1i64(<1 x i64> %a)
 declare i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
 
+declare i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> %a)
 declare i8 @llvm.experimental.vector.reduce.umax.v3i8(<3 x i8> %a)
 declare i8 @llvm.experimental.vector.reduce.umax.v9i8(<9 x i8> %a)
 declare i32 @llvm.experimental.vector.reduce.umax.v3i32(<3 x i32> %a)
 declare i1 @llvm.experimental.vector.reduce.umax.v4i1(<4 x i1> %a)
 declare i24 @llvm.experimental.vector.reduce.umax.v4i24(<4 x i24> %a)
 declare i128 @llvm.experimental.vector.reduce.umax.v2i128(<2 x i128> %a)
 declare i32 @llvm.experimental.vector.reduce.umax.v16i32(<16 x i32> %a)
 

 define i128 @test_v1i128(<1 x i128> %a) nounwind {
 ; CHECK-LABEL: test_v1i128:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
   %b = call i128 @llvm.experimental.vector.reduce.umax.v1i128(<1 x i128> %a)
   ret i128 %b
 }
 
+; No i64 vector support for UMAX.
+define i64 @test_v2i64(<2 x i64> %a) nounwind {
+; CHECK-LABEL: test_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:   mov     x8, v0.d[1]
+; CHECK-NEXT:   fmov    x9, d0
+; CHECK-NEXT:   cmp     x9, x8
+; CHECK-NEXT:   csel    x0, x9, x8, hi
+; CHECK-NEXT:   ret
+  %b = call i64 @llvm.experimental.vector.reduce.umax.v2i64(<2 x i64> %a)
+  ret i64 %b
+}
+
 define i8 @test_v3i8(<3 x i8> %a) nounwind {
 ; CHECK-LABEL: test_v3i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    mov v0.h[0], w0
 ; CHECK-NEXT:    mov v0.h[1], w1
 ; CHECK-NEXT:    mov v0.h[2], w2
 ; CHECK-NEXT:    bic v0.4h, #255, lsl #8