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[Legalize][ARM][X86] Add float legalization for VECREDUCE
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Authored by nikic on Sep 12 2020, 1:54 PM.

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Summary

This adds SoftenFloatRes, PromoteFloatRes and SoftPromoteHalfRes legalizations for VECREDUCE, to fill the remaining hole in the SDAG legalization. These legalizations simplify expand the reduction and let it be recursively legalized. For the PromoteFloatRes case at least it is possible to do better than that, but it's pretty tricky (because we need to consider the interaction of three different vector legalizations and the type promotion) and probably not really worthwhile.

I haven't added ExpandFloatRes support, as I am not familiar with ppc_fp128.

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nikic created this revision.Sep 12 2020, 1:54 PM
nikic requested review of this revision.Sep 12 2020, 1:54 PM
nikic updated this revision to Diff 291420.Sep 12 2020, 2:57 PM

Add missing cases

nikic updated this revision to Diff 291455.Sep 13 2020, 6:26 AM
nikic retitled this revision from [LegalizeFloatType][ARM] Add float legalization for VECREDUCE to [Legalize][ARM][X86] Add float legalization for VECREDUCE.
nikic edited the summary of this revision. (Show Details)

Add SoftPromoteHalfRes as well. As we do expand non-fast reductions on X86, we can run into it there. The added tests were previously asserting.

dmgreen accepted this revision.Sep 14 2020, 9:34 AM

This looks good to me. It may be worth adding some fmin/fmax tests with the fadds, just because they can end up being a little different.

This revision is now accepted and ready to land.Sep 14 2020, 9:34 AM
This revision was automatically updated to reflect the committed changes.