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[SVE] Replace remaining _MERGE_OP1 nodes with _PRED variants.
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Authored by paulwalker-arm on Aug 3 2020, 10:50 AM.

Details

Summary

This is the final bit of work to relax the register allocation
requirements when code generating normal LLVM IR, which rarely
care about the result of inactive lanes. By using _PRED nodes
we can make better use of SVE's reversed instructions.

Also removes a redundant parameter from the min/max tests.

Diff Detail

Unit TestsFailed

Event Timeline

paulwalker-arm created this revision.Aug 3 2020, 10:50 AM
paulwalker-arm requested review of this revision.Aug 3 2020, 10:50 AM
efriedma accepted this revision.Aug 3 2020, 1:11 PM

LGTM

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
11960

You don't need to change it here, but should we be lowering aarch64_sve_ptrue to AArch64ISD::PTRUE, instead of supporting both forms through isel?

This revision is now accepted and ready to land.Aug 3 2020, 1:11 PM
This revision was landed with ongoing or failed builds.Aug 4 2020, 3:21 AM
This revision was automatically updated to reflect the committed changes.
paulwalker-arm added inline comments.Aug 4 2020, 3:24 AM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
11960

This lowering is already done today, I was just being unnecessarily cautious. I removed the aarch64_sve_ptrue based path with no ill effects.