[llc] (almost) remove `--print-machineinstrs`

[ychen]

Summary

Its effect could be achieved by
-stop-after,-print-after,-print-after-all. But a few tests need to
print MIR after ISel which could not be done with
-print-after/-stop-after since isel pass does not have commandline name.
That's the reason --print-machineinstrs is downgraded to
--print-after-isel in this patch. --print-after-isel could be
removed after we switch to new pass manager since isel pass would have a
commandline text name to use print-after or equivalent switches.

The motivation of this patch is to reduce tests dependency on
would-be-deprecated feature.

[dsanders]

I was worried for a moment that we'd be losing the ability to print between all machine passes but it looks like -print-after-all covers that now (I don't think that was always the case). So long as we aren't losing any inter-pass dumps this LGTM but I'd suggest giving it a few days to see if anyone was using this in a way that isn't evident from the tests.

-print-after/-stop-after since isel pass does not have commandline name.

IIRC, there's something weird going on in this area. I vaguely remember a problem I never got to the bottom of where there was no name when AMDGPU was omitted but when it was compiled, everybody's pass was called amdgpu-isel. It had something to do with AMDGPU needing additional dependencies and using INITIALIZE_PASS to get them.

llvm/lib/CodeGen/TargetPassConfig.cpp

144–148

There's a typo (:->') but also there's more tests affected than just the two. Probably best to keep the exact number vague

[ychen]

In D83275#2134936, @dsanders wrote:

I was worried for a moment that we'd be losing the ability to print between all machine passes but it looks like -print-after-all covers that now (I don't think that was always the case). So long as we aren't losing any inter-pass dumps this LGTM but I'd suggest giving it a few days to see if anyone was using this in a way that isn't evident from the tests.

-print-after/-stop-after since isel pass does not have commandline name.

IIRC, there's something weird going on in this area. I vaguely remember a problem I never got to the bottom of where there was no name when AMDGPU was omitted but when it was compiled, everybody's pass was called amdgpu-isel. It had something to do with AMDGPU needing additional dependencies and using INITIALIZE_PASS to get them.

I don't know if it is the cause but AMDGPUDAGToDAGISel::ID is actually SelectionDAGISel::ID.

[arsenm]

I've never used -print-machineinstrs and was surprised it existed last time I noticed it

llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll

1

This test should probably be switched to stop-after and MIR

llvm/test/DebugInfo/WebAssembly/dbg-value-move-2.ll

1–2

Ditto

llvm/test/DebugInfo/WebAssembly/dbg-value-move.ll

1–2

Ditto

[dsanders]

In D83275#2134966, @ychen wrote:

In D83275#2134936, @dsanders wrote:

I was worried for a moment that we'd be losing the ability to print between all machine passes but it looks like -print-after-all covers that now (I don't think that was always the case). So long as we aren't losing any inter-pass dumps this LGTM but I'd suggest giving it a few days to see if anyone was using this in a way that isn't evident from the tests.

-print-after/-stop-after since isel pass does not have commandline name.

IIRC, there's something weird going on in this area. I vaguely remember a problem I never got to the bottom of where there was no name when AMDGPU was omitted but when it was compiled, everybody's pass was called amdgpu-isel. It had something to do with AMDGPU needing additional dependencies and using INITIALIZE_PASS to get them.

I don't know if it is the cause but AMDGPUDAGToDAGISel::ID is actually SelectionDAGISel::ID.

That could be it. Those ID's are the keys into the pass registry so that would cause AMDGPUDAGToDAGISel to register a PassInfo for SelectionDAGISel with the argument "amdgpu-isel" which would be how other targets are able to use it. Without it compiled in, there would be no PassInfo registered leaving getPassIDFromName() unable to find it.

[ychen]

llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll

1

There is a general problem is that -printer-after uses MachineFunctionPrinterPass(MachineFunction::print) whereas -stop-after uses MIRPrinter(in MIR serialization format). The general question is could we just use only of them? thoughts? maybe MIRPrinter since it *seems* the information it prints is a superset of what MachineFunction::print prints.

For this particular test, I could use stop-after because the check lines are simple. For the next two, using stop-after makes the tests fail. How about I add FIXME instead?

[arsenm]

llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll

1

Yes, the output of the machine debug dumps and MIR dumps are slightly different. They're gradually converging. Eventually we should probably only have the MIR dumps, with some simplifications for debug printing cases (e.g. prune some of the function metadata in the common cases)

I think there's no legitimate reason for a test to be scraping the machine debug dumps when it could be checking the MIR instead.

[arsenm]

llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll

1

Why do they fail? The "After.." checks can just be deleted.

There may may be a complication for the DBG_VALUE, I think there are some issues with serialization of debug info in MIR still

[ychen]

llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll

1

Yes, for dbg-value-move-2.ll, fib2.c:6:7 is checked.

[arsenm]

llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll

1

Yes, this is just a MIR printer bug

[ychen]

• add FIXME
• fix typo

[arsenm]

llvm/lib/CodeGen/TargetPassConfig.cpp

144–148

Or GlobalISel, whichever gets there first...

llvm/test/CodeGen/ARM/taildup-branch-weight.ll

0–1

Most of these still look like they can easily be replaced with stop-after

[ychen]

• use -stop-after where possible
• update comment

[arsenm]

LGTM

llvm/docs/CommandGuide/llc.rst

 .. option:: -remarks-section
 
  Emit the __remarks (MachO) section which contains metadata about remark
  diagnostics.
 
 Tuning/Configuration Options
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. option:: --print-machineinstrs
+.. option:: --print-after-isel
 
- Print generated machine code between compilation phases (useful for debugging).
+ Print generated machine code after instruction selection (useful for debugging).
 
 .. option:: --regalloc=<allocator>
 
  Specify the register allocator to use.
  Valid register allocators are:
 
  *basic*
 

llvm/docs/CommandGuide/lli.rst

  .. code-block:: text
 
       =default: Best scheduler for the target
       =none: No scheduling: breadth first sequencing
       =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
       =simple-noitin: Simple two pass scheduling: Same as simple except using generic latency
       =list-burr: Bottom-up register reduction list scheduling
       =list-tdrr: Top-down register reduction list scheduling
-      =list-td: Top-down list scheduler -print-machineinstrs - Print generated machine code
+      =list-td: Top-down list scheduler
 
 .. option:: -regalloc=allocator
 
  Register allocator to use (default=linearscan)
 
  .. code-block:: text
 
       =bigblock: Big-block register allocator

llvm/include/llvm/CodeGen/TargetPassConfig.h

public:
 
   /// Allow the target to override a specific pass without overriding the pass
   /// pipeline. When passes are added to the standard pipeline at the
   /// point where StandardID is expected, add TargetID in its place.
   void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
 
   /// Insert InsertedPassID pass after TargetPassID pass.
   void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
-                  bool VerifyAfter = true, bool PrintAfter = true);
+                  bool VerifyAfter = true);
 
   /// Allow the target to enable a specific standard pass by default.
   void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
 
   /// Allow the target to disable a specific standard pass by default.
   void disablePass(AnalysisID PassID) {
     substitutePass(PassID, IdentifyingPassPtr());
   }
public:
   void addStripDebugPass();
 
   /// Add standard passes before a pass that's about to be added. For example,
   /// the DebugifyMachineModulePass if it is enabled.
   void addMachinePrePasses(bool AllowDebugify = true);
 
   /// Add standard passes after a pass that has just been added. For example,
   /// the MachineVerifier if it is enabled.
-  void addMachinePostPasses(const std::string &Banner, bool AllowPrint = true,
-                            bool AllowVerify = true, bool AllowStrip = true);
+  void addMachinePostPasses(const std::string &Banner, bool AllowVerify = true,
+                            bool AllowStrip = true);
 
   /// Check whether or not GlobalISel should abort on error.
   /// When this is disabled, GlobalISel will fall back on SDISel instead of
   /// erroring out.
   bool isGlobalISelAbortEnabled() const;
 
   /// Check whether or not a diagnostic should be emitted when GlobalISel
   /// uses the fallback path. In other words, it will emit a diagnostic
protected:
   // `addPreEmitPass` *should* be but in reality isn't.
   virtual void addPreEmitPass2() {}
 
   /// Utilities for targets to add passes to the pass manager.
   ///
 
   /// Add a CodeGen pass at this point in the pipeline after checking overrides.
   /// Return the pass that was added, or zero if no pass was added.
-  /// @p printAfter    if true and adding a machine function pass add an extra
-  ///                  machine printer pass afterwards
   /// @p verifyAfter   if true and adding a machine function pass add an extra
   ///                  machine verification pass afterwards.
-  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
-                     bool printAfter = true);
+  AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true);
 
   /// Add a pass to the PassManager if that pass is supposed to be run, as
   /// determined by the StartAfter and StopAfter options. Takes ownership of the
   /// pass.
-  /// @p printAfter    if true and adding a machine function pass add an extra
-  ///                  machine printer pass afterwards
   /// @p verifyAfter   if true and adding a machine function pass add an extra
   ///                  machine verification pass afterwards.
-  void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
+  void addPass(Pass *P, bool verifyAfter = true);
 
   /// addMachinePasses helper to create the target-selected or overriden
   /// regalloc pass.
   virtual FunctionPass *createRegAllocPass(bool Optimized);
 
   /// Add core register alloator passes which do the actual register assignment
   /// and rewriting. \returns true if any passes were added.
   virtual bool addRegAssignmentFast();
   virtual bool addRegAssignmentOptimized();
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_TARGETPASSCONFIG_H

llvm/include/llvm/Target/TargetMachine.h

public:
   }
   void setSupportsDefaultOutlining(bool Enable) {
     Options.SupportsDefaultOutlining = Enable;
   }
   void setSupportsDebugEntryValues(bool Enable) {
     Options.SupportsDebugEntryValues = Enable;
   }
 
-  bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
-
   bool getUniqueSectionNames() const { return Options.UniqueSectionNames; }
 
   /// Return true if unique basic block section names must be generated.
   bool getUniqueBasicBlockSectionNames() const {
     return Options.UniqueBasicBlockSectionNames;
   }
 
   /// Return true if data objects should be emitted into their own section,

llvm/include/llvm/Target/TargetOptions.h

enum class GlobalISelAbortMode {
     Disable,        // Disable the abort.
     Enable,         // Enable the abort.
     DisableWithDiag // Disable the abort but emit a diagnostic on failure.
   };
 
   class TargetOptions {
   public:
     TargetOptions()
-        : PrintMachineCode(false), UnsafeFPMath(false), NoInfsFPMath(false),
-          NoNaNsFPMath(false), NoTrappingFPMath(true),
-          NoSignedZerosFPMath(false),
+        : UnsafeFPMath(false), NoInfsFPMath(false), NoNaNsFPMath(false),
+          NoTrappingFPMath(true), NoSignedZerosFPMath(false),
           HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
           GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
           EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
           DisableIntegratedAS(false), RelaxELFRelocations(false),
           FunctionSections(false), DataSections(false),
           UniqueSectionNames(true), UniqueBasicBlockSectionNames(false),
           TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
           EmulatedTLS(false), ExplicitEmulatedTLS(false), EnableIPRA(false),
           EmitStackSizeSection(false), EnableMachineOutliner(false),
           SupportsDefaultOutlining(false), EmitAddrsig(false),
           EmitCallSiteInfo(false), SupportsDebugEntryValues(false),
           EnableDebugEntryValues(false), ForceDwarfFrameSection(false),
           XRayOmitFunctionIndex(false),
           FPDenormalMode(DenormalMode::IEEE, DenormalMode::IEEE) {}
 
-    /// PrintMachineCode - This flag is enabled when the -print-machineinstrs
-    /// option is specified on the command line, and should enable debugging
-    /// output from the code generator.
-    unsigned PrintMachineCode : 1;
-
     /// DisableFramePointerElim - This returns true if frame pointer elimination
     /// optimization should be disabled for the given machine function.
     bool DisableFramePointerElim(const MachineFunction &MF) const;
 
     /// UnsafeFPMath - This flag is enabled when the
     /// -enable-unsafe-fp-math flag is specified on the command line.  When
     /// this flag is off (the default), the code generator is not allowed to
     /// produce results that are "less precise" than IEEE allows.  This includes

llvm/lib/CodeGen/MachineOperand.cpp

case PseudoSourceValue::ExternalSymbolCallEntry:
       OS << "call-entry &";
       printLLVMNameWithoutPrefix(
           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
       break;
     default: {
       const MIRFormatter *Formatter = TII->getMIRFormatter();
       // FIXME: This is not necessarily the correct MIR serialization format for
       // a custom pseudo source value, but at least it allows
-      // -print-machineinstrs to work on a target with custom pseudo source
+      // MIR printing to work on a target with custom pseudo source
       // values.
       OS << "custom \"";
       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
       OS << '\"';
       break;
     }
     }
   }

llvm/lib/CodeGen/TargetPassConfig.cpp

 static cl::opt<cl::boolOrDefault>
 EnableFastISelOption("fast-isel", cl::Hidden,
   cl::desc("Enable the \"fast\" instruction selector"));
 
 static cl::opt<cl::boolOrDefault> EnableGlobalISelOption(
     "global-isel", cl::Hidden,
     cl::desc("Enable the \"global\" instruction selector"));
 
-static cl::opt<std::string> PrintMachineInstrs(
-    "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
-    cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
+// FIXME: remove this after switching to NPM or GlobalISel, whichever gets there
+//        first...
+static cl::opt<bool>
+    PrintAfterISel("print-after-isel", cl::init(false), cl::Hidden,
+                   cl::desc("Print machine instrs after ISel"));
 
 static cl::opt<GlobalISelAbortMode> EnableGlobalISelAbort(
     "global-isel-abort", cl::Hidden,
     cl::desc("Enable abort calls when \"global\" instruction selection "
              "fails to lower/select an instruction"),
     cl::values(
         clEnumValN(GlobalISelAbortMode::Disable, "0", "Disable the abort"),
         clEnumValN(GlobalISelAbortMode::Enable, "1", "Enable the abort"),

 char TargetPassConfig::ID = 0;
 
 namespace {
 
 struct InsertedPass {
   AnalysisID TargetPassID;
   IdentifyingPassPtr InsertedPassID;
   bool VerifyAfter;
-  bool PrintAfter;
 
   InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID,
-               bool VerifyAfter, bool PrintAfter)
+               bool VerifyAfter)
       : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID),
-        VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {}
+        VerifyAfter(VerifyAfter) {}
 
   Pass *getInsertedPass() const {
     assert(InsertedPassID.isValid() && "Illegal Pass ID!");
     if (InsertedPassID.isInstance())
       return InsertedPassID.getInstance();
     Pass *NP = Pass::createPass(InsertedPassID.getID());
     assert(NP && "Pass ID not registered");
     return NP;
TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
   // Register all target independent codegen passes to activate their PassIDs,
   // including this pass itself.
   initializeCodeGen(*PassRegistry::getPassRegistry());
 
   // Also register alias analysis passes required by codegen passes.
   initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry());
   initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry());
 
-  if (StringRef(PrintMachineInstrs.getValue()).equals(""))
-    TM.Options.PrintMachineCode = true;
-
   if (EnableIPRA.getNumOccurrences())
     TM.Options.EnableIPRA = EnableIPRA;
   else {
     // If not explicitly specified, use target default.
     TM.Options.EnableIPRA |= TM.useIPRA();
   }
 
   if (TM.Options.EnableIPRA)
     setRequiresCodeGenSCCOrder();
 
   if (EnableGlobalISelAbort.getNumOccurrences())
     TM.Options.GlobalISelAbort = EnableGlobalISelAbort;
 
   setStartStopPasses();
 }
 
 CodeGenOpt::Level TargetPassConfig::getOptLevel() const {
   return TM->getOptLevel();
 }
 
 /// Insert InsertedPassID pass after TargetPassID.
 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
                                   IdentifyingPassPtr InsertedPassID,
-                                  bool VerifyAfter, bool PrintAfter) {
+                                  bool VerifyAfter) {
   assert(((!InsertedPassID.isInstance() &&
            TargetPassID != InsertedPassID.getID()) ||
           (InsertedPassID.isInstance() &&
            TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
          "Insert a pass after itself!");
-  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter,
-                                    PrintAfter);
+  Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter);
 }
 
 /// createPassConfig - Create a pass configuration object to be used by
 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
 ///
 /// Targets may override this to extend TargetPassConfig.
 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new TargetPassConfig(*this, PM);
return !FinalPtr.isValid() || FinalPtr.isInstance() ||
       FinalPtr.getID() != ID;
 }
 
 /// Add a pass to the PassManager if that pass is supposed to be run.  If the
 /// Started/Stopped flags indicate either that the compilation should start at
 /// a later pass or that it should stop after an earlier pass, then do not add
 /// the pass.  Finally, compare the current pass against the StartAfter
 /// and StopAfter options and change the Started/Stopped flags accordingly.
-void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
+void TargetPassConfig::addPass(Pass *P, bool verifyAfter) {
   assert(!Initialized && "PassConfig is immutable");
 
   // Cache the Pass ID here in case the pass manager finds this pass is
   // redundant with ones already scheduled / available, and deletes it.
   // Fundamentally, once we add the pass to the manager, we no longer own it
   // and shouldn't reference it.
   AnalysisID PassID = P->getPassID();
 
   if (StartBefore == PassID && StartBeforeCount++ == StartBeforeInstanceNum)
     Started = true;
   if (StopBefore == PassID && StopBeforeCount++ == StopBeforeInstanceNum)
     Stopped = true;
   if (Started && !Stopped) {
     if (AddingMachinePasses)
       addMachinePrePasses();
     std::string Banner;
     // Construct banner message before PM->add() as that may delete the pass.
-    if (AddingMachinePasses && (printAfter || verifyAfter))
+    if (AddingMachinePasses && verifyAfter)
       Banner = std::string("After ") + std::string(P->getPassName());
     PM->add(P);
     if (AddingMachinePasses)
-      addMachinePostPasses(Banner, /*AllowPrint*/ printAfter,
-                           /*AllowVerify*/ verifyAfter);
+      addMachinePostPasses(Banner, /*AllowVerify*/ verifyAfter);
 
     // Add the passes after the pass P if there is any.
     for (auto IP : Impl->InsertedPasses) {
       if (IP.TargetPassID == PassID)
-        addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter);
+        addPass(IP.getInsertedPass(), IP.VerifyAfter);
     }
   } else {
     delete P;
   }
 
   if (StopAfter == PassID && StopAfterCount++ == StopAfterInstanceNum)
     Stopped = true;
 
   if (StartAfter == PassID && StartAfterCount++ == StartAfterInstanceNum)
     Started = true;
   if (Stopped && !Started)
     report_fatal_error("Cannot stop compilation after pass that is not run");
 }
 
 /// Add a CodeGen pass at this point in the pipeline after checking for target
 /// and command line overrides.
 ///
 /// addPass cannot return a pointer to the pass instance because is internal the
 /// PassManager and the instance we create here may already be freed.
-AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
-                                     bool printAfter) {
+AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter) {
   IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
   IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
   if (!FinalPtr.isValid())
     return nullptr;
 
   Pass *P;
   if (FinalPtr.isInstance())
     P = FinalPtr.getInstance();
   else {
     P = Pass::createPass(FinalPtr.getID());
     if (!P)
       llvm_unreachable("Pass ID not registered");
   }
   AnalysisID FinalID = P->getPassID();
-  addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
+  addPass(P, verifyAfter); // Ends the lifetime of P.
 
   return FinalID;
 }
 
 void TargetPassConfig::printAndVerify(const std::string &Banner) {
   addPrintPass(Banner);
   addVerifyPass(Banner);
 }
 
 void TargetPassConfig::addPrintPass(const std::string &Banner) {
-  if (TM->shouldPrintMachineCode())
+  if (PrintAfterISel)
     PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
 }
 
 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
   bool Verify = VerifyMachineCode == cl::BOU_TRUE;
 #ifdef EXPENSIVE_CHECKS
   if (VerifyMachineCode == cl::BOU_UNSET)
     Verify = TM->isMachineVerifierClean();

 }
 
 void TargetPassConfig::addMachinePrePasses(bool AllowDebugify) {
   if (AllowDebugify && DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
     addDebugifyPass();
 }
 
 void TargetPassConfig::addMachinePostPasses(const std::string &Banner,
-                                            bool AllowPrint, bool AllowVerify,
-                                            bool AllowStrip) {
+                                            bool AllowVerify, bool AllowStrip) {
   if (DebugifyAndStripAll == cl::BOU_TRUE && DebugifyIsSafe)
     addStripDebugPass();
-  if (AllowPrint)
-    addPrintPass(Banner);
   if (AllowVerify)
     addVerifyPass(Banner);
 }
 
 /// Add common target configurable passes that perform LLVM IR to IR transforms
 /// following machine independent optimization.
 void TargetPassConfig::addIRPasses() {
   // Before running any passes, run the verifier to determine if the input

 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
 /// the target should override the stage instead.
 ///
 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
 /// before/after any target-independent pass. But it's currently overkill.
 void TargetPassConfig::addMachinePasses() {
   AddingMachinePasses = true;
 
-  // Insert a machine instr printer pass after the specified pass.
-  StringRef PrintMachineInstrsPassName = PrintMachineInstrs.getValue();
-  if (!PrintMachineInstrsPassName.equals("") &&
-      !PrintMachineInstrsPassName.equals("option-unspecified")) {
-    if (const PassInfo *TPI = getPassInfo(PrintMachineInstrsPassName)) {
-      const PassRegistry *PR = PassRegistry::getPassRegistry();
-      const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
-      assert(IPI && "failed to get \"machineinstr-printer\" PassInfo!");
-      const char *TID = (const char *)(TPI->getTypeInfo());
-      const char *IID = (const char *)(IPI->getTypeInfo());
-      insertPass(TID, IID);
-    }
-  }
-
   // Add passes that optimize machine instructions in SSA form.
   if (getOptLevel() != CodeGenOpt::None) {
     addMachineSSAOptimization();
   } else {
     // If the target requests it, assign local variables to stack slots relative
     // to one another and simplify frame index references where possible.
     addPass(&LocalStackSlotAllocationID);
   }
if (MISchedPostRA)
       addPass(&PostMachineSchedulerID);
     else
       addPass(&PostRASchedulerID);
   }
 
   // GC
   if (addGCPasses()) {
     if (PrintGCInfo)
-      addPass(createGCInfoPrinter(dbgs()), false, false);
+      addPass(createGCInfoPrinter(dbgs()), false);
   }
 
   // Basic block placement.
   if (getOptLevel() != CodeGenOpt::None)
     addBlockPlacement();
 
   // Insert before XRay Instrumentation.
   addPass(&FEntryInserterID);

llvm/lib/Target/Mips/MipsTargetMachine.cpp

if (Subtarget->allowMixed16_32()) {
     return TargetTransformInfo(F.getParent()->getDataLayout());
   }
 
   LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
   return TargetTransformInfo(BasicTTIImpl(this, F));
 }
 
 // Implemented by targets that want to run passes immediately before
-// machine code is emitted. return true if -print-machineinstrs should
-// print out the code after the passes.
+// machine code is emitted.
 void MipsPassConfig::addPreEmitPass() {
   // Expand pseudo instructions that are sensitive to register allocation.
   addPass(createMipsExpandPseudoPass());
 
   // The microMIPS size reduction pass performs instruction reselection for
   // instructions which can be remapped to a 16 bit instruction.
   addPass(createMicroMipsSizeReducePass());
 

llvm/test/CodeGen/AArch64/chkstk.ll

 ; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs %s -o - \
 ; RUN:  | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s
-; RUN: llc -mtriple=aarch64-windows -print-machineinstrs=prologepilog %s -o - 2>&1 \
+; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog \
 ; RUN:  | FileCheck -check-prefix CHECK-REGSTATE %s
 
 ; RUN: llc -mtriple=aarch64-windows -verify-machineinstrs -code-model=large %s -o - \
 ; RUN:  | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s
-; RUN: llc -mtriple=aarch64-windows -print-machineinstrs=prologepilog -code-model=large %s -o - 2>&1 \
+; RUN: llc < %s -mtriple=aarch64-windows -stop-after=prologepilog -code-model=large \
 ; RUN:  | FileCheck -check-prefix CHECK-REGSTATE-LARGE %s
 
 define void @check_watermark() {
 entry:
   %buffer = alloca [4096 x i8], align 1
   ret void
 }
 

llvm/test/CodeGen/AArch64/max-jump-table.ll

-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40                         -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0  < %t
-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4  -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4  < %t
-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8  -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8  < %t
-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t
-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3         -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40                         -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0  < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=4  -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4  < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=8  -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8  < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -max-jump-table-size=16 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK16 < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -mcpu=exynos-m3         -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECKM3 < %t
 
 declare void @ext(i32, i32)
 
 define i32 @jt1(i32 %a, i32 %b) {
 entry:
   switch i32 %a, label %return [
     i32 1,  label %bb1
     i32 2,  label %bb2

llvm/test/CodeGen/AArch64/min-jump-table.ll

-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0  < %t
-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2  < %t
-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4  < %t
-; RUN: llc %s -O2 -print-machineinstrs -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8  < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=0 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK0  < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=2 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK2  < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=4 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK4  < %t
+; RUN: llc %s -O2 -print-after-isel -mtriple=aarch64-linux-gnu -jump-table-density=40 -min-jump-table-entries=8 -o /dev/null 2> %t; FileCheck %s --check-prefixes=CHECK,CHECK8  < %t
 
 declare void @ext(i32, i32)
 
 define i32 @jt2(i32 %a, i32 %b) {
 entry:
   switch i32 %a, label %return [
     i32 1, label %bb1
     i32 3, label %bb2

llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll

-; RUN: llc < %s -mtriple=armv4t--linux-androideabi -print-machineinstrs=if-converter -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=armv4t--linux-androideabi -stop-after=if-converter | FileCheck %s
 ; Fix a bug triggered in IfConverterTriangle when CvtBB has multiple
 ; predecessors.
 ; PR18752
 
 %classK = type { i8, %classF }
 %classF = type { i8 }
 %classL = type { %classG, i32, i32 }
 %classG = type { %classL* }

llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll

-; RUN: llc < %s -mtriple=thumbv8 -print-machineinstrs=if-converter -arm-atomic-cfg-tidy=0 -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv8 -stop-after=if-converter -arm-atomic-cfg-tidy=0 | FileCheck %s
 
 %struct.S = type { i8* (i8*)*, [1 x i8] }
 define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
 entry:
   %0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0
   %1 = load i8, i8* %0, align 1
   %2 = zext i8 %1 to i32
   %3 = and i32 %2, 112

llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll

 ; RUN: llc < %s -mtriple thumbv7s-apple-darwin  -asm-verbose=false | FileCheck %s
-; RUN: llc < %s -mtriple thumbv7s-apple-darwin  -asm-verbose=false -print-machineinstrs=if-converter 2>&1 | FileCheck --check-prefix=CHECK-PROB %s
+; RUN: llc < %s -mtriple thumbv7s-apple-darwin  -asm-verbose=false -stop-after=if-converter | FileCheck --check-prefix=CHECK-PROB %s
 
 declare i32 @foo(i32)
 declare i8* @bar(i32, i8*, i8*)
 
 ; Verify that we don't try to iteratively re-ifconvert a block with a
 ; (predicated) indirectbr terminator.
 ; If we do, we would ignore its fallthrough successor.
 

llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll

-; RUN: llc -mtriple=arm-apple-ios -print-machineinstrs=branch-folder \
-; RUN: %s -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-ios -stop-after=branch-folder | FileCheck %s
 
 ; Branch probability of tailed-merged block:
 ;
 ; p(L0_L1 -> L2) = p(entry -> L0) * p(L0 -> L2) + p(entry -> L1) * p(L1 -> L2)
 ;                = 0.2 * 0.6 + 0.8 * 0.3 = 0.36
 ; p(L0_L1 -> L3) = p(entry -> L0) * p(L0 -> L3) + p(entry -> L1) * p(L1 -> L3)
 ;                = 0.2 * 0.4 + 0.8 * 0.7 = 0.64
 
-; CHECK: # Machine code for function test0:
 ; CHECK: successors: %bb.{{[0-9]+}}(0x1999999a), %bb.{{[0-9]+}}(0x66666666)
 ; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
 ; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
-; CHECK: # End machine code for function test0.
 
 define i32 @test0(i32 %n, i32 %m, i32* nocapture %a, i32* nocapture %b) {
 entry:
   %cmp = icmp sgt i32 %n, 0
   br i1 %cmp, label %L0, label %L1, !prof !0
 
 L0:                                          ; preds = %entry
   store i32 12, i32* %a, align 4

llvm/test/CodeGen/ARM/taildup-branch-weight.ll

-; RUN: llc -mtriple=arm-eabi -print-machineinstrs=tailduplication -tail-dup-size=100 \
-; RUN:      -enable-tail-merge=false -disable-cgp %s -o /dev/null 2>&1 \
-; RUN:  | FileCheck %s
+; RUN: llc < %s -mtriple=arm-eabi -stop-after=tailduplication -tail-dup-size=100 \
+; RUN:      -enable-tail-merge=false -disable-cgp | FileCheck %s
 
-; CHECK: Machine code for function test0:
+; CHECK: name:            test0
 ; CHECK: successors: %bb.1(0x04000000), %bb.2(0x7c000000)
 
 define void @test0(i32 %a, i32 %b, i32* %c, i32* %d) {
 entry:
   store i32 3, i32* %d
   br label %B1
 
 B2:
B1:
   br i1 %test0, label %B2, label %B3, !prof !0
 
 B4:
   ret void
 }
 
 !0 = !{!"branch_weights", i32 4, i32 124}
 
-; CHECK: Machine code for function test1:
+; CHECK: name:            test1
 ; CHECK: successors: %bb.2(0x7c000000), %bb.1(0x04000000)
 
 @g0 = common global i32 0, align 4
 
 define void @test1(i32 %a, i32 %b, i32* %c, i32* %d, i32* %e) {
 
   %test0 = icmp slt i32 %a, %b
   br i1 %test0, label %B1, label %B2, !prof !1

llvm/test/CodeGen/Generic/print-machineinstrs.ll

-; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs=branch-folder -verify-machineinstrs -o /dev/null 2>&1 \
-; RUN:   | FileCheck %s -check-prefix=PRINT-BRANCH-FOLD
-; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs -verify-machineinstrs -o /dev/null 2>&1 \
-; RUN:   | FileCheck %s -check-prefix=PRINT
-; RUN: llc < %s -O3 -debug-pass=Structure -print-machineinstrs= -verify-machineinstrs -o /dev/null 2>&1 \
-; RUN:   | FileCheck %s -check-prefix=PRINT
-
-; Note: -verify-machineinstrs is used in order to make this test compatible with EXPENSIVE_CHECKS.
-
-define i64 @foo(i64 %a, i64 %b) nounwind {
-; PRINT-BRANCH-FOLD: -branch-folder -machineverifier -machineinstr-printer
-; PRINT-BRANCH-FOLD: Control Flow Optimizer
-; PRINT-BRANCH-FOLD-NEXT: Verify generated machine code
-; PRINT-BRANCH-FOLD-NEXT: MachineFunction Printer
-; PRINT-BRANCH-FOLD: Machine code for function foo:
-
-; PRINT: -branch-folder -machineinstr-printer
-; PRINT: Control Flow Optimizer
-; PRINT-NEXT: MachineFunction Printer
-; PRINT-NEXT: Verify generated machine code
-; PRINT: Machine code for function foo:
-
-  %c = add i64 %a, %b
-  %d = trunc i64 %c to i32
-  %e = zext i32 %d to i64
-  ret i64 %e
-}

llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll

-; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -print-machineinstrs=if-converter %s -o /dev/null 2>&1 | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -stop-after=if-converter < %s | FileCheck %s
 ; Check that the edge weights are updated correctly after if-conversion.
 
 ; CHECK: bb.3.if{{[0-9a-zA-Z.]*}}:
 ; CHECK: successors: %bb.2(0x0ccccccd), %bb.1(0x73333333)
 @a = external global i32
 @d = external global i32
 
 ; In the following CFG, A,B,C,D will be if-converted into a single block.

llvm/test/CodeGen/X86/llc-print-machineinstrs.mir

-# Check that -print-machineinstrs doesn't assert when it's passed an unknown pass name.
-# RUN: llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=greedy %s -o /dev/null
-# RUN: not --crash llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=unknown %s -o /dev/null 2>&1 | FileCheck %s
-# CHECK: LLVM ERROR: "unknown" pass is not registered.
-
-...
----
-name: fun
-tracksRegLiveness: true
-body: |
-  bb.0:
-    RET 0

llvm/test/DebugInfo/WebAssembly/dbg-value-live-interval.ll

-; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
+; FIXME: use -stop-after when MIR serialization output includes needed debug info.
+; RUN: llc < %s -print-after=wasm-optimize-live-intervals 2>&1 | FileCheck %s
 
-; CHECK: After WebAssembly Optimize Live Intervals:
+; CHECK: {{.*}}After WebAssembly Optimize Live Intervals
 ; CHECK: bb.3.for.body.for.body_crit_edge:
 ; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
 ; CHECK: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
-; CHECK: After WebAssembly Memory Intrinsic Results:
 
 ; ModuleID = 'fib.bc'
 source_filename = "fib.c"
 ; void swap(int* a, int* b);
 ;
 ; __attribute__ ((visibility ("default")))
 ; int fib(int n) {
 ;   int i, t, a = 0, b = 1;

llvm/test/DebugInfo/WebAssembly/dbg-value-move-2.ll

-; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
+; FIXME: use -stop-after when MIR serialization output includes needed debug info.
+; RUN: llc < %s -print-after=wasm-reg-stackify 2>&1 | FileCheck %s
 
-; CHECK: After WebAssembly Register Stackify:
+; CHECK: {{.*}}After WebAssembly Register Stackify
 ; CHECK: bb.2.for.body:
 ; CHECK: [[REG:%[0-9]+]]:i32 = TEE_I32 {{.*}} fib2.c:6:7
 ; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib2.c:2:13
-; CHECK: After WebAssembly Register Coloring:
 
 ; ModuleID = 'fib2.bc'
 ; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib2.c -g -O2
 ; All non-"!dbg !18" llvm.dbg.value calls and attributes were removed.
 source_filename = "fib2.c"
 ; int fib(int n) {
 ;   int i, t, a = 0, b = 1;
 ;   for (i = 0; i < n; i++) {

llvm/test/DebugInfo/WebAssembly/dbg-value-move.ll

-; RUN: llc < %s -print-machineinstrs 2>&1 | FileCheck %s
+; FIXME: use -stop-after when MIR serialization output includes needed debug info.
+; RUN: llc < %s -print-after=wasm-reg-stackify 2>&1 | FileCheck %s
 
-; CHECK: After WebAssembly Register Stackify:
+; CHECK: {{.*}}After WebAssembly Register Stackify
 ; CHECK: bb.3.for.body.for.body_crit_edge:
 ; CHECK: [[REG:%[0-9]+]]:i32 = nsw ADD_I32 {{.*}} fib.c:7:7
 ; CHECK-NEXT: DBG_VALUE [[REG]]:i32, $noreg, !"a", {{.*}} fib.c:5:13
-; CHECK: After WebAssembly Register Coloring:
 
 ; ModuleID = 'fib.bc'
 ; The test generated via: clang --target=wasm32-unknown-unknown-wasm fib.c -g -O2
 ; All lifetime markers and attributes were removed.
 source_filename = "fib.c"
 ; void swap(int* a, int* b);
 ;
 ; __attribute__ ((visibility ("default")))