[ARM] More unpredictable VCVT instructions.

[dmgreen]

Summary

These extra vcvt instructions were missed from D81639 because they live in a different Domain, but should be treated in the same way.

[dmgreen]

Update test.

[dmgreen]

Ping :)

[efriedma]

llvm/lib/Target/ARM/ARMInstrVFP.td

1605

Move this to AVConv1InsS_Encode?

llvm/unittests/Target/ARM/MachineInstrTest.cpp

1106–1107

Unnecessary parentheses around first "&".

[dmgreen]

Move to AVConv1InsS_Encode.

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMInstrVFP.td

class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
   bits<5> Sd;
   bits<5> Sm;
 
   // Encode instruction operands.
   let Inst{3-0}   = Sm{4-1};
   let Inst{5}     = Sm{0};
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
+
+  let hasSideEffects = 0;
 }
 
 class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
                          bits<4> opcod4, dag oops, dag iops,
                          InstrItinClass itin, string opc, string asm,
                          list<dag> pattern>
   : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
               pattern> {
def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
                                  IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
                                  []>,
               Sched<[WriteFPCVT]> {
   let Inst{7} = 1; // Z bit
 
   // Some single precision VFP instructions may be executed on both NEON and
   // VFP pipelines on A8.
   let D = VFPNeonA8Domain;
 }
 
 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
                    (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
 
 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
                                    addrmode5:$ptr),
                    (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
 

llvm/test/CodeGen/Thumb2/mve-vcvt.ll

entry:
   ret <4 x float> %out
 }
 
 define arm_aapcs_vfpcc <4 x i32> @foo_int32_float(<4 x float> %src) {
 ; CHECK-MVE-LABEL: foo_int32_float:
 ; CHECK-MVE:       @ %bb.0: @ %entry
 ; CHECK-MVE-NEXT:    vcvt.s32.f32 s4, s0
 ; CHECK-MVE-NEXT:    vcvt.s32.f32 s6, s1
-; CHECK-MVE-NEXT:    vcvt.s32.f32 s8, s3
 ; CHECK-MVE-NEXT:    vcvt.s32.f32 s10, s2
+; CHECK-MVE-NEXT:    vcvt.s32.f32 s8, s3
 ; CHECK-MVE-NEXT:    vmov r0, s4
 ; CHECK-MVE-NEXT:    vmov.32 q0[0], r0
 ; CHECK-MVE-NEXT:    vmov r0, s6
 ; CHECK-MVE-NEXT:    vmov.32 q0[1], r0
 ; CHECK-MVE-NEXT:    vmov r0, s10
 ; CHECK-MVE-NEXT:    vmov.32 q0[2], r0
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.32 q0[3], r0
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: foo_int32_float:
 ; CHECK-MVEFP:       @ %bb.0: @ %entry
 ; CHECK-MVEFP-NEXT:    vcvt.s32.f32 q0, q0
 ; CHECK-MVEFP-NEXT:    bx lr
 entry:
   %out = fptosi <4 x float> %src to <4 x i32>
   ret <4 x i32> %out
 }
 
 define arm_aapcs_vfpcc <4 x i32> @foo_uint32_float(<4 x float> %src) {
 ; CHECK-MVE-LABEL: foo_uint32_float:
 ; CHECK-MVE:       @ %bb.0: @ %entry
 ; CHECK-MVE-NEXT:    vcvt.u32.f32 s4, s0
 ; CHECK-MVE-NEXT:    vcvt.u32.f32 s6, s1
-; CHECK-MVE-NEXT:    vcvt.u32.f32 s8, s3
 ; CHECK-MVE-NEXT:    vcvt.u32.f32 s10, s2
+; CHECK-MVE-NEXT:    vcvt.u32.f32 s8, s3
 ; CHECK-MVE-NEXT:    vmov r0, s4
 ; CHECK-MVE-NEXT:    vmov.32 q0[0], r0
 ; CHECK-MVE-NEXT:    vmov r0, s6
 ; CHECK-MVE-NEXT:    vmov.32 q0[1], r0
 ; CHECK-MVE-NEXT:    vmov r0, s10
 ; CHECK-MVE-NEXT:    vmov.32 q0[2], r0
 ; CHECK-MVE-NEXT:    vmov r0, s8
 ; CHECK-MVE-NEXT:    vmov.32 q0[3], r0

llvm/unittests/Target/ARM/MachineInstrTest.cpp

TEST(MachineInstr, HasSideEffects) {
   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
                   std::string(TM->getTargetFeatureString()),
                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
   auto MII = TM->getMCInstrInfo();
 
   for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) {
     const MCInstrDesc &Desc = TII->get(Op);
-    if ((Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainMVE &&
-        (Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainVFP)
+    if ((Desc.TSFlags &
+         (ARMII::DomainMVE | ARMII::DomainVFP | ARMII::DomainNEONA8)) == 0)
       continue;
     if (UnpredictableOpcodes.count(Op))
       continue;
 
     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
         << MII->getName(Op) << " has unexpected side effects";
   }
 }