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Differential D83204

[ARM] More unpredictable VCVT instructions.
ClosedPublic

Authored by dmgreen on Jul 6 2020, 2:46 AM.

Details

Reviewers
samparker
efriedma
SjoerdMeijer
simon_tatham
ostannard
Commits
rG30371df85f3e: [ARM] More unpredictable VCVT instructions.
Summary

These extra vcvt instructions were missed from D81639 because they live in a different Domain, but should be treated in the same way.

Diff Detail

Event Timeline

dmgreen created this revision.Jul 6 2020, 2:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2020, 2:46 AM
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen updated this revision to Diff 275626.Jul 6 2020, 2:49 AM
dmgreen retitled this revision from [ARM to [ARM] More unpredicatable VCVT instructions..
dmgreen edited the summary of this revision. (Show Details)
dmgreen added reviewers: samparker, efriedma, SjoerdMeijer, simon_tatham, ostannard.

Update test.

dmgreen retitled this revision from [ARM] More unpredicatable VCVT instructions. to [ARM] More unpredictable VCVT instructions..Jul 6 2020, 3:02 AM
dmgreen added a comment.Jul 16 2020, 10:51 AM

Ping :)

efriedma added inline comments.Jul 16 2020, 1:32 PM
llvm/lib/Target/ARM/ARMInstrVFP.td
1603

Move this to AVConv1InsS_Encode?

llvm/unittests/Target/ARM/MachineInstrTest.cpp
1106–1107

Unnecessary parentheses around first "&".

dmgreen updated this revision to Diff 278662.Jul 16 2020, 10:41 PM

Move to AVConv1InsS_Encode.

efriedma accepted this revision.Jul 20 2020, 2:16 PM

LGTM

This revision is now accepted and ready to land.Jul 20 2020, 2:16 PM
Closed by commit rG30371df85f3e: [ARM] More unpredictable VCVT instructions. (authored by dmgreen). · Explain WhyJul 20 2020, 11:32 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
2 lines
unittests/
Target/
ARM/
4 lines

Diff 275624

llvm/lib/Target/ARM/ARMInstrVFP.td

Show First 20 Lines • Show All 1,594 Lines • ▼ Show 20 Linesdef VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm", IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
[]>, []>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
let Inst{7} = 1; // Z bit let Inst{7} = 1; // Z bit
// Some single precision VFP instructions may be executed on both NEON and // Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8. // VFP pipelines on A8.
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
let hasSideEffects = 0;
efriedmaUnsubmitted
Not Done
ReplyInline Actions

Move this to AVConv1InsS_Encode?

efriedma: Move this to AVConv1InsS_Encode?
} }
def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)), def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
(COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))), def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
addrmode5:$ptr), addrmode5:$ptr),
(VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>; (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
Show All 31 Linesdef VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm", IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
[]>, []>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
let Inst{7} = 1; // Z bit let Inst{7} = 1; // Z bit
// Some single precision VFP instructions may be executed on both NEON and // Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8. // VFP pipelines on A8.
let D = VFPNeonA8Domain; let D = VFPNeonA8Domain;
let hasSideEffects = 0;
} }
def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)), def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
(COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>; (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))), def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
addrmode5:$ptr), addrmode5:$ptr),
(VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>; (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
▲ Show 20 Lines • Show All 1,213 Lines • Show Last 20 Lines

llvm/unittests/Target/ARM/MachineInstrTest.cpp

Show First 20 Lines • Show All 1,097 Lines • ▼ Show 20 LinesTEST(MachineInstr, HasSideEffects) {
ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
std::string(TM->getTargetFeatureString()), std::string(TM->getTargetFeatureString()),
*static_cast<const ARMBaseTargetMachine *>(TM.get()), false); *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
const ARMBaseInstrInfo *TII = ST.getInstrInfo(); const ARMBaseInstrInfo *TII = ST.getInstrInfo();
auto MII = TM->getMCInstrInfo(); auto MII = TM->getMCInstrInfo();
for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) { for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) {
const MCInstrDesc &Desc = TII->get(Op); const MCInstrDesc &Desc = TII->get(Op);
if ((Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainMVE && if (((Desc.TSFlags & ARMII::DomainMask) &
(Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainVFP) (ARMII::DomainMVE | ARMII::DomainVFP | ARMII::DomainNEONA8)) == 0)
efriedmaUnsubmitted
Not Done
ReplyInline Actions

Unnecessary parentheses around first "&".

efriedma: Unnecessary parentheses around first "&".
continue; continue;
if (UnpredictableOpcodes.count(Op)) if (UnpredictableOpcodes.count(Op))
continue; continue;
ASSERT_FALSE(Desc.hasUnmodeledSideEffects()) ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
<< MII->getName(Op) << " has unexpected side effects"; << MII->getName(Op) << " has unexpected side effects";
} }
} }