[Power10] Implement Vector Splat Immediate Builtins in LLVM/Clang

[biplmish]

Summary

This patch implements builtins for the following prototypes:

vector signed int vec_splati (const signed int);
vector float vec_splati (const float);

vector double vec_splatid (const float);

vector signed int vec_splati_ins (vector signed int, const unsigned int, const signed int);
vector unsigned int vec_splati_ins (vector unsigned int, const unsigned int, const unsigned int);
vector float vec_splati_ins (vector float, const unsigned int, const float);

[amyk]

clang/include/clang/Basic/BuiltinsPPC.def

449

Nit: space after //

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1477

This PPCISD node is not used anywhere?

llvm/lib/Target/PowerPC/PPCISelLowering.h

100

Maybe we can say PPC VSX Splat Immediate instructions for converting . . .

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

588

There's a section for anonymous patterns at the bottom of the file. It may be better to have a separate PrefixInstrs anonymous patterns section there.

[biplmish]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1477

This is used in XXSPLTIDP. The input to builtin is a single precision float which needs to be converted to a double precision for the input xxspltidp

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

588

Can implement on these lines.

[steven.zhang]

What I see from this patch is:

• builtins -> expressions
• intrinsics -> hw instructions.

I didn't see any test or something that we can prove that, the expression can be lowered to hw instructions.

clang/test/CodeGen/builtins-ppc-p10vector.c

86

The test is too weak. Please check <4 x i32><i32 -1, i32 -1, i32 -1, i32 -1>

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

573

Not prefix instruction.

581

Can you explain more on why we need this pattern ? I didn't see any test for this .

[biplmish]

On intrinsics -> hw instructions, will have a discussion and if needs to be implemented in these lines.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

573

These are prefixed 64 bit instructions.

581

This is used in XXSPLTIDP. The input to builtin is a single precision float which needs to be converted to a double precision for the input xxspltidp

[biplmish]

Repatching after the p10 vector splat immediate instructions have been merged upstream.

[steven.zhang]

LGTM now as https://reviews.llvm.org/D82911 landed to exploit the splat hw instruction. Please hold on to see if @lei or @amyk have more comments.

[nemanjai]

If this patch does not include the back end codegen test cases for these, which patch does? I don't see any selection patterns or test cases for xxsplti32dx in ToT.
The implementation and test cases for xxspltiw are in ToT, so they don't appear to be a concern.

clang/lib/Headers/altivec.h

16852

Again, I think it is preferable from a readability standpoint to keep the LE and BE blocks close together:

static __inline__ vector signed int __ATTRS_o_ai vec_splati_ins(
    vector signed int __a, const unsigned int __b, const signed int __c) {
  assert(__b < 2 && "The second argument must be 0 or 1");
#ifdef __LITTLE_ENDIAN__
  __a[1 - __b] = __c;
  __a[3 - __b] = __c;
#else
  __a[__b] = __c;
  __a[2 + __b] = __c;
#endif
  return __a;
}

And similarly for the other two. Of course, in this case you can't really forward calls because there isn't really a way to represent a bitcast of a float constant to int in the language.

clang/test/CodeGen/builtins-ppc-p10vector.c

109

You have separate checks for LE/BE. Please show the index in the checks and don't use the same index for all 3 test cases.

[nemanjai]

Also, please add a couple of new test in test/CodeGen/PowerPC/p10-splatImm.ll so that when someone looks at this commit in the log, they can see that vec_splati and vec_splatid are meant to produce xxspltiw and xxspltidp (i.e. the same IR produced for the calls in this test, produces the desired instruction)..

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

12

I don't see why this is needed as it's the exact same test as line 2 but with a diff check-prefix.

111

Why bother with different checks for BE and LE? Seems they produce the same outputs.

[amyk]

clang/test/CodeGen/builtins-ppc-p10vector.c

113

Would also be good to add tests where the second argument is 1.

[biplmish]

Code changes to bring the LE and BE block close, add additional tests.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

104

missing CHECK-BE?

[biplmish]

clang/test/CodeGen/builtins-ppc-p10vector.c

104

There will 1 less case for BE as one splat location will be the same as index.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

86

missing CHECK-BE

90

same

96

same

104

not sure what you mean. There is not checks for BE here at all....

[amyk]

clang/lib/Headers/altivec.h

16845

Move function name on next line for consistency.

16851

Also move function name to next line.

16864

Also move function name to next line.

[biplmish]

clang/lib/Headers/altivec.h

16845

These changes break the clang-format.

clang/test/CodeGen/builtins-ppc-p10vector.c

86

vec_splati and vec_splati do not have an endianess specific implementation.

[biplmish]

Update tests to add checks for BE.

[lei]

LGTM

[amyk]

Unless Lei and Nemanja have any additional comments, LGTM.

[nemanjai]

Other than removing the assert, this LGTM.

clang/lib/Headers/altivec.h

16852

Sorry that I didn't really pay close enough attention here previously, but please no asserts in the header.

1. The user of the header may not include <assert.h>
2. The compiler should not be injecting asserts into user code.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "")
 BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "")
 BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "")
 BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "")
 BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "")
 
+//P10 Vector Splat built-ins.
+BUILTIN(__builtin_vsx_xxspltiw, "V4UiIi", "")
+BUILTIN(__builtin_vsx_xxspltidp, "V2dIi", "")
+BUILTIN(__builtin_vsx_xxsplti32dx, "V4UiV4UiIiIi", "")
+
 // HTM builtins
 BUILTIN(__builtin_tbegin, "UiUIi", "")
 BUILTIN(__builtin_tend, "UiUIi", "")
 
 BUILTIN(__builtin_tabort, "UiUi", "")
 BUILTIN(__builtin_tabortdc, "UiUiUiUi", "")
 BUILTIN(__builtin_tabortdci, "UiUiUii", "")
 BUILTIN(__builtin_tabortwc, "UiUiUiUi", "")

clang/lib/Headers/altivec.h

 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_clrr(vector unsigned char __a, unsigned int __n) {
 #ifdef __LITTLE_ENDIAN__
   return __builtin_altivec_vclrlb((vector signed char)__a, __n);
 #else
   return __builtin_altivec_vclrrb((vector signed char)__a, __n);
 #endif
 }
+
+#ifdef __VSX__
+
+/* vec_splati */
+
+#define vec_splati(__a)                                                        \
+  _Generic((__a), signed int                                                   \
+           : ((vector signed int)__a), unsigned int                            \
+           : ((vector unsigned int)__a), float                                 \
+           : ((vector float)__a))
+
+
+/* vec_spatid */
+
+static __inline__ vector double __ATTRS_o_ai vec_splatid(const float __a) {
+  return ((vector double)((double)__a));
+}
+
+/* vec_splati_ins */
+
+#ifdef __LITTLE_ENDIAN__
+static __inline__ vector signed int __ATTRS_o_ai vec_splati_ins(
+    vector signed int __a, const unsigned int __b, const signed int __c) {
+  assert((__b == 0 || __b == 1) && "The second argument must be 0 or 1");
+  __a[1 - __b] = __c;
+  __a[2 + 1 - __b] = __c;
+  return __a;
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_splati_ins(
+    vector unsigned int __a, const unsigned int __b, const unsigned int __c) {
+  assert((__b == 0 || __b == 1) && "The second argument must be 0 or 1");
+  __a[1 - __b] = __c;
+  __a[2 + 1 - __b] = __c;
+  return __a;
+}
+
+static __inline__ vector float __ATTRS_o_ai
+vec_splati_ins(vector float __a, const unsigned int __b, const float __c) {
+  assert((__b == 0 || __b == 1) && "The second argument must be 0 or 1");
+  __a[1 - __b] = __c;
+  __a[2 + 1 - __b] = __c;
+  return __a;
+}
+#else
+static __inline__ vector signed int __ATTRS_o_ai vec_splati_ins(
+    vector signed int __a, const unsigned int __b, const signed int __c) {
+  assert((__b == 0 || __b == 1) && "The second argument must be 0 or 1");
+  __a[__b] = __c;
+  __a[2 + __b] = __c;
+  return __a;
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_splati_ins(
+    vector unsigned int __a, const unsigned int __b, const unsigned int __c) {
+  assert((__b == 0 || __b == 1) && "The second argument must be 0 or 1");
+  __a[__b] = __c;
+  __a[2 + __b] = __c;
+  return __a;
+}
+
+static __inline__ vector float __ATTRS_o_ai
+vec_splati_ins(vector float __a, const unsigned int __b, const float __c) {
+  assert((__b == 0 || __b == 1) && "The second argument must be 0 or 1");
+  __a[__b] = __c;
+  __a[2 + __b] = __c;
+  return __a;
+}
+#endif
+#endif /* __VSX__ */
 #endif /* __POWER10_VECTOR__ */
 
 #undef __ATTRS_o_ai
 
 #endif /* __ALTIVEC_H */

clang/lib/Sema/SemaChecking.cpp

bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
   case PPC::BI__builtin_vsx_xxpermdi:
   case PPC::BI__builtin_vsx_xxsldwi:
     return SemaBuiltinVSX(TheCall);
   case PPC::BI__builtin_unpack_vector_int128:
     return SemaVSXCheck(TheCall) ||
            SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
   case PPC::BI__builtin_pack_vector_int128:
     return SemaVSXCheck(TheCall);
+  case PPC::BI__builtin_vsx_xxsplti32dx:
+     return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
   }
   return SemaBuiltinConstantArgRange(TheCall, i, l, u);
 }
 
 bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
                                           CallExpr *TheCall) {
   // position of memory order and scope arguments in the builtin
   unsigned OrderIndex, ScopeIndex;

clang/test/CodeGen/builtins-ppc-p10vector.c

 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -target-feature +vsx -target-feature +altivec \
 // RUN:   -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \
 // RUN:   -o - | FileCheck %s
 
 #include <altivec.h>
 
 vector signed char vsca;
 vector unsigned char vuca;
 vector unsigned short vusa;
 vector unsigned int vuia;
 vector unsigned long long vulla, vullb;
+vector signed int vsia;
+vector float vfa;
 unsigned int uia;
 
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pdep(vulla, vullb);
 }
 

 
 vector unsigned char test_vec_clrr_uc(void) {
   // CHECK-BE: @llvm.ppc.altivec.vclrrb(<16 x i8>
   // CHECK-BE-NEXT: ret <16 x i8>
   // CHECK-LE: @llvm.ppc.altivec.vclrlb(<16 x i8>
   // CHECK-LE-NEXT: ret <16 x i8>
   return vec_clrr(vuca, uia);
 }
+
+vector signed int test_vec_vec_splati_si(void) {
+  // CHECK: ret <4 x i32>
+  return vec_splati(-1);
+}
+
+vector unsigned int test_vec_vec_splati_ui(void) {
+  // CHECK: ret <4 x i32>
+  return vec_splati(1);
+}
+
+vector float test_vec_vec_splati_f(void) {
+  // CHECK: ret <4 x float>
+  return vec_splati(1.0f);
+}
+
+vector double test_vec_vec_splatid(void) {
+  // CHECK: ret <2 x double>
+  return vec_splatid(1.0);
+}
+
+vector signed int test_vec_vec_splati_ins_si(void) {
+  // CHECK-BE: insertelement <4 x i32>
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: insertelement <4 x i32>
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vsia, 0, 1);
+}
+
+vector unsigned int test_vec_vec_splati_ins_ui(void) {
+  // CHECK-BE: insertelement <4 x i32>
+  // CHECK-BE: ret <4 x i32>
+  // CHECK-LE: insertelement <4 x i32>
+  // CHECK-LE: ret <4 x i32>
+  return vec_splati_ins(vuia, 0, (unsigned int)1);
+}
+
+vector float test_vec_vec_splati_ins_f(void) {
+  // CHECK-BE: insertelement <4 x float>
+  // CHECK-BE: ret <4 x float>
+  // CHECK-LE: insertelement <4 x float>
+  // CHECK-LE: ret <4 x float>
+  return vec_splati_ins(vfa, 0, 1.0);
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xxgenpcvhm :
       PowerPC_VSX_Intrinsic<"xxgenpcvhm", [llvm_v8i16_ty],
                             [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxgenpcvwm :
       PowerPC_VSX_Intrinsic<"xxgenpcvwm", [llvm_v4i32_ty],
                             [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxgenpcvdm :
       PowerPC_VSX_Intrinsic<"xxgenpcvdm", [llvm_v2i64_ty],
                             [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
+// P10 VSX Vector Splat.
+def int_ppc_vsx_xxspltiw : GCCBuiltin<"__builtin_vsx_xxspltiw">,
+              Intrinsic<[llvm_v4i32_ty],[llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<0>>]>;
+def  int_ppc_vsx_xxspltidp: GCCBuiltin<"__builtin_vsx_xxspltidp">,
+              Intrinsic<[llvm_v2f64_ty],[llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<0>>]>;
+def  int_ppc_vsx_xxsplti32dx: GCCBuiltin<"__builtin_vsx_xxsplti32dx">,
+              Intrinsic<[llvm_v4i32_ty],[llvm_v4i32_ty,llvm_i1_ty,llvm_i32_ty],
+                        [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC QPX Intrinsics.
 //
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics.

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     /// VPERM - The PPC VPERM Instruction.
     ///
     VPERM,
 
     /// XXSPLT - The PPC VSX splat instructions
     ///
     XXSPLT,
 
+    /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for
+    /// converting immediate single precision numbers to double precision
+    /// vector or scalar.
+    XXSPLTI_SP_TO_DP,
+
     /// VECINSERT - The PPC vector insert instruction
     ///
     VECINSERT,
 
     /// VECSHL - The PPC vector shift left instruction
     ///
     VECSHL,
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case PPCISD::FP_TO_UINT_IN_VSR:
                                 return "PPCISD::FP_TO_UINT_IN_VSR,";
   case PPCISD::FP_TO_SINT_IN_VSR:
                                 return "PPCISD::FP_TO_SINT_IN_VSR";
   case PPCISD::FRE:             return "PPCISD::FRE";
   case PPCISD::FRSQRTE:         return "PPCISD::FRSQRTE";
   case PPCISD::STFIWX:          return "PPCISD::STFIWX";
   case PPCISD::VPERM:           return "PPCISD::VPERM";
   case PPCISD::XXSPLT:          return "PPCISD::XXSPLT";
+  case PPCISD::XXSPLTI_SP_TO_DP:
+                                return "PPCISD::XXSPLTI_SP_TO_DP";
   case PPCISD::VECINSERT:       return "PPCISD::VECINSERT";
   case PPCISD::XXPERMDI:        return "PPCISD::XXPERMDI";
   case PPCISD::VECSHL:          return "PPCISD::VECSHL";
   case PPCISD::CMPB:            return "PPCISD::CMPB";
   case PPCISD::Hi:              return "PPCISD::Hi";
   case PPCISD::Lo:              return "PPCISD::Lo";
   case PPCISD::TOC_ENTRY:       return "PPCISD::TOC_ENTRY";
   case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def SDT_PPCvperm   : SDTypeProfile<1, 3, [
   SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
 ]>;
 
 def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
   SDTCisVec<1>, SDTCisInt<2>
 ]>;
 
+def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>,
+  SDTCisInt<1>
+]>;
+
 def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>,
   SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3>
 ]>;
 
 def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>,
   SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3>
 ]>;
 
def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR",
                                SDTypeProfile<1, 3, [
                                  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
                                  SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>;
 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
 def PPCaddiDtprelL   : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
 
 def PPCvperm     : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
 def PPCxxsplt    : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
+def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>;
 def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>;
 def PPCxxpermdi  : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>;
 def PPCvecshl    : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>;
 
 def PPCqvfperm   : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
 def PPCqvgpci    : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
 def PPCqvaligni  : SDNode<"PPCISD::QVALIGNI", SDT_PPCqvaligni, []>;
 def PPCqvesplati : SDNode<"PPCISD::QVESPLATI", SDT_PPCqvesplati, []>;

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

class XForm_XT6_IMM5_VB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
   let Pattern = pattern;
   let Inst{6-10} = XT{4-0};
   let Inst{11-15} = IMM;
   let Inst{16-20} = VRB;
   let Inst{21-30} = xo;
   let Inst{31} = XT{5};
 }
 
+// 8RR:D-Form: [ 1 1 0 // // imm0 
+//               PO T XO TX imm1 ].
+class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 
+                          string asmstr, InstrItinClass itin,
+                          list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<32> IMM32;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 1; 
+  let Inst{8-11} = 0; 
+  let Inst{12-13} = 0; // reserved
+  let Inst{14-15} = 0; // reserved
+  let Inst{16-31} = IMM32{31-16};
+
+  // The instruction.
+  let Inst{38-42} = XT{4-0};
+  let Inst{43-46} = xo;
+  let Inst{47} = XT{5};
+  let Inst{48-63} = IMM32{15-0};
+}
+
+// 8RR:D-Form: [ 1 1 0 // // imm0
+//               PO T XO IX TX imm1 ].
+class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
+                             string asmstr, InstrItinClass itin,
+                             list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bit IX;
+  bits<32> IMM32;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 1;
+  let Inst{8-11} = 0;
+  let Inst{12-13} = 0; // reserved
+  let Inst{14-15} = 0; // reserved
+  let Inst{16-31} = IMM32{31-16};
+
+  // The instruction.
+  let Inst{38-42} = XT{4-0};
+  let Inst{43-45} = xo;
+  let Inst{46} = IX;
+  let Inst{47} = XT{5};
+  let Inst{48-63} = IMM32{15-0};
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
                                        dag PCRel_IOL, string asmstr,
                                        InstrItinClass itin> {
   def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
                                        !strconcat(asmstr, ", 0"), itin, []>;
   def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
                                      !strconcat(asmstr, ", 1"), itin, []>,
                                      isPCRel;
def : Pat<(PPCstore_scal_int_from_vsr
               (PPCmatpcreladdr pcreladdr:$dst), 8),
             (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
 
   // If the PPCmatpcreladdr node is not caught by any other pattern it should be
   // caught here and turned into a paddi instruction to materialize the address.
   def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
 }
 
+let Predicates = [PrefixInstrs] in {
+  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
+                                     (ins i32imm:$IMM32),
+                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
+                                     []>;
+  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
+                                      (ins i32imm:$IMM32),
+                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
+                                      [(set v2f64:$XT,
+                                        (PPCxxspltidp i32:$IMM32))]>;
+  def XXSPLTI32DX :
+      8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
+                             (ins vsrc:$XTi, i1imm:$IX, i32imm:$IMM32),
+                             "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, []>,
+                             RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+
+  def : Pat<(int_ppc_vsx_xxspltiw timm:$A),
+            (XXSPLTIW $A)>;
+  def : Pat<(int_ppc_vsx_xxspltidp timm:$A),
+            (XXSPLTIDP $A)>;
+  def : Pat<(int_ppc_vsx_xxsplti32dx v4i32:$A, i1:$B, timm:$C),
+            (XXSPLTI32DX $A, $B, $C)>;
+}
+
 let Predicates = [IsISA3_1] in {
    def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,
                          (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
    def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpextd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,

llvm/test/CodeGen/PowerPC/p10-permute-ops.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr10 \
+; RUN:   -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
+
+
+define <4 x i32> @testXXSPLTIW() {
+; CHECK-LABEL: testXXSPLTIW:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxspltiw v2, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.xxspltiw(i32 1)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.xxspltiw(i32 immarg)
+
+define <2 x double> @testXXSPLTIDP() {
+; CHECK-LABEL: testXXSPLTIDP:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxspltidp v2, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <2 x double> @llvm.ppc.vsx.xxspltidp(i32 1)
+  ret <2 x double> %0
+}
+declare <2 x double> @llvm.ppc.vsx.xxspltidp(i32 immarg)
+
+define <4 x i32> @testXXSPLTI32DX(<4 x i32> %a) {
+; CHECK-LABEL: testXXSPLTI32DX:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xxsplti32dx v2, -1, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.xxsplti32dx(<4 x i32> %a, i1 true, i32 1)
+  ret <4 x i32> %0
+}
+declare <4 x i32> @llvm.ppc.vsx.xxsplti32dx(<4 x i32>, i1 immarg, i32 immarg)

llvm/test/MC/Disassembler/PowerPC/p10insts.txt

 # CHECK xxgenpcvdm 0, 1, 2
 0xf0 0x02 0x0f 0x6a
 
 # CHECK: vclrlb 1, 4, 3
 0x10 0x24 0x19 0x8d
 
 # CHECK: vclrrb 1, 4, 3
 0x10 0x24 0x19 0xcd
+
+# Boundary conditions of 8RR_DForm_IMM32_XT6's immediates
+# CHECK: xxspltiw 63, 4294901760
+0x05 0x00 0xff 0xff 0x83 0xe7 0x00 0x00
+
+# CHECK: xxspltiw 63, 65535
+0x05 0x00 0x00 0x00 0x83 0xe7 0xff 0xff
+
+# CHECK: xxspltiw 63, 4294967295
+0x05 0x00 0xff 0xff 0x83 0xe7 0xff 0xff
+
+# CHECK: xxspltidp 63, 4294967295
+0x05 0x00 0xff 0xff 0x83 0xe5 0xff 0xff
+
+# Boundary conditions of 8RR_DForm_IMM32_XT6_IX's immediates
+# CHECK: xxsplti32dx 63, 1, 4294901760
+0x05 0x00 0xff 0xff 0x83 0xe3 0x00 0x00
+
+# CHECK: xxsplti32dx 63, 1, 65535
+0x05 0x00 0x00 0x00 0x83 0xe3 0xff 0xff
+
+# CHECK: xxsplti32dx 63, 1, 4294967295
+0x05 0x00 0xff 0xff 0x83 0xe3 0xff 0xff

llvm/test/MC/PowerPC/p10.s

 # CHECK-LE: xxgenpcvdm 0, 1, 2                    # encoding: [0x6a,0x0f,0x02,0xf0]
             xxgenpcvdm 0, 1, 2
 # CHECK-BE: vclrlb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0x8d]
 # CHECK-LE: vclrlb 1, 4, 3                        # encoding: [0x8d,0x19,0x24,0x10]
             vclrlb 1, 4, 3
 # CHECK-BE: vclrrb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0xcd]
 # CHECK-LE: vclrrb 1, 4, 3                        # encoding: [0xcd,0x19,0x24,0x10]
             vclrrb 1, 4, 3
+# Boundary conditions of 8RR_DForm_IMM32_XT6's immediates
+# CHECK-BE: xxspltiw 63, 4294901760         # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                         0x83,0xe7,0x00,0x00]
+# CHECK-LE: xxspltiw 63, 4294901760         # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                         0x00,0x00,0xe7,0x83]
+            xxspltiw 63, 4294901760
+# CHECK-BE: xxspltiw 63, 65535              # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                         0x83,0xe7,0xff,0xff]
+# CHECK-LE: xxspltiw 63, 65535              # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                         0xff,0xff,0xe7,0x83]
+            xxspltiw 63, 65535
+# CHECK-BE: xxspltiw 63, 4294967295         # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                         0x83,0xe7,0xff,0xff]
+# CHECK-LE: xxspltiw 63, 4294967295         # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                         0xff,0xff,0xe7,0x83]
+            xxspltiw 63, 4294967295
+# CHECK-BE: xxspltiw 63, -1                 # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                         0x83,0xe7,0xff,0xff]
+# CHECK-LE: xxspltiw 63, -1                 # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                         0xff,0xff,0xe7,0x83]
+            xxspltiw 63, -1
+# CHECK-BE: xxspltidp 63, 4294967295        # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                         0x83,0xe5,0xff,0xff]
+# CHECK-LE: xxspltidp 63, 4294967295        # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                         0xff,0xff,0xe5,0x83]
+            xxspltidp 63, 4294967295
+# Boundary conditions of 8RR_DForm_IMM32_XT6_IX's immediates
+# CHECK-BE: xxsplti32dx 63, 1, 4294901760   # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                         0x83,0xe3,0x00,0x00]
+# CHECK-LE: xxsplti32dx 63, 1, 4294901760   # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                         0x00,0x00,0xe3,0x83]
+            xxsplti32dx 63, 1, 4294901760
+# CHECK-BE: xxsplti32dx 63, 1, 65535        # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                         0x83,0xe3,0xff,0xff]
+# CHECK-LE: xxsplti32dx 63, 1, 65535        # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                         0xff,0xff,0xe3,0x83]
+            xxsplti32dx 63, 1, 65535
+# CHECK-BE: xxsplti32dx 63, 1, 4294967295   # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                         0x83,0xe3,0xff,0xff]
+# CHECK-LE: xxsplti32dx 63, 1, 4294967295   # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                         0xff,0xff,0xe3,0x83]
+            xxsplti32dx 63, 1, 4294967295
+# CHECK-BE: xxsplti32dx 63, 1, -1           # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                         0x83,0xe3,0xff,0xff]
+# CHECK-LE: xxsplti32dx 63, 1, -1           # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                         0xff,0xff,0xe3,0x83]
+            xxsplti32dx 63, 1, -1