Implemented Builtins for Load VSX Vector and sign extend and zero extend along with appropriate test cases. The new instructions are used for ZEXT but SEXT will continue to use the previously generated ASM.
Details
- Reviewers
nemanjai saghir hfinkel amyk - Group Reviewers
Restricted Project - Commits
- rG331dcc43eac2: [PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll | ||
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56 ↗ | (On Diff #273421) | these were extra checks that I should've removed; thanks for catching it |
llvm/lib/Target/PowerPC/PPCISelLowering.h | ||
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501 | missing ,? | |
llvm/lib/Target/PowerPC/PPCInstrPrefix.td | ||
526 | We should put all such def at the top of this file under: // PowerPC specific type constraints. | |
530 | Put these under the type constraints section and doc with: // PowerPC specific DAG Nodes. | |
llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll | ||
3 ↗ | (On Diff #275124) | remve extra line. Makes the comment harder to read. |
10 ↗ | (On Diff #275124) | You don't need the local_unnamed_addr #0 |
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | ||
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13670 | nit: don't need () aroud !ValidLDType | |
13676 | I don't think we need to explicitly say this sine everything we do here is for pattern matching to appropriate instructions in the backend... | |
13677 | Can just merge this into the next line and remove this tmp value. | |
llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll | ||
6 ↗ | (On Diff #275423) | Please add tests for BE. |
Please update this patch to remove the instruction defs and MC tests. Also, you can update the patch to put your backend llc tests in the file I've introduced in: https://reviews.llvm.org/D82467
clang/test/CodeGen/builtins-ppc-p10vector.c | ||
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9 | unintended change? | |
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | ||
13675 | You did not assign anything here? |
Removed duplicate test code found in the instructions and MC Test implementation of VSX Vector store and load with sign extend or zero extend; re-added a test file that was omitted in the last diff update.
I think the patterns for the load instructions may have accidentally been deleted. Please add them back to the patch. Thank you.
Restored accidentally deleted pattern, removed duplicate tests, moved new tests to another pre-existing file instead.
The title of the patch mentions both zero extend and sign extend.
However, it seems that we only have instructions for the zero extend case. Is that right?
I see both types of tests in:
test/CodeGen/builtins-ppc-p10vector.c
But I only see codegen tests for the zreo extend version.
test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
I bring it up because I want to make sure that this is intentional.
clang/lib/Headers/altivec.h | ||
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16564 | I'm a little confused about this. | |
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | ||
13671 | It looks like you are doing this for zero extend only. | |
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll | ||
60 | nit: |
Addressed formatting comments
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | ||
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13664 | I'm not too sure what you mean, would you be able to elaborate?
Thanks! |
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | ||
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13664 | Extra the in your sentence: |
Could we also elaborate in the description on how we are utilizing the new load instructions for zero extend case but not the sign extend case?
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | ||
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13674 | Over 80 characters? | |
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll | ||
6 | This line actually is for -O0 and not a BE RUN line. I believe the most up to date version of the test includes the LE, BE and O0 line. |
Clang formatted relevant lines, combined LE and BE tests as they produced the same ASM.
I realized I didn't put a comment on this earlier but this overall LGTM, but I think it would be good to see if @nemanjai has any additional comments on this patch.