[PowerPC][Power10] Implement Truncate and Store VSX Vector Builtins

[amyk]

Summary

This patch implements the following function prototypes for the truncate and store VSX Vector instructions:

void vec_xst_trunc (vector signed __int128, signed long long, signed char *);
void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *);

void vec_xst_trunc (vector signed __int128, signed long long, signed short *);
void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned short *);

void vec_xst_trunc (vector signed __int128, signed long long, signed int *);
void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned int *);

void vec_xst_trunc (vector signed __int128, signed long long, signed long long *);
void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned long long *);

Depends on D82431.

[amyk]

Updated the patch to move the MC/llc tests into the appropriate files.

[amyk]

Update the patch to place MC tests into appropriate files.

[lei]

Please move encoding tests to ppc64-encoding-ISA31.[txt|s].

clang/test/CodeGen/builtins-ppc-p10vector.c

647

I don't see a run line above that uses CHECK-BE|CHECK-LE. Since all these look the same, did you mean to use the default CHECK?

[amyk]

clang/test/CodeGen/builtins-ppc-p10vector.c

647

You're right - unfortunately in the previous tests that use CHECK-BE/CHECK-LE that were committed, I did not realize that I forgot to upstream the appropriate RUN lines... If it is okay, I can add them into this patch when I update it.

[lei]

clang/test/CodeGen/builtins-ppc-p10vector.c

647

Not sure what you mean by appropriate RUN lines. From the checks you are adding seems there is no diff between BE and LE so both can use the default CHECK.

[amyk]

Rebased patch, and addressed review comments of having a single CHECK.

[NeHuang]

llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

2

Do we also need to run for big endian?

[stefanp]

LGTM.

Please wait for Lei to give the approval as well before you commit.

llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

2

I don't think it would hurt to add a BE run for this as well. the only thing to watch out for is the fact that this is not actually a new file. This test file already exists on master so I assume that this will be merged in (and not added as a new file).

[lei]

LGTM,
Please add tests for BE in llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll prior to committing.

llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

2

I believe this is a new file 🙂

[amyk]

The llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll file actually exists, but does not have a BE RUN line. I realized I didn't rebase this diff to my previous patch that introduced it. Thus on the commit, I will append my tests to that file and add a BE line to it.

clang/lib/Headers/altivec.h

 static inline __ATTRS_o_ai void vec_xst(vector unsigned __int128 __vec,
                                         signed long long __offset,
                                         unsigned __int128 *__ptr) {
   signed char *__addr = (signed char *)__ptr + __offset;
   *(unaligned_vec_ui128 *)__addr = __vec;
 }
 #endif
 
+/* vec_xst_trunc */
+
+#if defined(__POWER10_VECTOR__) && defined(__VSX__)
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+                                              signed long long __offset,
+                                              signed char *__ptr) {
+  *(__ptr + __offset) = (signed char)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+                                              signed long long __offset,
+                                              unsigned char *__ptr) {
+  *(__ptr + __offset) = (unsigned char)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+                                              signed long long __offset,
+                                              signed short *__ptr) {
+  *(__ptr + __offset) = (signed short)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+                                              signed long long __offset,
+                                              unsigned short *__ptr) {
+  *(__ptr + __offset) = (unsigned short)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+                                              signed long long __offset,
+                                              signed int *__ptr) {
+  *(__ptr + __offset) = (signed int)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+                                              signed long long __offset,
+                                              unsigned int *__ptr) {
+  *(__ptr + __offset) = (unsigned int)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector signed __int128 __vec,
+                                              signed long long __offset,
+                                              signed long long *__ptr) {
+  *(__ptr + __offset) = (signed long long)__vec[0];
+}
+
+static inline __ATTRS_o_ai void vec_xst_trunc(vector unsigned __int128 __vec,
+                                              signed long long __offset,
+                                              unsigned long long *__ptr) {
+  *(__ptr + __offset) = (unsigned long long)__vec[0];
+}
+#endif
+
 /* vec_xst_be */
 
 #ifdef __LITTLE_ENDIAN__
 static __inline__ void __ATTRS_o_ai vec_xst_be(vector signed char __vec,
                                                signed long long  __offset,
                                                signed char *__ptr) {
   vector signed char __tmp =
      __builtin_shufflevector(__vec, __vec, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14,

clang/test/CodeGen/builtins-ppc-p10vector.c

vector float test_vec_vec_splati_ins_f(void) {
   // CHECK:  [[T1:%.+]] = sub i32 1, %{{.+}}
   // CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T1]]
   // CHECK:  [[T2:%.+]] = sub i32 3, %{{.+}}
   // CHECK: insertelement <4 x float> %{{.+}}, float %{{.+}}, i32 [[T2]]
   // CHECK: ret <4 x float>
   return vec_splati_ins(vfa, 0, 1.0f);
 }
 
+void test_vec_xst_trunc_sc(vector signed __int128 __a, signed long long __b,
+                           signed char *__c) {
+  // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_uc(vector unsigned __int128 __a, signed long long __b,
+                           unsigned char *__c) {
+  // CHECK: store i8 %{{.+}}, i8* %{{.+}}, align 1
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_ss(vector signed __int128 __a, signed long long __b,
+                           signed short *__c) {
+  // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_us(vector unsigned __int128 __a, signed long long __b,
+                           unsigned short *__c) {
+  // CHECK: store i16 %{{.+}}, i16* %{{.+}}, align 2
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_si(vector signed __int128 __a, signed long long __b,
+                           signed int *__c) {
+  // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_ui(vector unsigned __int128 __a, signed long long __b,
+                           unsigned int *__c) {
+  // CHECK: store i32 %{{.+}}, i32* %{{.+}}, align 4
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_sll(vector signed __int128 __a, signed long long __b,
+                            signed long long *__c) {
+  // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8
+  vec_xst_trunc(__a, __b, __c);
+}
+
+void test_vec_xst_trunc_ull(vector unsigned __int128 __a, signed long long __b,
+                            unsigned long long *__c) {
+  // CHECK: store i64 %{{.+}}, i64* %{{.+}}, align 8
+  vec_xst_trunc(__a, __b, __c);
+}
+
 int test_vec_test_lsbb_all_ones(void) {
   // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 1
   // CHECK-NEXT: ret i32
   return vec_test_lsbb_all_ones(vuca);
 }
 
 int test_vec_test_lsbb_all_zeros(void) {
   // CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 0
   // CHECK-NEXT: ret i32
   return vec_test_lsbb_all_zeros(vuca);
 }

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [IsISA3_1] in {
   def : Pat<(v2i64 (int_ppc_vsx_xxgenpcvdm v2i64:$VRB, imm:$IMM)),
             (v2i64 (COPY_TO_REGCLASS (XXGENPCVDM $VRB, imm:$IMM), VRRC))>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 1)),
             (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
   def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
             (EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
 }
 
+let AddedComplexity = 400, Predicates = [IsISA3_1] in {
+  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$rS, 0)), xoaddr:$src),
+            (STXVRBX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
+  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$rS, 0)), xoaddr:$src),
+            (STXVRHX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
+  def : Pat<(store (i32 (vector_extract v4i32:$rS, 0)), xoaddr:$src),
+            (STXVRWX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
+  def : Pat<(store (i64 (vector_extract v2i64:$rS, 0)), xoaddr:$src),
+            (STXVRDX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
+}
+
 let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
  def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A)),
            (v4i32 (XXSPLTIW imm:$A))>;
  def : Pat<(f32 nzFPImmAsi32:$A),
            (COPY_TO_REGCLASS (XXSPLTIDP (getFPAs32BitInt fpimm:$A)),

llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
 ; RUN:   FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-O0
 
 ; These test cases aims to test the builtins for the Power10 VSX vector
 ; instructions introduced in ISA 3.1.
 
 declare i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8>, i32)
 
 define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
 ; CHECK-LABEL: test_vec_test_lsbb_all_ones:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xvtlsbb cr0, v2
 ; CHECK-NEXT:    mfocrf r3, 128
 ; CHECK-NEXT:    srwi r3, r3, 31
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: test_vec_test_lsbb_all_ones:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    xvtlsbb cr0, v2
+; CHECK-O0-NEXT:    mfocrf r3, 128
+; CHECK-O0-NEXT:    srwi r3, r3, 31
+; CHECK-O0-NEXT:    extsw r3, r3
+; CHECK-O0-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 1)
   ret i32 %0
 }
 
 define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
 ; CHECK-LABEL: test_vec_test_lsbb_all_zeros:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xvtlsbb cr0, v2
 ; CHECK-NEXT:    mfocrf r3, 128
 ; CHECK-NEXT:    rlwinm r3, r3, 3, 31, 31
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: test_vec_test_lsbb_all_zeros:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    xvtlsbb cr0, v2
+; CHECK-O0-NEXT:    mfocrf r3, 128
+; CHECK-O0-NEXT:    rlwinm r3, r3, 3, 31, 31
+; CHECK-O0-NEXT:    extsw r3, r3
+; CHECK-O0-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 0)
   ret i32 %0
 }
+
+define void @vec_xst_trunc_sc(<1 x i128> %__vec, i64 %__offset, i8* nocapture %__ptr) {
+; CHECK-LABEL: vec_xst_trunc_sc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvrbx v2, r6, r5
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_sc:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    li r3, 0
+; CHECK-O0-NEXT:    vextubrx r3, r3, v2
+; CHECK-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
+; CHECK-O0-NEXT:    add r4, r6, r5
+; CHECK-O0-NEXT:    stb r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <16 x i8>
+  %conv = extractelement <16 x i8> %0, i32 0
+  %add.ptr = getelementptr inbounds i8, i8* %__ptr, i64 %__offset
+  store i8 %conv, i8* %add.ptr, align 1
+  ret void
+}
+
+define void @vec_xst_trunc_uc(<1 x i128> %__vec, i64 %__offset, i8* nocapture %__ptr) {
+; CHECK-LABEL: vec_xst_trunc_uc:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stxvrbx v2, r6, r5
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_uc:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    li r3, 0
+; CHECK-O0-NEXT:    vextubrx r3, r3, v2
+; CHECK-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
+; CHECK-O0-NEXT:    add r4, r6, r5
+; CHECK-O0-NEXT:    stb r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <16 x i8>
+  %conv = extractelement <16 x i8> %0, i32 0
+  %add.ptr = getelementptr inbounds i8, i8* %__ptr, i64 %__offset
+  store i8 %conv, i8* %add.ptr, align 1
+  ret void
+}
+
+define void @vec_xst_trunc_ss(<1 x i128> %__vec, i64 %__offset, i16* nocapture %__ptr) {
+; CHECK-LABEL: vec_xst_trunc_ss:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sldi r3, r5, 1
+; CHECK-NEXT:    stxvrhx v2, r6, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_ss:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    li r3, 0
+; CHECK-O0-NEXT:    vextuhrx r3, r3, v2
+; CHECK-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
+; CHECK-O0-NEXT:    sldi r4, r5, 1
+; CHECK-O0-NEXT:    add r4, r6, r4
+; CHECK-O0-NEXT:    sth r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <8 x i16>
+  %conv = extractelement <8 x i16> %0, i32 0
+  %add.ptr = getelementptr inbounds i16, i16* %__ptr, i64 %__offset
+  store i16 %conv, i16* %add.ptr, align 2
+  ret void
+}
+
+define void @vec_xst_trunc_us(<1 x i128> %__vec, i64 %__offset, i16* nocapture %__ptr) {
+; CHECK-LABEL: vec_xst_trunc_us:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sldi r3, r5, 1
+; CHECK-NEXT:    stxvrhx v2, r6, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_us:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    li r3, 0
+; CHECK-O0-NEXT:    vextuhrx r3, r3, v2
+; CHECK-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
+; CHECK-O0-NEXT:    sldi r4, r5, 1
+; CHECK-O0-NEXT:    add r4, r6, r4
+; CHECK-O0-NEXT:    sth r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <8 x i16>
+  %conv = extractelement <8 x i16> %0, i32 0
+  %add.ptr = getelementptr inbounds i16, i16* %__ptr, i64 %__offset
+  store i16 %conv, i16* %add.ptr, align 2
+  ret void
+}
+
+define void @vec_xst_trunc_si(<1 x i128> %__vec, i64 %__offset, i32* nocapture %__ptr) {
+; CHECK-LABEL: vec_xst_trunc_si:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sldi r3, r5, 2
+; CHECK-NEXT:    stxvrwx v2, r6, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_si:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    li r3, 0
+; CHECK-O0-NEXT:    vextuwrx r3, r3, v2
+; CHECK-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
+; CHECK-O0-NEXT:    sldi r4, r5, 2
+; CHECK-O0-NEXT:    add r4, r6, r4
+; CHECK-O0-NEXT:    stw r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <4 x i32>
+  %conv = extractelement <4 x i32> %0, i32 0
+  %add.ptr = getelementptr inbounds i32, i32* %__ptr, i64 %__offset
+  store i32 %conv, i32* %add.ptr, align 4
+  ret void
+}
+
+define void @vec_xst_trunc_ui(<1 x i128> %__vec, i64 %__offset, i32* nocapture %__ptr) {
+; CHECK-LABEL: vec_xst_trunc_ui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sldi r3, r5, 2
+; CHECK-NEXT:    stxvrwx v2, r6, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_ui:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    li r3, 0
+; CHECK-O0-NEXT:    vextuwrx r3, r3, v2
+; CHECK-O0-NEXT:    # kill: def $r3 killed $r3 killed $x3
+; CHECK-O0-NEXT:    sldi r4, r5, 2
+; CHECK-O0-NEXT:    add r4, r6, r4
+; CHECK-O0-NEXT:    stw r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <4 x i32>
+  %conv = extractelement <4 x i32> %0, i32 0
+  %add.ptr = getelementptr inbounds i32, i32* %__ptr, i64 %__offset
+  store i32 %conv, i32* %add.ptr, align 4
+  ret void
+}
+
+define void @vec_xst_trunc_sll(<1 x i128> %__vec, i64 %__offset, i64* nocapture %__ptr)  {
+; CHECK-LABEL: vec_xst_trunc_sll:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sldi r3, r5, 3
+; CHECK-NEXT:    stxvrdx v2, r6, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_sll:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    mfvsrld r3, v2
+; CHECK-O0-NEXT:    sldi r4, r5, 3
+; CHECK-O0-NEXT:    add r4, r6, r4
+; CHECK-O0-NEXT:    std r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <2 x i64>
+  %conv = extractelement <2 x i64> %0, i32 0
+  %add.ptr = getelementptr inbounds i64, i64* %__ptr, i64 %__offset
+  store i64 %conv, i64* %add.ptr, align 8
+  ret void
+}
+
+define void @vec_xst_trunc_ull(<1 x i128> %__vec, i64 %__offset, i64* nocapture %__ptr)  {
+; CHECK-LABEL: vec_xst_trunc_ull:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    sldi r3, r5, 3
+; CHECK-NEXT:    stxvrdx v2, r6, r3
+; CHECK-NEXT:    blr
+;
+; CHECK-O0-LABEL: vec_xst_trunc_ull:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    mfvsrld r3, v2
+; CHECK-O0-NEXT:    sldi r4, r5, 3
+; CHECK-O0-NEXT:    add r4, r6, r4
+; CHECK-O0-NEXT:    std r3, 0(r4)
+; CHECK-O0-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %__vec to <2 x i64>
+  %conv = extractelement <2 x i64> %0, i32 0
+  %add.ptr = getelementptr inbounds i64, i64* %__ptr, i64 %__offset
+  store i64 %conv, i64* %add.ptr, align 8
+  ret void
+}