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[PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend
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Authored by Conanap on Jul 7 2020, 6:04 PM.

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Summary

Includes instruction defintion and MC Tests for above instructions.

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Event Timeline

Conanap created this revision.Jul 7 2020, 6:04 PM
amyk accepted this revision as: amyk.Jul 8 2020, 7:46 AM
amyk added a subscriber: amyk.

This LGTM.

This revision is now accepted and ready to land.Jul 8 2020, 7:46 AM
kamaub accepted this revision.Jul 8 2020, 8:14 AM
kamaub added a subscriber: kamaub.

LGTM

lei added a subscriber: lei.Jul 8 2020, 9:12 AM
lei added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
431

Instead of creating a new section like this, why not add to the existing one on line 469? I realize that does not have Predicates = [IsISA3_1], but I think that is an oversight from previous patch and it should be added as those instructions are also part of ISA3.1.

439

same.

Conanap updated this revision to Diff 276564.Jul 8 2020, 2:58 PM

Relocated some of the instructions to a more appropriate place.

Conanap marked 2 inline comments as done.Jul 8 2020, 2:58 PM

Relocated the isntr definitions to a more appropriate place.

lei accepted this revision.Jul 9 2020, 11:15 AM

LGTM thx.

bsaleil added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
947

Shouldn't mayStore be 0 instead of 1 here ?

Conanap marked an inline comment as done.Jul 9 2020, 1:33 PM
Conanap added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
947

yes, thanks; will fix on the commit

This revision was automatically updated to reflect the committed changes.