[XCOFF][AIX] Use 'L..' instead of '.L' for getPrivateGlobalPrefix in DataLayout

[jasonliu]

Summary

D80831 changed part of the prefix usage for AIX. But there are other places getting prefix from DataLayout.
This patch intends to make prefix usage consistent on AIX.

[hubert.reinterpretcast]

llvm/lib/IR/DataLayout.cpp

450

This is an addition to the IR. Should there be a bitcode test?

[hubert.reinterpretcast]

llvm/lib/IR/DataLayout.cpp

450

There should be an update to the LLVM Language Reference Manual.

[daltenty]

Based on the result of the pre-merge checks, do we need to include the clang change in the scope here?

[jasonliu]

In D81270#2079731, @daltenty wrote:

Based on the result of the pre-merge checks, do we need to include the clang change in the scope here?

Yes, looks like I need to include the clang portion as well. Thanks!

[jasonliu]

Added clang portion of the change.
Added unittest to test mangler.
Added description in Language Reference Manual.

[jasonliu]

llvm/lib/IR/DataLayout.cpp

450

This is an addition to the IR. Should there be a bitcode test?

I added an unittest in IR, hope that's enough.

[hubert.reinterpretcast]

clang/lib/Basic/Targets/PPC.h

351 ↗

(On Diff #269304)

Triple.isOSAIX() is used by D79719; do we want to be consistent in using that?

400 ↗

(On Diff #269304)

Triple.isOSAIX() is used by D79719; do we want to be consistent in using that?

[jasonliu]

Use Triple.isOSAIX() instead.

[jasonliu]

Gentle ping.

[hubert.reinterpretcast]

LGTM; thanks.

llvm/include/llvm/IR/DataLayout.h

private:
   FunctionPtrAlignType TheFunctionPtrAlignType;
 
   enum ManglingModeT {
     MM_None,
     MM_ELF,
     MM_MachO,
     MM_WinCOFF,
     MM_WinCOFFX86,
-    MM_Mips
+    MM_Mips,
+    MM_XCOFF
   };
   ManglingModeT ManglingMode;
 
   SmallVector<unsigned char, 8> LegalIntWidths;
 
   /// Primitive type alignment data. This is sorted by type and bit
   /// width during construction.
   using AlignmentsTy = SmallVector<LayoutAlignElem, 16>;
public:
   }
 
   char getGlobalPrefix() const {
     switch (ManglingMode) {
     case MM_None:
     case MM_ELF:
     case MM_Mips:
     case MM_WinCOFF:
+    case MM_XCOFF:
       return '\0';
     case MM_MachO:
     case MM_WinCOFFX86:
       return '_';
     }
     llvm_unreachable("invalid mangling mode");
   }
 
   StringRef getPrivateGlobalPrefix() const {
     switch (ManglingMode) {
     case MM_None:
       return "";
     case MM_ELF:
     case MM_WinCOFF:
       return ".L";
     case MM_Mips:
       return "$";
     case MM_MachO:
     case MM_WinCOFFX86:
       return "L";
+    case MM_XCOFF:
+      return "L..";
     }
     llvm_unreachable("invalid mangling mode");
   }
 
   static const char *getManglingComponent(const Triple &T);
 
   /// Returns true if the specified type fits in a native integer type
   /// supported by the CPU.

llvm/lib/IR/DataLayout.cpp

 //                       DataLayout Class Implementation
 //===----------------------------------------------------------------------===//
 
 const char *DataLayout::getManglingComponent(const Triple &T) {
   if (T.isOSBinFormatMachO())
     return "-m:o";
   if (T.isOSWindows() && T.isOSBinFormatCOFF())
     return T.getArch() == Triple::x86 ? "-m:x" : "-m:w";
+  if (T.isOSBinFormatXCOFF())
+    return "-m:a";
   return "-m:e";
 }
 
 static const LayoutAlignElem DefaultAlignments[] = {
     {INTEGER_ALIGN, 1, Align(1), Align(1)},    // i1
     {INTEGER_ALIGN, 8, Align(1), Align(1)},    // i8
     {INTEGER_ALIGN, 16, Align(2), Align(2)},   // i16
     {INTEGER_ALIGN, 32, Align(4), Align(4)},   // i32
void DataLayout::reset(StringRef Desc) {
   NonIntegralAddressSpaces.clear();
 
   // Default alignments
   for (const LayoutAlignElem &E : DefaultAlignments) {
     setAlignment((AlignTypeEnum)E.AlignType, E.ABIAlign, E.PrefAlign,
                  E.TypeBitWidth);
   }
   setPointerAlignment(0, Align(8), Align(8), 8, 8);
   
   parseSpecifier(Desc);
 }
 
 /// Checked version of split, to ensure mandatory subparts.
 static std::pair<StringRef, StringRef> split(StringRef Str, char Separator) {
   assert(!Str.empty() && "parse error, string can't be empty here");
   std::pair<StringRef, StringRef> Split = Str.split(Separator);
   if (Split.second.empty() && Split.first != Str)
case 'm':
         ManglingMode = MM_Mips;
         break;
       case 'w':
         ManglingMode = MM_WinCOFF;
         break;
       case 'x':
         ManglingMode = MM_WinCOFFX86;
         break;
+      case 'a':
+        ManglingMode = MM_XCOFF;
+        break;
       }
       break;
     default:
       report_fatal_error("Unknown specifier in datalayout string");
       break;
     }
   }
 }

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

 ; 64SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $x[[REG1]] :: (load 4 from constant-pool)
 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %const.0
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %const.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $x[[REG2]] :: (load 4 from constant-pool)
 
 ; 32SMALL-ASM:         .csect .rodata[RO],2
 ; 32SMALL-ASM:         .align  2
-; 32SMALL-ASM: .LCPI0_0:
+; 32SMALL-ASM: L..CPI0_0:
 ; 32SMALL-ASM:         .vbyte 4, 0x40b00000
 ; 32SMALL-ASM: .test_float:
 ; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], L..C0(2)
 ; 32SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 32SMALL-ASM:         blr
 
 ; 32LARGE-ASM:         .csect .rodata[RO],2
 ; 32LARGE-ASM:         .align  2
-; 32LARGE-ASM: .LCPI0_0:
+; 32LARGE-ASM: L..CPI0_0:
 ; 32LARGE-ASM:         .vbyte 4, 0x40b00000
 ; 32LARGE-ASM: .test_float:
 ; 32LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
 ; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; 32LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 32LARGE-ASM:         blr
 
 ; 64SMALL-ASM:         .csect .rodata[RO],2
 ; 64SMALL-ASM:         .align  2
-; 64SMALL-ASM: .LCPI0_0:
+; 64SMALL-ASM: L..CPI0_0:
 ; 64SMALL-ASM:         .vbyte 4, 0x40b00000
 ; 64SMALL-ASM: .test_float:
 ; 64SMALL-ASM:         ld [[REG1:[0-9]+]], L..C0(2)
 ; 64SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 64SMALL-ASM:         blr
 
 ; 64LARGE-ASM:         .csect .rodata[RO],2
 ; 64LARGE-ASM:         .align  2
-; 64LARGE-ASM: .LCPI0_0:
+; 64LARGE-ASM: L..CPI0_0:
 ; 64LARGE-ASM:         .vbyte 4, 0x40b00000
 ; 64LARGE-ASM: .test_float:
 ; 64LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
 ; 64LARGE-ASM:         ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; 64LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 64LARGE-ASM:         blr
 
 ; CHECK: .toc
-; CHECK: .tc .LCPI0_0[TC],.LCPI0_0
+; CHECK: .tc L..CPI0_0[TC],L..CPI0_0

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

 ; 32SMALL-ASM: L..BB0_3:
 ; 32SMALL-ASM: L..BB0_4:
 ; 32SMALL-ASM: L..BB0_5:
 ; 32SMALL-ASM: L..BB0_6:
 ; 32SMALL-ASM:      li 3, 0
 ; 32SMALL-ASM:      blr
 ; 32SMALL-ASM:      .csect .rodata[RO],2
 ; 32SMALL-ASM:      .align  2
-; 32SMALL-ASM: .LJTI0_0:
-; 32SMALL-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
-; 32SMALL-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
-; 32SMALL-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
-; 32SMALL-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
+; 32SMALL-ASM: L..JTI0_0:
+; 32SMALL-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
+; 32SMALL-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
+; 32SMALL-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
+; 32SMALL-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
 
 ; 32LARGE-ASM-LABEL: jump_table
 ; 32LARGE-ASM: .jump_table:
 ; 32LARGE-ASM:      addi 3, 3, -1
 ; 32LARGE-ASM:      cmplwi  3, 3
 ; 32LARGE-ASM:      bgt     0, L..BB0_6
 ; 32LARGE-ASM:      addis 4, L..C0@u(2)
 ; 32LARGE-ASM:      slwi 3, 3, 2
 ; 32LARGE-ASM:      lwz 4, L..C0@l(4)
 ; 32LARGE-ASM:      lwzx 3, 3, 4
 ; 32LARGE-ASM:      add 3, 3, 4
 ; 32LARGE-ASM:      mtctr 3
 ; 32LARGE-ASM:      bctr
 ; 32LARGE-ASM: L..BB0_2:
 ; 32LARGE-ASM: L..BB0_3:
 ; 32LARGE-ASM: L..BB0_4:
 ; 32LARGE-ASM: L..BB0_5:
 ; 32LARGE-ASM: L..BB0_6:
 ; 32LARGE-ASM:      li 3, 0
 ; 32LARGE-ASM:      blr
 ; 32LARGE-ASM:      .csect .rodata[RO],2
 ; 32LARGE-ASM:      .align  2
-; 32LARGE-ASM: .LJTI0_0:
-; 32LARGE-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
-; 32LARGE-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
-; 32LARGE-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
-; 32LARGE-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
+; 32LARGE-ASM: L..JTI0_0:
+; 32LARGE-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
+; 32LARGE-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
+; 32LARGE-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
+; 32LARGE-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
 
 ; 64SMALL-ASM-LABEL: jump_table
 ; 64SMALL-ASM: .jump_table:
 ; 64SMALL-ASM:      addi 3, 3, -1
 ; 64SMALL-ASM:      cmplwi  3, 3
 ; 64SMALL-ASM:      bgt     0, L..BB0_6
 ; 64SMALL-ASM:      ld 4, L..C0(2)
 ; 64SMALL-ASM:      rldic 3, 3, 2, 30
 ; 64SMALL-ASM:      lwax 3, 3, 4
 ; 64SMALL-ASM:      add 3, 3, 4
 ; 64SMALL-ASM:      mtctr 3
 ; 64SMALL-ASM:      bctr
 ; 64SMALL-ASM: L..BB0_2:
 ; 64SMALL-ASM: L..BB0_3:
 ; 64SMALL-ASM: L..BB0_4:
 ; 64SMALL-ASM: L..BB0_5:
 ; 64SMALL-ASM: L..BB0_6:
 ; 64SMALL-ASM:      li 3, 0
 ; 64SMALL-ASM:      blr
 ; 64SMALL-ASM:      .csect .rodata[RO],2
 ; 64SMALL-ASM:      .align  2
-; 64SMALL-ASM: .LJTI0_0:
-; 64SMALL-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
-; 64SMALL-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
-; 64SMALL-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
-; 64SMALL-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
+; 64SMALL-ASM: L..JTI0_0:
+; 64SMALL-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
+; 64SMALL-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
+; 64SMALL-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
+; 64SMALL-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
 
 ; 64LARGE-ASM-LABEL: jump_table
 ; 64LARGE-ASM: .jump_table:
 ; 64LARGE-ASM:      addi 3, 3, -1
 ; 64LARGE-ASM:      cmplwi  3, 3
 ; 64LARGE-ASM:      bgt     0, L..BB0_6
 ; 64LARGE-ASM:      addis 4, L..C0@u(2)
 ; 64LARGE-ASM:      rldic 3, 3, 2, 30
 ; 64LARGE-ASM:      ld 4, L..C0@l(4)
 ; 64LARGE-ASM:      lwax 3, 3, 4
 ; 64LARGE-ASM:      add 3, 3, 4
 ; 64LARGE-ASM:      mtctr 3
 ; 64LARGE-ASM:      bctr
 ; 64LARGE-ASM: L..BB0_2:
 ; 64LARGE-ASM: L..BB0_3:
 ; 64LARGE-ASM: L..BB0_4:
 ; 64LARGE-ASM: L..BB0_5:
 ; 64LARGE-ASM: L..BB0_6:
 ; 64LARGE-ASM:      li 3, 0
 ; 64LARGE-ASM:      blr
 ; 64LARGE-ASM:      .csect .rodata[RO],2
 ; 64LARGE-ASM:      .align  2
-; 64LARGE-ASM: .LJTI0_0:
-; 64LARGE-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
-; 64LARGE-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
-; 64LARGE-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
-; 64LARGE-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
+; 64LARGE-ASM: L..JTI0_0:
+; 64LARGE-ASM:      .vbyte  4, L..BB0_2-L..JTI0_0
+; 64LARGE-ASM:      .vbyte  4, L..BB0_3-L..JTI0_0
+; 64LARGE-ASM:      .vbyte  4, L..BB0_4-L..JTI0_0
+; 64LARGE-ASM:      .vbyte  4, L..BB0_5-L..JTI0_0
 
 ; CHECK: .toc
-; CHECK: .tc .LJTI0_0[TC],.LJTI0_0
+; CHECK: .tc L..JTI0_0[TC],L..JTI0_0

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

 define i32 @main() #0 {
 entry:
   ret i32 0
 }
 
 ;CHECK:         .csect .rodata[RO],4
 
 ;CHECK-NEXT:         .align  4
-;CHECK-NEXT: .L__const.main.cnst32:
+;CHECK-NEXT: L..__const.main.cnst32:
 ;CHECK32-NEXT:         .vbyte 4, 1073741824
 ;CHECK32-NEXT:         .vbyte 4, 50
 ;CHECK64-NEXT:         .vbyte 8, 4611686018427387954
 ;CHECK-NEXT:           .vbyte 4, 0                       # 0x0
 ;CHECK-NEXT:           .space  4
 ;CHECK32-NEXT:         .vbyte 4, 0
 ;CHECK32-NEXT:         .vbyte 4, 0
 ;CHECK64-NEXT:         .vbyte 8, 0
 ;CHECK-NEXT:           .vbyte 4, 0                       # 0x0
 ;CHECK-NEXT:           .space  4
 
 ;CHECK-NEXT:           .align  3
-;CHECK-NEXT: .L__const.main.cnst16:
+;CHECK-NEXT: L..__const.main.cnst16:
 ;CHECK32-NEXT:         .vbyte 4, 1073741824
 ;CHECK32-NEXT:         .vbyte 4, 22
 ;CHECK64-NEXT:         .vbyte 8, 4611686018427387926
 ;CHECK-NEXT:           .vbyte 4, 0                       # 0x0
 ;CHECK-NEXT:           .space  4
 
 ;CHECK-NEXT:         .align  3
-;CHECK-NEXT: .L__const.main.cnst8:
+;CHECK-NEXT: L..__const.main.cnst8:
 ;CHECK-NEXT:         .vbyte 4, 1073741832              # 0x40000008
 ;CHECK-NEXT:         .vbyte 4, 0                       # 0x0
 
 ;CHECK-NEXT:         .align  3
-;CHECK-NEXT: .L__const.main.cnst4:
+;CHECK-NEXT: L..__const.main.cnst4:
 ;CHECK-NEXT:         .vbyte 2, 16392                   # 0x4008
 ;CHECK-NEXT:         .byte   0                       # 0x0
 ;CHECK-NEXT:         .space  1
 
 
 ;CHECKOBJ:      00000000 <.text>:
 ;CHECKOBJ-NEXT:        0: 38 60 00 00                    li 3, 0
 ;CHECKOBJ-NEXT:        4: 4e 80 00 20                    blr

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

 entry:
   %0 = load i8*, i8** @p, align 4
   %1 = load i8, i8* %0, align 1
   ret i8 %1
 }
 
 ; CHECK:   .csect .rodata.str2.2[RO],2
 ; CHECK-NEXT:   .align  1
-; CHECK-NEXT: .Lmagic16:
+; CHECK-NEXT: L..magic16:
 ; CHECK-NEXT:   .vbyte  2, 264                     # 0x108
 ; CHECK-NEXT:   .vbyte  2, 272                     # 0x110
 ; CHECK-NEXT:   .vbyte  2, 213                     # 0xd5
 ; CHECK-NEXT:   .vbyte  2, 0                       # 0x0
 ; CHECK-NEXT:   .csect .rodata.str4.4[RO],2
 ; CHECK-NEXT:   .align  2
-; CHECK-NEXT: .Lmagic32:
+; CHECK-NEXT: L..magic32:
 ; CHECK-NEXT:   .vbyte  4, 464                     # 0x1d0
 ; CHECK-NEXT:   .vbyte  4, 472                     # 0x1d8
 ; CHECK-NEXT:   .vbyte  4, 413                     # 0x19d
 ; CHECK-NEXT:   .vbyte  4, 0                       # 0x0
 ; CHECK-NEXT:   .csect .rodata.str1.1[RO],2
-; CHECK-NEXT: .LstrA:
+; CHECK-NEXT: L..strA:
 ; CHECK-NEXT: .byte   104
 ; CHECK-NEXT: .byte   101
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   111
 ; CHECK-NEXT: .byte   32
 ; CHECK-NEXT: .byte   119
 ; CHECK-NEXT: .byte   111
 ; CHECK-NEXT: .byte   114
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   100
 ; CHECK-NEXT: .byte   33
 ; CHECK-NEXT: .byte   10
 ; CHECK-NEXT: .byte   0
-; CHECK-NEXT: .L.str:
+; CHECK-NEXT: L...str:
 ; CHECK-NEXT: .byte   97
 ; CHECK-NEXT: .byte   98
 ; CHECK-NEXT: .byte   99
 ; CHECK-NEXT: .byte   100
 ; CHECK-NEXT: .byte   101
 ; CHECK-NEXT: .byte   102
 ; CHECK-NEXT: .byte   103
 ; CHECK-NEXT: .byte   104