[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm

[lei]

Summary

This patch simply adds support for the new CPU in anticipation of
Power10. There isn't really any functionality added so there are no
associated test cases at this time.

[lei]

Add support in llvm.

[lei]

missed a file

[amyk]

I believe we're also missing IsISA3_1 = false; in PPCSubtarget.cpp.

llvm/lib/Target/PowerPC/PPC.td

338 ↗

(On Diff #264303)

Are we missing FeatureISA3_1 in P10AdditionalFeatures?

[steven.zhang]

clang/lib/Basic/Targets/PPC.cpp

272

Do we miss to define this macro ?

__POWER10_VECTOR__

llvm/lib/Target/PowerPC/PPC.td

211 ↗

(On Diff #264303)

Nit: no ending dot.

[steven.zhang]

clang/lib/Basic/Targets/PPC.cpp

272

Well, pls ignore this comments as that macro should be added when p10 vector feature is added.

[stefanp]

Most of my comments are related to the fact that we are now inserting P10 between P9 and Future and so a few things need to change for the Future code to sit on top of P10 now.

clang/test/Preprocessor/init-ppc64.c

652 ↗

(On Diff #264303)

Since we are adding P10 between P9 and Future we should add another line here:

PPCFUTURE:#define _ARCH_PWR10 1

llvm/lib/Target/PowerPC/PPC.td

340 ↗

(On Diff #264303)

I think these can be moved up to P10AdditionalFeatures. That way everything on P10 is now inheritable by future and we don't have to specify anything for FutureSpecificFeatures.

351 ↗

(On Diff #264303)

These features are now no longer FutureSpecificFeatures I would think that they would now be part of Power10 and should be inherited by future CPU.

llvm/test/CodeGen/PowerPC/check-cpu.ll

11 ↗

(On Diff #264303)

nit:
We should probably update this comment too.

[NeHuang]

clang/lib/Basic/Targets/PPC.cpp

345

I think we also need to check for ArchDefinePwr10 and ArchDefineFuture based on the comment "// We have __float128 on PPC but not power 9 and above."

!(ArchDefs & ArchDefinePwr9) -> !(ArchDefs & (ArchDefinePwr9 | ArchDefinePwr10 | ArchDefineFuture))

[lei]

address review comments

clang/lib/Basic/Targets/PPC.cpp

345

I would think this would be redundant since -mcpu=pwr10 also defines ArchDefinePwr9 ...

llvm/lib/Target/PowerPC/PPC.td

211 ↗

(On Diff #264303)

That's needed to indicate the end of the sentence. Similar to line 208.

[NeHuang]

clang/lib/Basic/Targets/PPC.cpp

345

Yeah. That makes sense. Thanks for the explanation!

[amyk]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

653 ↗

(On Diff #266073)

Should this comment be updated to include P10 as well?

[nemanjai]

LGTM aside from a couple of minor nits.

clang/lib/Basic/Targets/PPC.cpp

319

Please remove this since HTM was removed in P10.

clang/test/Preprocessor/init-ppc64.c

644 ↗

(On Diff #266073)

I am not sure what the story is with not checking for _ARCH_PWR8 for the P9 test, but I don't think we need to continue that precedent.

[stefanp]

LGTM

[amyk]

I think this looks good aside from the comments I had.

llvm/lib/Target/PowerPC/PPCSubtarget.h

142 ↗

(On Diff #266073)

Missing IsISA3_1 = false; in PPCSubtarget.cpp.

[lei]

update as per reviewers comments

[lei]

change how we generate p10 feature list.

[stefanp]

LGTM

[amyk]

This LGTM.

[lei]

rebased

[lei]

fix up rebase issue after revert

clang/lib/Basic/Targets/PPC.h

public:
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
 
   bool
   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
                  StringRef CPU,
                  const std::vector<std::string> &FeaturesVec) const override;
 
+  void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
   void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 
   bool hasFeature(StringRef Feature) const override;
 
   void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,

clang/lib/Basic/Targets/PPC.cpp

Features["altivec"] = llvm::StringSwitch<bool>(CPU)
                             .Case("pwr6", true)
                             .Case("pwr7", true)
                             .Case("pwr8", true)
                             .Case("pwr9", true)
                             .Case("pwr10", true)
                             .Case("ppc64", true)
                             .Case("ppc64le", true)
                             .Default(false);
 
   Features["qpx"] = (CPU == "a2q");
   Features["power9-vector"] = llvm::StringSwitch<bool>(CPU)
                                   .Case("pwr10", true)
                                   .Case("pwr9", true)
                                   .Default(false);
   Features["crypto"] = llvm::StringSwitch<bool>(CPU)
                            .Case("ppc64le", true)
                            .Case("pwr10", true)
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
                         .Case("ppc64le", true)
                         .Case("pwr10", true)
                         .Case("pwr9", true)
                         .Case("pwr8", true)
                         .Case("pwr7", true)
                         .Default(false);
   Features["htm"] = llvm::StringSwitch<bool>(CPU)
                         .Case("ppc64le", true)
                         .Case("pwr9", true)
                         .Case("pwr8", true)
                         .Default(false);
 
   Features["spe"] = llvm::StringSwitch<bool>(CPU)
                         .Case("8548", true)
                         .Case("e500", true)
                         .Default(false);
 
+  // Power10 includes all the same features as Power9 plus any features specific
+  // to the Power10 core.
+  if (CPU == "pwr10" || CPU == "power10") {
+    initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+    addP10SpecificFeatures(Features);
+  }
+
   // Future CPU should include all of the features of Power 10 as well as any
   // additional features (yet to be determined) specific to it.
   if (CPU == "future") {
     initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
     addFutureSpecificFeatures(Features);
   }
 
   if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
     return false;
 
   if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
       llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
     // We have __float128 on PPC but not power 9 and above.
     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
     return false;
   }
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
 }
 
+// Add any Power10 specific features.
+void PPCTargetInfo::addP10SpecificFeatures(
+    llvm::StringMap<bool> &Features) const {
+  Features["htm"] = false; // HTM was removed for P10.
+  return;
+}
+
 // Add features specific to the "Future" CPU.
 void PPCTargetInfo::addFutureSpecificFeatures(
     llvm::StringMap<bool> &Features) const {
   return;
 }
 
 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)