[CSInfo][MIPS] Describe parameter value loaded by ADDiu instruction

[ntesic]

Summary

Describe parameter's value loaded by MIPS ADDiu instruction.
When parameter's value is loaded into a register by mips ADDiu/DADDiu instruction,
it could be described correctly and emitted as DW_AT_GNU_call_site_value.

Test:
-dbg-call-site-param-addiu.mir, dbg-call-site-param-addiu-64bit.mir - confirm correct DW_AT_GNU_call_site_value of call site parameter DIE for parameter which value is loaded by ADDiu/DADDiu instruction.

[dstenb]

llvm/lib/Target/Mips/MipsInstrInfo.cpp

849

Nit: >80 cols

There are also some other minor indentation things here, so it might be good to run this patch through git-clang-format.

874

The AArch64 implementation (and the other target implementations) now check if the first operand really is a register: https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp#L6610.

For AArch64, that seems to have been done due to encountering INLINEASM that defined the parameter register.

Should the same check be added here?

llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir

16

Personal opinion, but I prefer having the RUN lines at the top of the file, as I think that makes it easier to get an overview of what is tested, without having to scan the file.

[ntesic]

llvm/lib/Target/Mips/MipsInstrInfo.cpp

874

I agree, we should consider that case for Mips also. Thanks.

llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir

16

Definitely, I can use that principle. Thanks.

[ntesic]

Address comments.

[vsk]

This looks reasonable to me, but I'll defer to someone with more Mips background to give an official lgtm.

[atanasyan]

Looks good overall, just a few nits inline.

llvm/lib/Target/Mips/MipsInstrInfo.cpp

850

You can join declaration and initialization.

869

You can join declaration and initialization.

883

The second "value" in this comment is redundant.

885

I prefer to reverse this condition something like this. I think, in this case it's more clear what we need from the operands.

if (Dop.isReg() && (Sop1.isReg() || Sop1.isFI()) && Sop2.isImm())
  return RegImmPair{Sop1.getReg(), Sop2.getImm()};

return None;

[dstenb]

llvm/lib/Target/Mips/MipsInstrInfo.cpp

885

Oh, and the getReg() invocation will trigger an assert/produce incorrect data in the Sop1.isFI() case! What is the expected behavior if the operand is a frame-index?

[djtodoro]

llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir

100

The same tip for trimming out the test: Use only one DILocation per scope.

[ntesic]

llvm/lib/Target/Mips/MipsInstrInfo.cpp

885

@atanasyan Thanks for suggestions.
@dstenb This was leftover from an old implementation. Case of ADDiu with frame index operand, should be considered separately. We can omit it for now and mark it with TODO.

[ntesic]

Address comments.
Rebase.

[djtodoro]

Thanks, lgtm. Please wait for others (for another day at least) to give their final comments.

In addition, I feel like mentioning the utility that could be useful for finding (target dependent) candidates for the DW_AT_call_value description: https://github.com/djolertrk/call-site-params-stats.
This could be useful when someone starts extending the support to other architectures as well.

llvm/lib/Target/Mips/MipsInstrInfo.h

bool verifyInstruction(const MachineInstr &MI,
                          StringRef &ErrInfo) const override;
 
   std::pair<unsigned, unsigned>
   decomposeMachineOperandsTargetFlags(unsigned TF) const override;
 
   ArrayRef<std::pair<unsigned, const char *>>
   getSerializableDirectMachineOperandTargetFlags() const override;
 
+  Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
+                                      Register Reg) const override;
+
+  Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
+                                                 Register Reg) const override;
+
 protected:
   bool isZeroImm(const MachineOperand &op) const;
 
   MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
                                    MachineMemOperand::Flags Flags) const;
 
 private:
   virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;

llvm/lib/Target/Mips/MipsInstrInfo.cpp

 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Target/TargetMachine.h"
 #include <cassert>
 
 using namespace llvm;
 
 #define GET_INSTRINFO_CTOR_DTOR
static const std::pair<unsigned, const char*> Flags[] = {
     {MO_GOT_HI16,     "mips-got-hi16"},
     {MO_GOT_LO16,     "mips-got-lo16"},
     {MO_CALL_HI16,    "mips-call-hi16"},
     {MO_CALL_LO16,    "mips-call-lo16"},
     {MO_JALR,         "mips-jalr"}
   };
   return makeArrayRef(Flags);
 }
+
+Optional<ParamLoadedValue>
+MipsInstrInfo::describeLoadedValue(const MachineInstr &MI,
+                                     Register Reg) const {
+  DIExpression *Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
+  int64_t Offset;
+  // TODO: Special MIPS instructions that need to be described separately.
+  if (auto RegImm = isAddImmediate(MI, Reg)) {
+    Register SrcReg = RegImm->Reg;
+    Offset = RegImm->Imm;
+    // When SrcReg is $zero, treat loaded value as immediate only.
+    // Ex. $a2 = ADDiu $zero, 10
+    if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64){
+      return ParamLoadedValue(MI.getOperand(2), Expr);
+    }
+    Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
+    return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
+  }
+
+ return TargetInstrInfo::describeLoadedValue(MI, Reg);
+}
+
+Optional<RegImmPair>
+MipsInstrInfo::isAddImmediate(const MachineInstr &MI,
+                                Register Reg) const {
+  int64_t Offset = 0;
+
+  // TODO: Handle cases where Reg is a super- or sub-register of the
+  // destination register.
+  if (Reg != MI.getOperand(0).getReg())
+    return None;
+
+  switch (MI.getOpcode()){
+    case Mips::ADDiu:
+    case Mips::DADDiu: {
+    const MachineOperand &Dop = MI.getOperand(0);
+    const MachineOperand &Sop1 = MI.getOperand(1);
+    const MachineOperand &Sop2 = MI.getOperand(2);
+    // Value is sum of register and immediate. Immediate value value could be
+    // global string address which is not supported.
+    if (!Dop.isReg() || (!Sop1.isReg() && !Sop1.isFI()) || !Sop2.isImm())
+      return None;
+
+    Offset = Sop2.getImm();
+    return RegImmPair{Sop1.getReg(), Offset};
+    }
+  }
+  return None;
+}

llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir

+## Following code is used for producing this test case.
+##
+## extern int fn1(long,long,long);
+## extern void clobber();
+## int fn2(long a) {
+##   clobber();
+##   int local = fn1(44, a, a+10);
+##   if (local > 10)
+##     return local + 10;
+##   return local;
+## }
+## Check that parameters value loaded by instruction ADDiu/DADDiu is
+## interpreted correctly.
+
+## Test mips64:
+# RUN: llc -mtriple mips64-linux-gnu -emit-call-site-info -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT: DW_AT_abstract_origin {{.*}} "fn1"
+# CHECK: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg5 A1_64)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg4 A0_64)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_constu 0x2c)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg6 A2_64)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+10)
+
+## Test mips64el:
+# RUN: llc -mtriple mips64el-linux-gnu -emit-call-site-info -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s --check-prefix=CHECK64el
+# CHECK64el: DW_TAG_GNU_call_site
+# CHECK64el-NEXT: DW_AT_abstract_origin {{.*}} "fn1"
+# CHECK64el: DW_TAG_GNU_call_site_parameter
+# CHECK64el-NEXT:   DW_AT_location      (DW_OP_reg5 A1_64)
+# CHECK64el-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+0)
+# CHECK64el-EMPTY: 
+# CHECK64el-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64el-NEXT:   DW_AT_location      (DW_OP_reg4 A0_64)
+# CHECK64el-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_constu 0x2c)
+# CHECK64el-EMPTY: 
+# CHECK64el-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK64el-NEXT:   DW_AT_location      (DW_OP_reg6 A2_64)
+# CHECK64el-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+10)
+
+--- |
+  ; ModuleID = 'mips64.ll'
+  source_filename = "m64.c"
+  target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+  target triple = "mips64-unknown-linux-gnu"
+  
+  ; Function Attrs: nounwind
+  define signext i32 @fn2(i64 signext %a) local_unnamed_addr !dbg !14 {
+  entry:
+    call void @llvm.dbg.value(metadata i64 %a, metadata !18, metadata !DIExpression()), !dbg !20
+    tail call void bitcast (void (...)* @clobber to void ()*)(), !dbg !21
+    %add = add nsw i64 %a, 10, !dbg !22
+    %call = tail call signext i32 @fn1(i64 signext 44, i64 signext %a, i64 signext %add), !dbg !23
+    call void @llvm.dbg.value(metadata i32 %call, metadata !19, metadata !DIExpression()), !dbg !20
+    %cmp = icmp sgt i32 %call, 10, !dbg !24
+    %add1 = add nsw i32 %call, 10, !dbg !26
+    %retval.0 = select i1 %cmp, i32 %add1, i32 %call, !dbg !26
+    ret i32 %retval.0, !dbg !27
+  }
+  
+  declare void @clobber(...) local_unnamed_addr
+  
+  declare !dbg !4 signext i32 @fn1(i64 signext, i64 signext, i64 signext) local_unnamed_addr
+  
+  ; Function Attrs: nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!9, !10, !11, !12}
+  !llvm.ident = !{!13}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, splitDebugInlining: false, nameTableKind: None)
+  !1 = !DIFile(filename: "m.c", directory: "/dir")
+  !2 = !{}
+  !3 = !{!4}
+  !4 = !DISubprogram(name: "fn1", scope: !1, file: !1, line: 1, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
+  !5 = !DISubroutineType(types: !6)
+  !6 = !{!7, !8, !8, !8}
+  !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !8 = !DIBasicType(name: "long int", size: 64, encoding: DW_ATE_signed)
+  !9 = !{i32 7, !"Dwarf Version", i32 4}
+  !10 = !{i32 2, !"Debug Info Version", i32 3}
+  !11 = !{i32 1, !"wchar_size", i32 4}
+  !12 = !{i32 7, !"PIC Level", i32 1}
+  !13 = !{!"clang version 11.0.0"}
+  !14 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 3, type: !15, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !17)
+  !15 = !DISubroutineType(types: !16)
+  !16 = !{!7, !8}
+  !17 = !{!18, !19}
+  !18 = !DILocalVariable(name: "a", arg: 1, scope: !14, file: !1, line: 3, type: !8)
+  !19 = !DILocalVariable(name: "local", scope: !14, file: !1, line: 5, type: !7)
+  !20 = !DILocation(line: 0, scope: !14)
+  !21 = !DILocation(line: 4, column: 4, scope: !14)
+  !22 = !DILocation(line: 5, column: 28, scope: !14)
+  !23 = !DILocation(line: 5, column: 16, scope: !14)
+  !24 = !DILocation(line: 6, column: 14, scope: !25)
+  !25 = distinct !DILexicalBlock(scope: !14, file: !1, line: 6, column: 8)
+  !26 = !DILocation(line: 6, column: 8, scope: !14)
+  !27 = !DILocation(line: 9, column: 2, scope: !14)
+
+...
+---
+name:            fn2
+alignment:       8
+liveins:
+  - { reg: '$a0_64', virtual-reg: '' }
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8, 
+      stack-id: default, callee-saved-register: '$ra_64', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, 
+      stack-id: default, callee-saved-register: '$s0_64', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:
+  - { bb: 0, offset: 8, fwdArgRegs: [] }
+  - { bb: 0, offset: 12, fwdArgRegs: 
+      - { arg: 0, reg: '$a0_64' }
+      - { arg: 1, reg: '$a1_64' }
+      - { arg: 2, reg: '$a2_64' } }
+body:             |
+  bb.0.entry:
+    DBG_VALUE $a0_64, $noreg, !18, !DIExpression(), debug-location !20
+    $sp_64 = DADDiu $sp_64, -16
+    CFI_INSTRUCTION def_cfa_offset 16
+    SD killed $ra_64, $sp_64, 8 :: (store 8 into %stack.0)
+    SD killed $s0_64, $sp_64, 0 :: (store 8 into %stack.1)
+    CFI_INSTRUCTION offset $ra_64, -8
+    CFI_INSTRUCTION offset $s0_64, -16
+    DBG_VALUE $s0_64, $noreg, !18, !DIExpression(), debug-location !20
+    JAL @clobber, csr_n64, implicit-def dead $ra, implicit-def $sp, debug-location !21 {
+      $s0_64 = OR64 $a0_64, $zero_64
+    }
+    renamable $a2_64 = nsw DADDiu renamable $s0_64, 10, debug-location !22
+    $a0_64 = DADDiu $zero_64, 44, debug-location !23
+    JAL @fn1, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit killed $a1_64, implicit $a2_64, implicit-def $sp, implicit-def $v0, debug-location !23 {
+      $a1_64 = OR64 killed $s0_64, $zero_64, debug-location !23
+    }
+    DBG_VALUE $v0, $noreg, !19, !DIExpression(), debug-location !20
+    renamable $at = SLTi renamable $v0, 11, debug-location !26
+    renamable $v1 = nsw ADDiu renamable $v0, 10, debug-location !26
+    renamable $v0 = MOVZ_I_I killed renamable $v1, killed renamable $at, killed renamable $v0, debug-location !26
+    renamable $v0_64 = SLL64_32 killed renamable $v0, debug-location !27
+    $s0_64 = LD $sp_64, 0, debug-location !27 :: (load 8 from %stack.1)
+    $ra_64 = LD $sp_64, 8, debug-location !27 :: (load 8 from %stack.0)
+    PseudoReturn64 undef $ra_64, implicit $v0_64, debug-location !27 {
+      $sp_64 = DADDiu $sp_64, 16
+    }

llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir

+## Following code is used for producing this test case.
+##
+## extern int fn1(int,int,int);
+## extern void clobber();
+## int fn2(int a) {
+##   clobber();
+##   int local = fn1(44, a, a+10);
+##   if (local > 10)
+##     return local + 10;
+##   return local;
+## }
+## Check that parameters value loaded by instruction ADDiu/DADDiu is
+## interpreted correctly.
+
+## Test mips32:
+# RUN: llc -mtriple mips-linux-gnu -emit-call-site-info -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s
+# CHECK: DW_TAG_GNU_call_site
+# CHECK-NEXT: DW_AT_abstract_origin {{.*}} "fn1"
+# CHECK: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg5 A1_64)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+0)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg4 A0_64)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_constu 0x2c)
+# CHECK-EMPTY: 
+# CHECK-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECK-NEXT:   DW_AT_location      (DW_OP_reg6 A2_64)
+# CHECK-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+10)
+
+## Test mipsel:
+# RUN: llc -mtriple mipsel-linux-gnu -emit-call-site-info -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s --check-prefix=CHECKel
+# CHECKel: DW_TAG_GNU_call_site
+# CHECKel-NEXT: DW_AT_abstract_origin {{.*}} "fn1"
+# CHECKel: DW_TAG_GNU_call_site_parameter
+# CHECKel-NEXT:   DW_AT_location      (DW_OP_reg5 A1_64)
+# CHECKel-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+0)
+# CHECKel-EMPTY: 
+# CHECKel-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECKel-NEXT:   DW_AT_location      (DW_OP_reg4 A0_64)
+# CHECKel-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_constu 0x2c)
+# CHECKel-EMPTY: 
+# CHECKel-NEXT: DW_TAG_GNU_call_site_parameter
+# CHECKel-NEXT:   DW_AT_location      (DW_OP_reg6 A2_64)
+# CHECKel-NEXT:   DW_AT_GNU_call_site_value   (DW_OP_breg16 S0_64+10)
+--- |
+  ; ModuleID = 'm.ll'
+  source_filename = "m.c"
+  target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
+  target triple = "mips-unknown-linux-gnu"
+
+  ; Function Attrs: nounwind
+  define dso_local i32 @fn2(i32 signext %a) local_unnamed_addr !dbg !12 {
+  entry:
+    call void @llvm.dbg.value(metadata i32 %a, metadata !16, metadata !DIExpression()), !dbg !18
+    tail call void bitcast (void (...)* @clobber to void ()*)(), !dbg !19
+    %add = add nsw i32 %a, 10, !dbg !20
+    %call = tail call i32 @fn1(i32 signext 44, i32 signext %a, i32 signext %add), !dbg !21
+    call void @llvm.dbg.value(metadata i32 %call, metadata !17, metadata !DIExpression()), !dbg !18
+    %cmp = icmp sgt i32 %call, 10, !dbg !22
+    %add1 = add nsw i32 %call, 10, !dbg !24
+    %retval.0 = select i1 %cmp, i32 %add1, i32 %call, !dbg !24
+    ret i32 %retval.0, !dbg !25
+  }
+  
+  declare dso_local void @clobber(...) local_unnamed_addr
+  
+  declare !dbg !4 dso_local i32 @fn1(i32 signext, i32 signext, i32 signext) local_unnamed_addr
+  
+  ; Function Attrs: nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!8, !9, !10}
+  !llvm.ident = !{!11}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, splitDebugInlining: false, nameTableKind: None)
+  !1 = !DIFile(filename: "m.c", directory: "/dir")
+  !2 = !{}
+  !3 = !{!4}
+  !4 = !DISubprogram(name: "fn1", scope: !1, file: !1, line: 1, type: !5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2)
+  !5 = !DISubroutineType(types: !6)
+  !6 = !{!7, !7, !7, !7}
+  !7 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !8 = !{i32 7, !"Dwarf Version", i32 4}
+  !9 = !{i32 2, !"Debug Info Version", i32 3}
+  !10 = !{i32 1, !"wchar_size", i32 4}
+  !11 = !{!"clang version 11.0.0"}
+  !12 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 3, type: !13, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !15)
+  !13 = !DISubroutineType(types: !14)
+  !14 = !{!7, !7}
+  !15 = !{!16, !17}
+  !16 = !DILocalVariable(name: "a", arg: 1, scope: !12, file: !1, line: 3, type: !7)
+  !17 = !DILocalVariable(name: "local", scope: !12, file: !1, line: 5, type: !7)
+  !18 = !DILocation(line: 0, scope: !12)
+  !19 = !DILocation(line: 4, column: 4, scope: !12)
+  !20 = !DILocation(line: 5, column: 28, scope: !12)
+  !21 = !DILocation(line: 5, column: 16, scope: !12)
+  !22 = !DILocation(line: 6, column: 14, scope: !23)
+  !23 = distinct !DILexicalBlock(scope: !12, file: !1, line: 6, column: 8)
+  !24 = !DILocation(line: 6, column: 8, scope: !12)
+  !25 = !DILocation(line: 9, column: 2, scope: !12)
+
+...
+---
+name:            fn2
+alignment:       4
+liveins:
+  - { reg: '$a0', virtual-reg: '' }
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$ra', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$s0', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:
+  - { bb: 0, offset: 8, fwdArgRegs: [] }
+  - { bb: 0, offset: 12, fwdArgRegs: 
+      - { arg: 0, reg: '$a0' }
+      - { arg: 1, reg: '$a1' }
+      - { arg: 2, reg: '$a2' } }
+body:             |
+  bb.0.entry:
+    DBG_VALUE $a0, $noreg, !16, !DIExpression(), debug-location !18
+    $sp = ADDiu $sp, -24
+    CFI_INSTRUCTION def_cfa_offset 24
+    SW killed $ra, $sp, 20 :: (store 4 into %stack.0)
+    SW killed $s0, $sp, 16 :: (store 4 into %stack.1)
+    CFI_INSTRUCTION offset $ra_64, -4
+    CFI_INSTRUCTION offset $s0_64, -8
+    DBG_VALUE $s0, $noreg, !16, !DIExpression(), debug-location !18
+    JAL @clobber, csr_o32, implicit-def dead $ra, implicit-def $sp, debug-location !19 {
+      $s0 = OR $a0, $zero
+    }
+    renamable $a2 = nsw ADDiu renamable $s0, 10, debug-location !20
+    $a0 = ADDiu $zero, 44, debug-location !21
+    JAL @fn1, csr_o32, implicit-def dead $ra, implicit $a0, implicit killed $a1, implicit $a2, implicit-def $sp, implicit-def $v0, debug-location !21 {
+      $a1 = OR killed $s0, $zero, debug-location !21
+    }
+    DBG_VALUE $v0, $noreg, !17, !DIExpression(), debug-location !18
+    renamable $at = SLTi renamable $v0, 11, debug-location !24
+    renamable $v1 = nsw ADDiu renamable $v0, 10, debug-location !24
+    renamable $v0 = MOVZ_I_I killed renamable $v1, killed renamable $at, killed renamable $v0, debug-location !24
+    $s0 = LW $sp, 16, debug-location !25 :: (load 4 from %stack.1)
+    $ra = LW $sp, 20, debug-location !25 :: (load 4 from %stack.0)
+    PseudoReturn undef $ra, implicit $v0, debug-location !25 {
+      $sp = ADDiu $sp, 24
+    }