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Differential D77931

[GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES
ClosedPublic

Authored by aemerson on Apr 10 2020, 10:52 PM.

Details

Reviewers
arsenm
paquette
dsanders
gargaroff
qcolombet
Commits
rGc22cb5bd31ca: [GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES.
Summary

We generally only combine starting from users to defs in the artifact combiner, but this doesn't catch cases where at the point of combining a G_UNMERGE we don't yet have the opposite G_MERGE on input yet since we haven't legalized that far.

This change adds the users of a G_MERGE to the artifact combiner worklist if one of the uses is a G_UNMERGE.

Diff Detail

Unit TestsFailed

TimeTest
130 msLLVM.CodeGen/AMDGPU/GlobalISel::Unknown Unit Message ("")
170 msLLVM.CodeGen/AMDGPU/GlobalISel::Unknown Unit Message ("")
200 msLLVM.CodeGen/AMDGPU/GlobalISel::Unknown Unit Message ("")

Event Timeline

aemerson created this revision.Apr 10 2020, 10:52 PM
Herald added subscribers: atanasyan, jrtc27, rovka and 2 others. · View Herald TranscriptApr 10 2020, 10:52 PM
Harbormaster completed remote builds in B52785: Diff 256744.Apr 10 2020, 11:25 PM
gargaroff added inline comments.Apr 14 2020, 2:55 AM
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
655

Should this skip COPYs?

656

The artifact combiner can also combine trunc(merge). Could you add trunc users to the worklist as well?

aemerson updated this revision to Diff 257547.Apr 14 2020, 3:58 PM

Add TRUNC users to the list.

Herald added subscribers: kerbowa, nhaehnle, jvesely. · View Herald TranscriptApr 14 2020, 3:58 PM
aemerson marked an inline comment as done.Apr 14 2020, 4:00 PM
aemerson added inline comments.
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
655

I don't think it's quite that simple. Here we may have multiple users, and if we skip through COPYs then we have to potentially search through a tree rather than just walking up a single chain. This could have a compile time impact.

Harbormaster failed remote builds in B53260: Diff 257547!Apr 14 2020, 5:25 PM
gargaroff accepted this revision.Apr 15 2020, 3:44 AM

LGTM with the failing tests fixed.

This revision is now accepted and ready to land.Apr 15 2020, 3:44 AM
Closed by commit rGc22cb5bd31ca: [GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES. (authored by aemerson). · Explain WhyApr 15 2020, 10:57 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
11 lines
test/
CodeGen/
AArch64/
GlobalISel/
8 lines
29 lines
AMDGPU/
GlobalISel/
30 lines
Mips/
GlobalISel/
legalizer/
6 lines
6 lines
22 lines
12 lines
12 lines

Diff 257547

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Show First 20 Lines • Show All 643 Lines • ▼ Show 20 Lines case TargetOpcode::G_ZEXT:
Changed = tryCombineZExt(MI, DeadInsts, UpdatedDefs, WrapperObserver); Changed = tryCombineZExt(MI, DeadInsts, UpdatedDefs, WrapperObserver);
break; break;
case TargetOpcode::G_SEXT: case TargetOpcode::G_SEXT:
Changed = tryCombineSExt(MI, DeadInsts, UpdatedDefs); Changed = tryCombineSExt(MI, DeadInsts, UpdatedDefs);
break; break;
case TargetOpcode::G_UNMERGE_VALUES: case TargetOpcode::G_UNMERGE_VALUES:
Changed = tryCombineMerges(MI, DeadInsts, UpdatedDefs, WrapperObserver); Changed = tryCombineMerges(MI, DeadInsts, UpdatedDefs, WrapperObserver);
break; break;
case TargetOpcode::G_MERGE_VALUES:
// If any of the users of this merge are an unmerge, then add them to the
// artifact worklist in case there's folding that can be done looking up.
for (MachineInstr &U : MRI.use_instructions(MI.getOperand(0).getReg())) {
gargaroffUnsubmitted
Not Done
ReplyInline Actions

Should this skip COPYs?

gargaroff: Should this skip COPYs?
aemersonAuthorUnsubmitted
Done
ReplyInline Actions

I don't think it's quite that simple. Here we may have multiple users, and if we skip through COPYs then we have to potentially search through a tree rather than just walking up a single chain. This could have a compile time impact.

aemerson: I don't think it's quite that simple. Here we may have multiple users, and if we skip through…
if (U.getOpcode() == TargetOpcode::G_UNMERGE_VALUES ||
gargaroffUnsubmitted
Not Done
ReplyInline Actions

The artifact combiner can also combine trunc(merge). Could you add trunc users to the worklist as well?

gargaroff: The artifact combiner can also combine trunc(merge). Could you add trunc users to the worklist…
U.getOpcode() == TargetOpcode::G_TRUNC) {
UpdatedDefs.push_back(MI.getOperand(0).getReg());
break;
}
}
break;
case TargetOpcode::G_EXTRACT: case TargetOpcode::G_EXTRACT:
Changed = tryCombineExtract(MI, DeadInsts, UpdatedDefs); Changed = tryCombineExtract(MI, DeadInsts, UpdatedDefs);
break; break;
case TargetOpcode::G_TRUNC: case TargetOpcode::G_TRUNC:
Changed = tryCombineTrunc(MI, DeadInsts, UpdatedDefs, WrapperObserver); Changed = tryCombineTrunc(MI, DeadInsts, UpdatedDefs, WrapperObserver);
if (!Changed) { if (!Changed) {
// Try to combine truncates away even if they are legal. As all artifact // Try to combine truncates away even if they are legal. As all artifact
// combines at the moment look only "up" the def-use chains, we achieve // combines at the moment look only "up" the def-use chains, we achieve
▲ Show 20 Lines • Show All 159 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sext-zext-128.mir

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesbody: |
bb.1: bb.1:
liveins: $x0, $x1 liveins: $x0, $x1
; CHECK-LABEL: name: narrow_zext_s192 ; CHECK-LABEL: name: narrow_zext_s192
; CHECK: liveins: $x0, $x1 ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64) ; CHECK: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store 8)
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64), [[UV2:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[MV]](s192) ; CHECK: G_STORE [[C]](s64), [[COPY1]](p0) :: (store 8)
; CHECK: G_STORE [[UV]](s64), [[COPY1]](p0) :: (store 8) ; CHECK: G_STORE [[C]](s64), [[COPY1]](p0) :: (store 8)
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
%1:_(p0) = COPY $x1 %1:_(p0) = COPY $x1
%2:_(s192) = G_ZEXT %0(s64) %2:_(s192) = G_ZEXT %0(s64)
%3:_(s64), %4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %2(s192) %3:_(s64), %4:_(s64), %5:_(s64) = G_UNMERGE_VALUES %2(s192)
G_STORE %3, %1(p0) :: (store 8) G_STORE %3, %1(p0) :: (store 8)
G_STORE %4, %1(p0) :: (store 8)
G_STORE %5, %1(p0) :: (store 8)
RET_ReallyLR RET_ReallyLR
... ...

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines bb.0:
%1:_(<2 x s64>) = COPY $q1 %1:_(<2 x s64>) = COPY $q1
%2:_(<4 x s64>) = G_CONCAT_VECTORS %0(<2 x s64>), %1(<2 x s64>) %2:_(<4 x s64>) = G_CONCAT_VECTORS %0(<2 x s64>), %1(<2 x s64>)
%3:_(s64), %4:_(s64), %5:_(s64), %6:_(s64) = G_UNMERGE_VALUES %2(<4 x s64>) %3:_(s64), %4:_(s64), %5:_(s64), %6:_(s64) = G_UNMERGE_VALUES %2(<4 x s64>)
$x0 = COPY %3(s64) $x0 = COPY %3(s64)
$x1 = COPY %4(s64) $x1 = COPY %4(s64)
$x2 = COPY %5(s64) $x2 = COPY %5(s64)
$x3 = COPY %6(s64) $x3 = COPY %6(s64)
... ...
---
name: unmerge_merge_combine
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: unmerge_merge_combine
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[LOAD1:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load 16)
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD1]](s128)
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[LOAD]], [[UV]]
; CHECK: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[C]], [[UV]]
; CHECK: [[MUL2:%[0-9]+]]:_(s64) = G_MUL [[LOAD]], [[UV1]]
; CHECK: [[UMULH:%[0-9]+]]:_(s64) = G_UMULH [[LOAD]], [[UV]]
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MUL1]], [[MUL2]]
; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[UMULH]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MUL]](s64), [[ADD1]](s64)
; CHECK: $q0 = COPY [[MV]](s128)
; CHECK: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s128) = G_ZEXTLOAD %0:_(p0) :: (load 8)
%2:_(s128) = G_LOAD %0:_(p0) :: (load 16)
%3:_(s128) = G_MUL %1:_, %2:_
$q0 = COPY %3
RET_ReallyLR
...

llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines; GFX6-NEXT: s_setpc_b64 s[30:31]
%ext = zext i32 %load to i96 %ext = zext i32 %load to i96
ret i96 %ext ret i96 %ext
} }
define i128 @zextload_global_i32_to_i128(i32 addrspace(1)* %ptr) { define i128 @zextload_global_i32_to_i128(i32 addrspace(1)* %ptr) {
; GFX9-LABEL: zextload_global_i32_to_i128: ; GFX9-LABEL: zextload_global_i32_to_i128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v3, v1 ; GFX9-NEXT: global_load_dword v0, v[0:1], off
; GFX9-NEXT: v_mov_b32_e32 v2, v0 ; GFX9-NEXT: s_mov_b32 s4, 0
; GFX9-NEXT: global_load_dword v0, v[2:3], off ; GFX9-NEXT: s_mov_b32 s5, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s5
; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: zextload_global_i32_to_i128: ; GFX8-LABEL: zextload_global_i32_to_i128:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v3, v1 ; GFX8-NEXT: flat_load_dword v0, v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v2, v0 ; GFX8-NEXT: s_mov_b32 s4, 0
; GFX8-NEXT: flat_load_dword v0, v[2:3] ; GFX8-NEXT: s_mov_b32 s5, 0
; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, 0
; GFX8-NEXT: v_mov_b32_e32 v3, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: v_mov_b32_e32 v3, s4
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX6-LABEL: zextload_global_i32_to_i128: ; GFX6-LABEL: zextload_global_i32_to_i128:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v3, v1
; GFX6-NEXT: v_mov_b32_e32 v2, v0
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b64 s[4:5], 0 ; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_dword v0, v[2:3], s[4:7], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
; GFX6-NEXT: v_mov_b32_e32 v2, 0 ; GFX6-NEXT: s_mov_b32 s8, 0
; GFX6-NEXT: s_mov_b32 s4, 0
; GFX6-NEXT: v_mov_b32_e32 v1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: v_mov_b32_e32 v3, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: v_mov_b32_e32 v3, s8
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
%load = load i32, i32 addrspace(1)* %ptr %load = load i32, i32 addrspace(1)* %ptr
%ext = zext i32 %load to i128 %ext = zext i32 %load to i128
ret i128 %ext ret i128 %ext
} }

llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir

Show All 36 Lines bb.1.entry:
; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) ; MIPS32: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]] ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]]
; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32) ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]] ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[CTLZ1]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[CTLZ1]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[C]](s32) ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v1 = COPY [[C]](s32)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%1:_(s32) = COPY $a0 %1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1 %2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTLZ %0(s64) %3:_(s64) = G_CTLZ %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
$v0 = COPY %4(s32) $v0 = COPY %4(s32)
$v1 = COPY %5(s32) $v1 = COPY %5(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctpop.mir

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]]
; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32) ; MIPS32: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32)
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]] ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]]
; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]] ; MIPS32: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]]
; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C6]] ; MIPS32: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C6]]
; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32) ; MIPS32: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32)
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]]
; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD4]](s32), [[C8]](s32) ; MIPS32: $v0 = COPY [[ADD4]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v1 = COPY [[C8]](s32)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%1:_(s32) = COPY $a0 %1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1 %2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTPOP %0(s64) %3:_(s64) = G_CTPOP %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
$v0 = COPY %4(s32) $v0 = COPY %4(s32)
$v1 = COPY %5(s32) $v1 = COPY %5(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32) ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]] ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]]
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]] ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[C]](s32) ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v1 = COPY [[C]](s32)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%1:_(s32) = COPY $a0 %1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1 %2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%3:_(s64) = G_CTTZ %0(s64) %3:_(s64) = G_CTTZ %0(s64)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64) %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
$v0 = COPY %4(s32) $v0 = COPY %4(s32)
$v1 = COPY %5(s32) $v1 = COPY %5(s32)
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]] ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C2]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]] ; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]] ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32) ; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]] ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]]
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]] ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[SELECT]](s32), [[C1]](s32) ; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]]
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV1]](s64)
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[C]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]] ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[C1]] ; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[C1]], [[C1]]
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32) ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND3]] ; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND3]]
; MIPS32: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32) ; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32)
; MIPS32: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]] ; MIPS32: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
; MIPS32: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]] ; MIPS32: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]] ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]] ; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]]
; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32) ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV]], [[MV2]] ; MIPS32: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV]], [[MV1]]
; MIPS32: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64) ; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
; MIPS32: $v0 = COPY [[UV2]](s32) ; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV3]](s32) ; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%1:_(s32) = COPY $a0 %1:_(s32) = COPY $a0
%2:_(s32) = COPY $a1 %2:_(s32) = COPY $a1
%0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32) %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
%4:_(s64) = G_CONSTANT i64 1 %4:_(s64) = G_CONSTANT i64 1
%6:_(s64) = G_CONSTANT i64 0 %6:_(s64) = G_CONSTANT i64 0
%3:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64) %3:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64)
%5:_(s64) = nuw nsw G_ADD %3, %4 %5:_(s64) = nuw nsw G_ADD %3, %4
%7:_(s1) = G_ICMP intpred(eq), %0(s64), %6 %7:_(s1) = G_ICMP intpred(eq), %0(s64), %6
%8:_(s64) = G_SELECT %7(s1), %6, %5 %8:_(s64) = G_SELECT %7(s1), %6, %5
%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64) %9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(s64)
$v0 = COPY %9(s32) $v0 = COPY %9(s32)
$v1 = COPY %10(s32) $v1 = COPY %10(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Linesbody: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64 ; MIPS32-LABEL: name: load4_s32_to_zextLoad4_s64
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px) ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[C]](s32) ; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v1 = COPY [[C]](s32)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0 %0:_(p0) = COPY $a0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.px) %2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32) $v0 = COPY %3(s32)
$v1 = COPY %4(s32) $v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines bb.1.entry:
; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64 ; MIPS32-LABEL: name: load4_s32_to_sextLoad4_s64
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px) ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.px)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[LOAD]], [[C]](s32)
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[ASHR]](s32) ; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v1 = COPY [[ASHR]](s32)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0 %0:_(p0) = COPY $a0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.px) %2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.px)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64) %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32) $v0 = COPY %3(s32)
$v1 = COPY %4(s32) $v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...

llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir

Show All 12 Lines
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: zext ; MIPS32-LABEL: name: zext
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32) ; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v1 = COPY [[C]](s32)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s64) = G_ZEXT %0(s32) %1:_(s64) = G_ZEXT %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
$v1 = COPY %3(s32) $v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...
--- ---
name: sext name: sext
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.1.entry: bb.1.entry:
liveins: $a0 liveins: $a0
; MIPS32-LABEL: name: sext ; MIPS32-LABEL: name: sext
; MIPS32: liveins: $a0 ; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32) ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32) ; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) ; MIPS32: $v1 = COPY [[ASHR]](s32)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1 ; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(s32) = COPY $a0 %0:_(s32) = COPY $a0
%1:_(s64) = G_SEXT %0(s32) %1:_(s64) = G_SEXT %0(s32)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64) %2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
$v1 = COPY %3(s32) $v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1 RetRA implicit $v0, implicit $v1
... ...