[ARM,MVE] Add intrinsics vclzq and vclsq.

[simon_tatham]

Summary

vclzq maps nicely to the existing target-independent @llvm.ctlz IR
intrinsic. But vclsq ('count leading sign bits') has no corresponding
target-independent intrinsic, so I've made up @llvm.arm.mve.vcls.

This commit adds the unpredicated forms only.

[simon_tatham]

Spotted a mistake by myself: I had accidentally implemented the vclsq intrinsics for unsigned integer types as well as signed. ACLE only defines them for signed integers.

Also rebased to current master.

[miyuki]

LGTM

clang/include/clang/Basic/arm_mve.td

let params = T.Unsigned in {
   defm vddup:  vxdup_mc<(?             imm_1248:$step), (?         $step)>;
   defm viwdup: vxdup_mc<(? u32:$limit, imm_1248:$step), (? $limit, $step)>;
   defm vdwdup: vxdup_mc<(? u32:$limit, imm_1248:$step), (? $limit, $step)>;
 }
 
 let params = T.Int in {
   def vmvnq: Intrinsic<Vector, (args Vector:$a),
                        (xor $a, (uint_max Vector))>;
+  def vclzq: Intrinsic<Vector, (args Vector:$a),
+                       (IRIntBase<"ctlz", [Vector]> $a, (i1 0))>;
 }
 let params = T.Signed in {
+  def vclsq: Intrinsic<Vector, (args Vector:$a), (IRInt<"vcls", [Vector]> $a)>;
   def vnegq: Intrinsic<Vector, (args Vector:$a),
                        (sub (zeroinit Vector), $a)>;
   def vabsq: Intrinsic<Vector, (args Vector:$a),
                        (select (icmp_slt $a, (zeroinit Vector)),
                                (sub (zeroinit Vector), $a), $a)>;
   def vqnegq: Intrinsic<Vector, (args Vector:$a),
                         (select (icmp_eq $a, (int_min Vector)),
                                 (int_max Vector),

clang/include/clang/Basic/arm_mve_defs.td

 def sitofp: IRBuilder<"CreateSIToFP">;
 def uitofp: IRBuilder<"CreateUIToFP">;
 def fptosi: IRBuilder<"CreateFPToSI">;
 def fptoui: IRBuilder<"CreateFPToUI">;
 def vrev: CGHelperFn<"ARMMVEVectorElementReverse"> {
   let special_params = [IRBuilderIntParam<1, "unsigned">];
 }
 
+// Helper for making boolean flags in IR
+def i1: IRBuilderBase {
+  let prefix = "llvm::ConstantInt::get(Builder.getInt1Ty(), ";
+  let special_params = [IRBuilderIntParam<0, "bool">];
+}
+
 // A node that makes an Address out of a pointer-typed Value, by
 // providing an alignment as the second argument.
 def address;
 
 // Another node class you can use in the codegen dag. This one corresponds to
 // an IR intrinsic function, which has to be specialized to a particular list
 // of types.
 class IRIntBase<string name_, list<Type> params_ = [], bit appendKind_ = 0> {

clang/test/CodeGen/arm-mve-intrinsics/vclz.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+#include <arm_mve.h>
+
+// CHECK-LABEL: @test_vclzq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A:%.*]], i1 false)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vclzq_s8(int8x16_t a)
+{
+#ifdef POLYMORPHIC
+    return vclzq(a);
+#else /* POLYMORPHIC */
+    return vclzq_s8(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[A:%.*]], i1 false)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vclzq_s16(int16x8_t a)
+{
+#ifdef POLYMORPHIC
+    return vclzq(a);
+#else /* POLYMORPHIC */
+    return vclzq_s16(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[A:%.*]], i1 false)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vclzq_s32(int32x4_t a)
+{
+#ifdef POLYMORPHIC
+    return vclzq(a);
+#else /* POLYMORPHIC */
+    return vclzq_s32(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_u8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A:%.*]], i1 false)
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+uint8x16_t test_vclzq_u8(uint8x16_t a)
+{
+#ifdef POLYMORPHIC
+    return vclzq(a);
+#else /* POLYMORPHIC */
+    return vclzq_u8(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[A:%.*]], i1 false)
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+uint16x8_t test_vclzq_u16(uint16x8_t a)
+{
+#ifdef POLYMORPHIC
+    return vclzq(a);
+#else /* POLYMORPHIC */
+    return vclzq_u16(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclzq_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[A:%.*]], i1 false)
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+uint32x4_t test_vclzq_u32(uint32x4_t a)
+{
+#ifdef POLYMORPHIC
+    return vclzq(a);
+#else /* POLYMORPHIC */
+    return vclzq_u32(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclsq_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> [[A:%.*]])
+// CHECK-NEXT:    ret <16 x i8> [[TMP0]]
+//
+int8x16_t test_vclsq_s8(int8x16_t a)
+{
+#ifdef POLYMORPHIC
+    return vclsq(a);
+#else /* POLYMORPHIC */
+    return vclsq_s8(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclsq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> [[A:%.*]])
+// CHECK-NEXT:    ret <8 x i16> [[TMP0]]
+//
+int16x8_t test_vclsq_s16(int16x8_t a)
+{
+#ifdef POLYMORPHIC
+    return vclsq(a);
+#else /* POLYMORPHIC */
+    return vclsq_s16(a);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vclsq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> [[A:%.*]])
+// CHECK-NEXT:    ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vclsq_s32(int32x4_t a)
+{
+#ifdef POLYMORPHIC
+    return vclsq(a);
+#else /* POLYMORPHIC */
+    return vclsq_s32(a);
+#endif /* POLYMORPHIC */
+}
+

llvm/include/llvm/IR/IntrinsicsARM.td

 // * unsigned
 defm int_arm_mve_vcvt_fix: MVEMXPredicated<
   [llvm_anyvector_ty /* output */], [llvm_i32_ty],
   [llvm_anyvector_ty /* input vector */, llvm_i32_ty /* scale */],
   LLVMMatchType<0>, llvm_anyvector_ty>;
 
 def int_arm_mve_vrintn: Intrinsic<
   [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
+def int_arm_mve_vcls: Intrinsic<
+  [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 
 } // end TargetPrefix

llvm/lib/Target/ARM/ARMInstrMVE.td

 
 let Predicates = [HasMVEInt] in {
   def : Pat<(v16i8 ( ctlz (v16i8 MQPR:$val1))),
             (v16i8 ( MVE_VCLZs8 (v16i8 MQPR:$val1)))>;
   def : Pat<(v4i32 ( ctlz (v4i32 MQPR:$val1))),
             (v4i32 ( MVE_VCLZs32 (v4i32 MQPR:$val1)))>;
   def : Pat<(v8i16 ( ctlz (v8i16 MQPR:$val1))),
             (v8i16 ( MVE_VCLZs16 (v8i16 MQPR:$val1)))>;
+
+  def : Pat<(v16i8 ( int_arm_mve_vcls (v16i8 MQPR:$val1))),
+            (v16i8 ( MVE_VCLSs8 (v16i8 MQPR:$val1)))>;
+  def : Pat<(v4i32 ( int_arm_mve_vcls (v4i32 MQPR:$val1))),
+            (v4i32 ( MVE_VCLSs32 (v4i32 MQPR:$val1)))>;
+  def : Pat<(v8i16 ( int_arm_mve_vcls (v8i16 MQPR:$val1))),
+            (v8i16 ( MVE_VCLSs16 (v8i16 MQPR:$val1)))>;
 }
 
 class MVE_VABSNEG_int<string iname, string suffix, bits<2> size, bit negate,
                       list<dag> pattern=[]>
   : MVEIntSingleSrc<iname, suffix, size, pattern> {
 
   let Inst{28} = 0b1;
   let Inst{25-23} = 0b111;

llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
+
+define arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> %a) {
+; CHECK-LABEL: test_vclsq_s8:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcls.s8 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %a)
+  ret <16 x i8> %0
+}
+
+define arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> %a) {
+; CHECK-LABEL: test_vclsq_s16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcls.s16 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %a)
+  ret <8 x i16> %0
+}
+
+define arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> %a) {
+; CHECK-LABEL: test_vclsq_s32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vcls.s32 q0, q0
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %a)
+  ret <4 x i32> %0
+}
+
+declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>)
+declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>)
+declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>)