Handle subregs and superregs in callee-saved register mask

[jrtc27]

Summary

If a target lists both a subreg and a superreg in a callee-saved
register mask, the prolog will spill both aliasing registers. Instead,
don't spill the subreg if a superreg is being spilled. This case is hit by the
PowerPC SPE code, as well as a modified RISC-V backend for CHERI I maintain out
of tree.

[jhibbits]

Thanks for doing this! It's been on my TODO list for a little while already for SPE, but I never got around to it.

Is there any provision for spilling only the subreg, not the superreg? It seems to me that whenever the subreg needs spilled, it always also spills the superreg, even if the full superreg is not used.

[fhahn]

llvm/lib/CodeGen/PrologEpilogInserter.cpp

404

nit: I think you could use MCRegisterInfo::subregs() which is slightly less code.

[arsenm]

llvm/lib/CodeGen/PrologEpilogInserter.cpp

404

These masks should eventually be in terms of regunits

[jrtc27]

In D73170#1833793, @jhibbits wrote:

Thanks for doing this! It's been on my TODO list for a little while already for SPE, but I never got around to it.

Is there any provision for spilling only the subreg, not the superreg? It seems to me that whenever the subreg needs spilled, it always also spills the superreg, even if the full superreg is not used.

No, because restoring a subreg often has the side-effect of clearing the rest of the superreg, thereby violating the callee-preserved nature of them. I don't know whether that applies to SPE or not (and therefore whether the previously generated code was technically wrong), but it certainly applies to CHERI RISC-V.

llvm/lib/CodeGen/PrologEpilogInserter.cpp

404

Ah yes, I remember seeing MCRegisterInfo::subregs() go in but originally wrote this patch (not for SPE) over a year ago. I will update to the nicer API.

[jrtc27]

Switch from explicit iterator to recently-added range-based for loop interface. Ok to merge?

[jrtc27]

Ping?

[luismarques]

In D73170#1871167, @jrtc27 wrote:

Ping?

Ping landing this?

[jrtc27]

Rebased

[jrtc27]

Post-D101282 fp-strict.ll also has SPE check lines that get improved by this patch

[nemanjai]

It appears that this is approved but it keeps getting pinged. @jrtc27 Do you need someone to land this for you or are you hoping that someone else also approve this (perhaps @fhahn or @arsenm)?

[jrtc27]

I was speaking with @jhibbits earlier who intends to sanity check the updated SPE test changes, not that I expect there to be any issues

[jhibbits]

The spe.ll respin looks fine to me.

llvm/lib/CodeGen/PrologEpilogInserter.cpp

static void assignCalleeSavedSpillSlots(MachineFunction &F,
                                         const BitVector &SavedRegs,
                                         unsigned &MinCSFrameIndex,
                                         unsigned &MaxCSFrameIndex) {
   if (SavedRegs.empty())
     return;
 
   const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
   const MCPhysReg *CSRegs = F.getRegInfo().getCalleeSavedRegs();
+  BitVector CSMask(SavedRegs.size());
+
+  for (unsigned i = 0; CSRegs[i]; ++i)
+    CSMask.set(CSRegs[i]);
 
   std::vector<CalleeSavedInfo> CSI;
   for (unsigned i = 0; CSRegs[i]; ++i) {
     unsigned Reg = CSRegs[i];
-    if (SavedRegs.test(Reg))
+    if (SavedRegs.test(Reg)) {
+      bool SavedSuper = false;
+      for (const MCPhysReg &SuperReg : RegInfo->superregs(Reg)) {
+        // Some backends set all aliases for some registers as saved, such as
+        // Mips's $fp, so they appear in SavedRegs but not CSRegs.
+        if (SavedRegs.test(SuperReg) && CSMask.test(SuperReg)) {
+          SavedSuper = true;
+          break;
+        }
+      }
+
+      if (!SavedSuper)
         CSI.push_back(CalleeSavedInfo(Reg));
     }
+  }
 
   const TargetFrameLowering *TFI = F.getSubtarget().getFrameLowering();
   MachineFrameInfo &MFI = F.getFrameInfo();
   if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) {
     // If target doesn't implement this, use generic code.
 
     if (CSI.empty())
       return; // Early exit if no callee saved registers are modified!

llvm/test/CodeGen/PowerPC/spe.ll

 
 declare void @test_memset(i8* nocapture writeonly, i8, i32, i1)
 @global_var1 = global i32 0, align 4
 define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) nounwind {
 ; CHECK-LABEL: test_spill:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
-; CHECK-NEXT:    stwu 1, -352(1)
+; CHECK-NEXT:    stwu 1, -272(1)
 ; CHECK-NEXT:    li 5, 256
 ; CHECK-NEXT:    evstddx 30, 1, 5 # 8-byte Folded Spill
 ; CHECK-NEXT:    li 5, 264
 ; CHECK-NEXT:    evstddx 31, 1, 5 # 8-byte Folded Spill
 ; CHECK-NEXT:    li 5, .LCPI56_0@l
 ; CHECK-NEXT:    lis 6, .LCPI56_0@ha
 ; CHECK-NEXT:    evlddx 5, 6, 5
-; CHECK-NEXT:    stw 14, 280(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 15, 284(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 16, 288(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 17, 292(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 18, 296(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 19, 300(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 20, 304(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 21, 308(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 22, 312(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 23, 316(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 24, 320(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 25, 324(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 26, 328(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 27, 332(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 28, 336(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 29, 340(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 30, 344(1) # 4-byte Folded Spill
-; CHECK-NEXT:    stw 31, 348(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    evstdd 14, 128(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 15, 136(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 16, 144(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 17, 152(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 18, 160(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 19, 168(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 20, 176(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 21, 184(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 22, 192(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 23, 200(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 24, 208(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 25, 216(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 26, 224(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 27, 232(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 28, 240(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 29, 248(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evmergelo 3, 3, 4
-; CHECK-NEXT:    lwz 4, 360(1)
+; CHECK-NEXT:    lwz 4, 280(1)
 ; CHECK-NEXT:    efdadd 3, 3, 3
 ; CHECK-NEXT:    efdadd 3, 3, 5
 ; CHECK-NEXT:    evstdd 3, 24(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    stw 4, 20(1) # 4-byte Folded Spill
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    addi 3, 1, 76
 ; CHECK-NEXT:    li 4, 0

 ; CHECK-NEXT:    li 5, 20
 ; CHECK-NEXT:    li 6, 1
 ; CHECK-NEXT:    bl test_memset
 ; CHECK-NEXT:    evldd 4, 24(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    li 5, 264
 ; CHECK-NEXT:    evmergehi 3, 4, 4
 ; CHECK-NEXT:    evlddx 31, 1, 5 # 8-byte Folded Reload
 ; CHECK-NEXT:    li 5, 256
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
 ; CHECK-NEXT:    evlddx 30, 1, 5 # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 29, 248(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 28, 240(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 27, 232(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 26, 224(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 25, 216(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 24, 208(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 23, 200(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 22, 192(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 21, 184(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 20, 176(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 19, 168(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 18, 160(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 17, 152(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 16, 144(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 15, 136(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    evldd 14, 128(1) # 8-byte Folded Reload
-; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
-; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
-; CHECK-NEXT:    lwz 31, 348(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 30, 344(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 29, 340(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 28, 336(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 27, 332(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 26, 328(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 25, 324(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 24, 320(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 23, 316(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 22, 312(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 21, 308(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 20, 304(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 19, 300(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 18, 296(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 17, 292(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 16, 288(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 15, 284(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 14, 280(1) # 4-byte Folded Reload
-; CHECK-NEXT:    lwz 0, 356(1)
-; CHECK-NEXT:    addi 1, 1, 352
+; CHECK-NEXT:    lwz 0, 276(1)
+; CHECK-NEXT:    addi 1, 1, 272
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 entry:
   %v1 = alloca [13 x i32], align 4
   %v2 = alloca [11 x i32], align 4
   %0 = fadd double %a, %a
   call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
   %1 = fadd double %0, 3.14159