If a target lists both a subreg and a superreg in a callee-saved
register mask, the prolog will spill both aliasing registers. Instead,
don't spill the subreg if a superreg is being spilled. This case is hit by the
PowerPC SPE code, as well as a modified RISC-V backend for CHERI I maintain out
of tree.
Details
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
Thanks for doing this! It's been on my TODO list for a little while already for SPE, but I never got around to it.
Is there any provision for spilling only the subreg, not the superreg? It seems to me that whenever the subreg needs spilled, it always also spills the superreg, even if the full superreg is not used.
llvm/lib/CodeGen/PrologEpilogInserter.cpp | ||
---|---|---|
408 | nit: I think you could use MCRegisterInfo::subregs() which is slightly less code. |
llvm/lib/CodeGen/PrologEpilogInserter.cpp | ||
---|---|---|
408 | These masks should eventually be in terms of regunits |
No, because restoring a subreg often has the side-effect of clearing the rest of the superreg, thereby violating the callee-preserved nature of them. I don't know whether that applies to SPE or not (and therefore whether the previously generated code was technically wrong), but it certainly applies to CHERI RISC-V.
llvm/lib/CodeGen/PrologEpilogInserter.cpp | ||
---|---|---|
408 | Ah yes, I remember seeing MCRegisterInfo::subregs() go in but originally wrote this patch (not for SPE) over a year ago. I will update to the nicer API. |
Switch from explicit iterator to recently-added range-based for loop interface. Ok to merge?
I was speaking with @jhibbits earlier who intends to sanity check the updated SPE test changes, not that I expect there to be any issues
nit: I think you could use MCRegisterInfo::subregs() which is slightly less code.