[PowerPC][Future] Add pld and pstd to future CPU

[NeHuang]

Summary

Add the prefixed instructions pld and pstd to future CPU. These are load and store instructions that require new operand types that are 34 bits. This patch adds the two instructions as well as the operand types required.

Note that this patch also makes a minor change to tablegen to account for the fact that some instructions are going to require shifts greater than 31 bits for the new 34 bit instructions.

[nemanjai]

Adding Florian, Daniel and Craig as reviewers since they were involved in the most recent change to this area of table gen.

[dsanders]

I'm not convinced you really need the FixedLenDecoderEmitter.cpp changes. PPCInstrFormats.td has bits<64> Inst in the I2 class, but PPCDisassembler.cpp has InsnType as being uint32_t . InsnType needs to be able to hold your biggest instruction for the generated code to work correctly. I believe that if you changed:

uint32_t Inst = ...;

in PPCDisassembler::getInstruction(), to:

uint64_t Inst = ...;

then you will no longer need to change FixedLenDecoderEmitter.cpp as you'll be able to use shifts of up to 63.

llvm/utils/TableGen/FixedLenDecoderEmitter.cpp

1115 ↗

(On Diff #237550)

The OpInfo.begin()->Offset != 0 part doesn't look right to me at the moment. I think you're trying to guard against shift emitted by the code guarded by the else if (OpInfo.numFields() != 1 || EF.Offset != 0) on line 1133 (1120 in the old code) but here you only look at the first field whereas the original guard is checking all of them. Is there some sort order that guarantees that only the first field matters?

1120 ↗

(On Diff #237550)

You can't really rely on sizeof(InsnType) being meaningful as InsnType is allowed to be an object. For example, that object might be using an APInt internally. You'll need to provide a template that can handle both integer and object InsnTypes.

[NeHuang]

Commandeer the patch.

[NeHuang]

Thanks @dsanders. Comment addressed.

[amyk]

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

281

Do we need an assert here, as well?

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

472

nit: spacing between OpNo + 1, and to make it consistent with printMemRegImm34 and the rest of the functions in this file.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

168

s/immedaite/immediate.

llvm/test/MC/Disassembler/PowerPC/future-invalid.txt

2

Line too long?

[NeHuang]

Addressed review comments above.

[NeHuang]

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

281

+1

[nemanjai]

LGTM.

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

bool isS16Imm() const {
     }
   }
   bool isS16ImmX4() const { return Kind == Expression ||
                                    (Kind == Immediate && isInt<16>(getImm()) &&
                                     (getImm() & 3) == 0); }
   bool isS16ImmX16() const { return Kind == Expression ||
                                     (Kind == Immediate && isInt<16>(getImm()) &&
                                      (getImm() & 15) == 0); }
+  bool isS34ImmX16() const { return Kind == Expression ||
+                                    (Kind == Immediate && isInt<34>(getImm()) &&
+                                    (getImm() & 15) == 0); }
   bool isS34Imm() const {
     // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
     // ContextImmediate is needed.
     return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()));
   }
 
   bool isS17Imm() const {
     switch (Kind) {

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
 
   assert(Base < 32 && "Invalid base register");
 
   Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
+                                               int64_t Address,
+                                               const void *Decoder) {
+  // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
+  // displacement, and the next 5 bits as an immediate 0.
+  uint64_t Base = Imm >> 34;
+  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
+
+  assert(Base < 32 && "Invalid base register");
+
+  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
+  return decodeImmZeroOperand(Inst, Base, Address, Decoder);
+}
+
+static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
+                                          int64_t Address,
+                                          const void *Decoder) {
+  // Decode the memri34 field (imm, reg), which has the low 34-bits as the
+  // displacement, and the next 5 bits as the register #.
+  uint64_t Base = Imm >> 34;
+  uint64_t Disp = Imm & 0x3FFFFFFFFUL;
+
+  assert(Base < 32 && "Invalid base register");
+
+  Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
+  Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
                                          int64_t Address, const void *Decoder) {
   // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
   // displacement with 8-byte aligned, and the next 5 bits as the register #.
 
   uint64_t Base = Imm >> 5;
   uint64_t Disp = Imm & 0x1F;
 

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h

public:
   void printImmZeroOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
   void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 
   void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printMemRegImm34(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
   O << '(';
   if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
     O << "0";
   else
     printOperand(MI, OpNo+1, O);
   O << ')';
 }
 
+void PPCInstPrinter::printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo,
+                                           raw_ostream &O) {
+  printS34ImmOperand(MI, OpNo, O);
+  O << '(';
+  printImmZeroOperand(MI, OpNo+1, O);
+  O << ')';
+}
+
+void PPCInstPrinter::printMemRegImm34(const MCInst *MI, unsigned OpNo,
+                                        raw_ostream &O) {
+  printS34ImmOperand(MI, OpNo, O);
+  O << '(';
+  printOperand(MI, OpNo+1, O);
+  O << ')';
+}
+
 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
                                     raw_ostream &O) {
   // When used as the base register, r0 reads constant zero rather than
   // the value contained in the register.  For this reason, the darwin
   // assembler requires that we print r0 as 0 (no r) when used as the base.
   if (MI->getOperand(OpNo).getReg() == PPC::R0)
     O << "0";
   else

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h

unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
                             SmallVectorImpl<MCFixup> &Fixups,
                             const MCSubtargetInfo &STI) const;
   unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const;
   unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
+  uint64_t getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
+                                   SmallVectorImpl<MCFixup> &Fixups,
+                                   const MCSubtargetInfo &STI) const;
+  uint64_t getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
+                              SmallVectorImpl<MCFixup> &Fixups,
+                              const MCSubtargetInfo &STI) const;
   unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
   unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
   unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
                               SmallVectorImpl<MCFixup> &Fixups,

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
   }
 
   // Otherwise add a fixup for the displacement field.
   Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_half16ds));
   return RegBits;
 }
 
+uint64_t
+PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  // Encode (imm, reg) as a memri34, which has the low 34-bits as the
+  // displacement and the next 5 bits as an immediate 0.
+  assert(MI.getOperand(OpNo + 1).isImm() && "Expecting an immediate.");
+  uint64_t RegBits =
+    getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
+
+  if (RegBits != 0)
+    report_fatal_error("Operand must be 0");
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+  return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
+}
+
+uint64_t
+PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
+                                     SmallVectorImpl<MCFixup> &Fixups,
+                                     const MCSubtargetInfo &STI) const {
+  // Encode (imm, reg) as a memri34, which has the low 34-bits as the
+  // displacement and the next 5 bits as the register #.
+  assert(MI.getOperand(OpNo + 1).isReg() && "Expecting a register.");
+  uint64_t RegBits =
+    getMachineOpValue(MI, MI.getOperand(OpNo + 1), Fixups, STI) << 34;
+
+  const MCOperand &MO = MI.getOperand(OpNo);
+  return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
+}
+
 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
                                               SmallVectorImpl<MCFixup> &Fixups,
                                               const MCSubtargetInfo &STI)
                                               const {
   // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
   // as the displacement and the next 5 bits as the register #.
   assert(MI.getOperand(OpNo+1).isReg());
   uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5;

llvm/lib/Target/PowerPC/PPC.td

def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
                                                  "VectorsUseTwoUnits",
                                                  "true",
                                                  "Vectors use two units">;
 def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
                                            "true",
                                            "Enable prefixed instructions",
                                            [FeatureISA3_0, FeatureP8Vector,
                                             FeatureP9Altivec]>;
+def FeaturePCRelativeMemops :
+  SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
+                   "Enable PC relative Memory Ops",
+                   [FeatureISA3_0]>;
 
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
 // less error prone and easier to read.
 // Namely:
 //     list<SubtargetFeature> P8InheritableFeatures = ...
 //     list<SubtargetFeature> FutureProcessorAddtionalFeatures =
 //         [ features that Power8 does not support but inheritable ]
list<SubtargetFeature> P9InheritableFeatures =
     !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
   list<SubtargetFeature> P9Features =
     !listconcat(P9InheritableFeatures, P9SpecificFeatures);
 
   // Future
   // For future CPU we assume that all of the existing features from Power 9
   // still exist with the exception of those we know are Power 9 specific.
   list<SubtargetFeature> FutureAdditionalFeatures = [];
-  list<SubtargetFeature> FutureSpecificFeatures = [FeaturePrefixInstrs];
+  list<SubtargetFeature> FutureSpecificFeatures =
+    [FeaturePrefixInstrs, FeaturePCRelativeMemops];
   list<SubtargetFeature> FutureInheritableFeatures =
     !listconcat(P9InheritableFeatures, FutureAdditionalFeatures);
   list<SubtargetFeature> FutureFeatures =
     !listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
 }
 
 // Note: Future features to add when support is extended to more
 // recent ISA levels:

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 // Address operands
 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
 def PPCRegGxRCNoR0Operand : AsmOperandClass {
   let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
 }
 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> {
   let ParserMatchClass = PPCRegGxRCNoR0Operand;
 }
+
+// New addressing modes with 34 bit immediates.
+def PPCDispRI34Operand : AsmOperandClass {
+  let Name = "DispRI34"; let PredicateMethod = "isS34Imm";
+  let RenderMethod = "addImmOperands";
+}
+def dispRI34 : Operand<iPTR> {
+  let ParserMatchClass = PPCDispRI34Operand;
+}
+def memri34 : Operand<iPTR> { // memri, imm is a 34-bit value.
+  let PrintMethod = "printMemRegImm34";
+  let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg);
+  let EncoderMethod = "getMemRI34Encoding";
+  let DecoderMethod = "decodeMemRI34Operands";
+}
+// memri, imm is a 34-bit value for pc-relative instructions where
+// base register is set to zero.
+def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value.
+  let PrintMethod = "printMemRegImm34PCRel";
+  let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg);
+  let EncoderMethod = "getMemRI34PCRelEncoding";
+  let DecoderMethod = "decodeMemRI34PCRelOperands";
+}
+
 // A version of ptr_rc usable with the asm parser.
 def PPCRegGxRCOperand : AsmOperandClass {
   let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
 }
 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> {
   let ParserMatchClass = PPCRegGxRCOperand;
 }
 

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
                                    dag PCRel_IOL, string asmstr,
                                    InstrItinClass itin> {
   def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
                                    !strconcat(asmstr, ", 0"), itin, []>;
   def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
                                  !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
 }
 
+class 8LS_DForm_R_D34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+                           InstrItinClass itin, list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RT;
+  bits<39> D_RA;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-10} = 0;
+  let Inst{11} = PCRel;
+  let Inst{12-13} = 0;
+  let Inst{14-31} = D_RA{33-16}; // d0
+
+  // The instruction.
+  let Inst{38-42} = RT{4-0};
+  let Inst{43-47} = D_RA{38-34}; // RA
+  let Inst{48-63} = D_RA{15-0}; // d1
+}
+
+multiclass 8LS_DForm_R_D34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
+                                  dag PCRel_IOL, string asmstr,
+                                  InstrItinClass itin> {
+  def NAME : 8LS_DForm_R_D34_RTA5<opcode, OOL, IOL,
+                                  !strconcat(asmstr, ", 0"), itin, []>;
+  def pc : 8LS_DForm_R_D34_RTA5<opcode, OOL, PCRel_IOL,
+                                !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
+}
 
 def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">;
 
 let Predicates = [PrefixInstrs] in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     defm PADDI8 :
       MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
                               (ins immZero:$RA, s34imm:$SI),
                               "paddi $RT, $RA, $SI", IIC_LdStLFD>;
     let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
       def PLI8 : MLS_DForm2_r0<14, (outs g8rc:$RT),
                                (ins s34imm:$SI),
                                "pli $RT, $SI", IIC_IntSimple, []>;
     }
   }
   defm PADDI :
     MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
                             (ins immZero:$RA, s34imm:$SI),
                             "paddi $RT, $RA, $SI", IIC_LdStLFD>;
   let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
     def PLI : MLS_DForm2_r0<14, (outs gprc:$RT),
                             (ins s34imm:$SI),
                             "pli $RT, $SI", IIC_IntSimple, []>;
   }
+
+  let mayLoad = 1, mayStore = 0 in {
+    defm PLD :
+      8LS_DForm_R_D34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
+                             (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
+                             IIC_LdStLFD>;
+  }
+
+  let mayStore = 1, mayLoad = 0 in {
+    defm PSTD :
+      8LS_DForm_R_D34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
+                             (ins g8rc:$RS, memri34_pcrel:$D_RA),
+                             "pstd $RS, $D_RA", IIC_LdStLFD>;
+  }
 }
 

llvm/lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool HasVSX;
   bool NeedsTwoConstNR;
   bool HasP8Vector;
   bool HasP8Altivec;
   bool HasP8Crypto;
   bool HasP9Vector;
   bool HasP9Altivec;
   bool HasPrefixInstrs;
+  bool HasPCRelativeMemops;
   bool HasFCPSGN;
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
   bool HasRecipPrec;
   bool HasSTFIWX;
   bool HasLFIWAX;
   bool HasFPRND;
   bool HasFPCVT;
public:
   bool hasVSX() const { return HasVSX; }
   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasP9Vector() const { return HasP9Vector; }
   bool hasP9Altivec() const { return HasP9Altivec; }
   bool hasPrefixInstrs() const { return HasPrefixInstrs; }
+  bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
   bool hasBPERMD() const { return HasBPERMD; }
   bool hasExtDiv() const { return HasExtDiv; }
   bool hasCMPB() const { return HasCMPB; }
   bool hasLDBRX() const { return HasLDBRX; }
   bool isBookE() const { return IsBookE; }
   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   HasVSX = false;
   NeedsTwoConstNR = false;
   HasP8Vector = false;
   HasP8Altivec = false;
   HasP8Crypto = false;
   HasP9Vector = false;
   HasP9Altivec = false;
   HasPrefixInstrs = false;
+  HasPCRelativeMemops = false;
   HasFCPSGN = false;
   HasFSQRT = false;
   HasFRE = false;
   HasFRES = false;
   HasFRSQRTE = false;
   HasFRSQRTES = false;
   HasRecipPrec = false;
   HasSTFIWX = false;

llvm/test/CodeGen/PowerPC/future-check-features.ll

-; RUN: llc -mattr=prefix-instrs -verify-machineinstrs \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
 ; RUN:   -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
 ; RUN:   %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=prefix-instrs -verify-machineinstrs \
+; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
 ; RUN:   -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
 ; RUN:   %s -o - 2>&1 | FileCheck %s
 
 define dso_local signext i32 @f() {
 entry:
   ret i32 0
 }
 
 ; Make sure that all of the features listed are recognized.
 ; CHECK-NOT:    is not a recognized feature for this target
 
 ; Make sure that the test was actually compiled.
 ; CHECK:        li r3, 0
 ; CHECK-NEXT:   blr
 

llvm/test/MC/Disassembler/PowerPC/future-invalid.txt

+# RUN: llvm-mc --disassemble %s -mcpu=future -triple \
+# RUN:   powerpc64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
+
+# paddi 1, 2, 8589934591, 1. However, RA is not zero with R=1
+# CHECK: warning: invalid instruction encoding
+0x06 0x11 0xff 0xff 0x38 0x22 0xff 0xff
+
+# pld 1, -8589934592(3), 1. However, RA is not zero with R=1
+# CHECK: warning: invalid instruction encoding
+0x04 0x12 0x00 0x00 0xe0 0x23 0x00 0x00
+

llvm/test/MC/Disassembler/PowerPC/futureinsts.txt

 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
 # RUN:   -mcpu=future | FileCheck %s
 
 # CHECK: paddi 1, 2, 8589934591, 0
 0x06 0x01 0xff 0xff 0x38 0x22 0xff 0xff
 
 # CHECK: paddi 1, 0, -8589934592, 1
 0x06 0x12 0x00 0x00 0x38 0x20 0x00 0x00
 
+# CHECK: pld 1, -8589934592(3), 0
+0x04 0x02 0x00 0x00 0xe4 0x23 0x00 0x00
+
+# CHECK: pld 1, 8589934591(0), 1
+0x04 0x11 0xff 0xff 0xe4 0x20 0xff 0xff
+

llvm/test/MC/PowerPC/future-errors.s

+# RUN: not llvm-mc -triple powerpc64-unknown-unknown < %s 2> %t
+# RUN: FileCheck < %t %s
+# RUN: not llvm-mc -triple powerpc64le-unknown-unknown < %s 2> %t
+# RUN: FileCheck < %t %s
+
+ # CHECK: error: invalid operand for instruction
+paddi 1, 1, 32, 1
+
+# CHECK: error: invalid operand for instruction
+pld 1, 32(1), 1
+

llvm/test/MC/PowerPC/future.s

 # CHECK-LE: pli 1, -8589934592                    # encoding: [0x00,0x00,0x02,0x06
 # CHECK-LE-SAME:                                               0x00,0x00,0x20,0x38]
             pli 1, -8589934592
 # CHECK-BE: pli 1, 8589934591                     # encoding: [0x06,0x01,0xff,0xff
 # CHECK-BE-SAME:                                               0x38,0x20,0xff,0xff]
 # CHECK-LE: pli 1, 8589934591                     # encoding: [0xff,0xff,0x01,0x06
 # CHECK-LE-SAME:                                               0xff,0xff,0x20,0x38]
             pli 1, 8589934591
-
+# CHECK-BE: pld 1, -8589934592(3), 0              # encoding: [0x04,0x02,0x00,0x00,
+# CHECK-BE-SAME:                                               0xe4,0x23,0x00,0x00]
+# CHECK-LE: pld 1, -8589934592(3), 0              # encoding: [0x00,0x00,0x02,0x04
+# CHECK-LE-SAME:                                               0x00,0x00,0x23,0xe4]
+            pld 1, -8589934592(3), 0
+# CHECK-BE: pld 1, 8589934591(0), 1               # encoding: [0x04,0x11,0xff,0xff
+# CHECK-BE-SAME:                                               0xe4,0x20,0xff,0xff]
+# CHECK-LE: pld 1, 8589934591(0), 1               # encoding: [0xff,0xff,0x11,0x04,
+# CHECK-LE-SAME:                                               0xff,0xff,0x20,0xe4]
+            pld 1, 8589934591(0), 1