[POC][SVE] Allow code generation for fixed length vectorised loops [Patch 1/2].

[paulwalker-arm]

Summary

No expectations for review at this stage unless you are super keen.

This is a proof of concept patch to show how SVE can be used to code generate fixed length vectors. It represents the minimum amount of SVE instructions (ld1, st1, uzp, uunpklo) required to get most workloads to run.

The general idea is to make all fixed length vector types that fit within a user specified size legal and custom lower all fixed length vector operations to scalable vector operations that use a suitably created predicate. After legalisation there should be no vector operations that operate on fixed length vectors beyond insert/extract_subvector and various extends and truncate. The reason for special case these operations is to maximum our ability for DAG combine to remove them. Those still around at isel get custom selected within ISelDagToDag.

[efriedma]

I've spent a little time considering alternatives. There are basically a few possibilities here:

1. Say the types aren't legal, and convert the types as part of type legalization.
2. Say the types are legal, but the operations aren't, and custom-legalize (or teach LegalizeDAG to legalize) all the operations.
3. Say the types and patterns are legal, and add a bunch of extra patterns to match the instructions.

Any of these options have rough edges... but type legalization seems more natural to me. That would let you rewrite all the types, so you aren't stuck with "fake" types for values that are live across basic blocks. And it would let you take more advantage of existing type legalization infrastructure: you don't have to have a custom legalization handler for every SVE operation, and you probably get better handling of cases where the fixed->scalable transform still leaves some illegal types. And the code would be naturally shared with other targets.

You haven't really demonstrated how you plan to handle i1 vectors, in particular, <8 x i1> might be <vscale x 8 x i1> or <vscale x 4 x i1> depending on how it's generated/used. You can probably make it work with your current approach; I guess you end up inserting predicate pack/unpack operations in Select(), and we should be able to eliminate most of the redundant operations? Not completely sure how that works out. (If an i1 vector is live across basic blocks, the generated code gets really messy, but that's not really specific to SVE.)

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

3139 ↗

(On Diff #234877)

If we're going to use this approach, we probably want to custom legalize TRUNCATE and ANY_EXTEND, and leave only the INSERT_SUBVECTOR/EXTRACT_SUBVECTOR operations to be handled in Select().

[paulwalker-arm]

Rebasing to reflect the majority of the functionality is now in master. What remains is likely to be abandoned in favour of function attributes but it's here for those who want to experiment.

[paulwalker-arm]

Rebase.

[paulwalker-arm]

The intention of this patch is now complete. All work is available in master with the exception of the hook into -msve-vector-bits which is not necessarily the direction we'll use once function attributes are available.

clang/lib/Driver/ToolChains/Clang.cpp

if (IndirectBranches)
       CmdArgs.push_back("-mbranch-target-enforce");
   }
 
   // Handle -msve_vector_bits=<bits>
   if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits_EQ)) {
     StringRef Val = A->getValue();
     const Driver &D = getToolChain().getDriver();
     if (Val.equals("128") || Val.equals("256") || Val.equals("512") ||
-        Val.equals("1024") || Val.equals("2048"))
+        Val.equals("1024") || Val.equals("2048")) {
       CmdArgs.push_back(
           Args.MakeArgString(llvm::Twine("-msve-vector-bits=") + Val));
+      CmdArgs.push_back("-mllvm");
+      CmdArgs.push_back(
+          Args.MakeArgString("-aarch64-sve-vector-bits-min=" + Val));
+      // CmdArgs.push_back("-mllvm");
+      // CmdArgs.push_back(
+      //    Args.MakeArgString("-aarch64-sve-vector-bits-max=" + Val));
+    }
     // Silently drop requests for vector-length agnostic code as it's implied.
     else if (!Val.equals("scalable"))
       // Handle the unsupported values passed to msve-vector-bits.
       D.Diag(diag::err_drv_unsupported_option_argument)
           << A->getOption().getName() << Val;
   }
 }