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Differential D71211

[Codegen][X86] Modernize/regenerate old tests. NFCI.
ClosedPublic

Authored by xbolva00 on Dec 9 2019, 7:48 AM.

Details

Reviewers
craig.topper
spatel
RKSimon
Commits
rG584ed8822631: [Codegen][X86] Modernize/regenerate old tests. NFCI.
Summary

Switch to FileCheck where possible.
Adjust tests so they can be easily regenerated by update scripts.

Diff Detail

Event Timeline

xbolva00 created this revision.Dec 9 2019, 7:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2019, 7:48 AM
Herald added subscribers: llvm-commits, jfb, arphaman and 2 others. · View Herald Transcript
Harbormaster completed remote builds in B42136: Diff 232863.Dec 9 2019, 7:48 AM
xbolva00 retitled this revision from [Codegen][X86] Modernize/regenerated old tests. NFCI. to [Codegen][X86] Modernize/regenerate old tests. NFCI..Dec 9 2019, 7:51 AM
spatel accepted this revision.Dec 9 2019, 2:15 PM

I just spot checked about 10 of the files, and the changes seem mostly mechanical, so LGTM. Up to you whether you want to try this in 1 commit and risk breaking bots or split into bite-size chunks. :)

This revision is now accepted and ready to land.Dec 9 2019, 2:15 PM
Closed by commit rG584ed8822631: [Codegen][X86] Modernize/regenerate old tests. NFCI. (authored by xbolva00). · Explain WhyDec 9 2019, 3:30 PM
This revision was automatically updated to reflect the committed changes.
xbolva00 added a comment.Dec 9 2019, 3:44 PM
In D71211#1776095, @spatel wrote:

I just spot checked about 10 of the files, and the changes seem mostly mechanical, so LGTM. Up to you whether you want to try this in 1 commit and risk breaking bots or split into bite-size chunks. :)

Thanks. Bots are fine with this one huge commit, it seems :) I will watch bots for any issues.

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Diff 232950

llvm/test/CodeGen/X86/2006-04-27-ISelFoldingBug.ll

; RUN: llc < %s -mtriple=i686-apple-darwin8 -relocation-model=static > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "movl _last" %t | count 1 ; RUN: llc < %s -mtriple=i686-apple-darwin8 -relocation-model=static | FileCheck %s
; RUN: grep "cmpl.*_last" %t | count 1
@block = external global i8* ; <i8**> [#uses=1] @block = external global i8* ; <i8**> [#uses=1]
@last = external global i32 ; <i32*> [#uses=3] @last = external global i32 ; <i32*> [#uses=3]
define i1 @loadAndRLEsource_no_exit_2E_1_label_2E_0(i32 %tmp.21.reload, i32 %tmp.8) { define i1 @loadAndRLEsource_no_exit_2E_1_label_2E_0(i32 %tmp.21.reload, i32 %tmp.8) {
; CHECK-LABEL: loadAndRLEsource_no_exit_2E_1_label_2E_0:
; CHECK: ## %bb.0: ## %newFuncRoot
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl _last, %edx
; CHECK-NEXT: leal 1(%edx), %esi
; CHECK-NEXT: movl %esi, _last
; CHECK-NEXT: movl _block, %esi
; CHECK-NEXT: movb %al, 1(%esi,%edx)
; CHECK-NEXT: cmpl %ecx, _last
; CHECK-NEXT: jge LBB0_3
; CHECK-NEXT: ## %bb.1: ## %label.0
; CHECK-NEXT: cmpl $257, %eax ## imm = 0x101
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: ## %bb.2: ## %label.0.no_exit.1_crit_edge.exitStub
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_3: ## %codeRepl5.exitStub
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
newFuncRoot: newFuncRoot:
br label %label.0 br label %label.0
label.0.no_exit.1_crit_edge.exitStub: ; preds = %label.0 label.0.no_exit.1_crit_edge.exitStub: ; preds = %label.0
ret i1 true ret i1 true
codeRepl5.exitStub: ; preds = %label.0 codeRepl5.exitStub: ; preds = %label.0
ret i1 false ret i1 false
label.0: ; preds = %newFuncRoot label.0: ; preds = %newFuncRoot
%tmp.35 = load i32, i32* @last ; <i32> [#uses=1] %tmp.35 = load i32, i32* @last ; <i32> [#uses=1]
Show All 13 Lines

llvm/test/CodeGen/X86/2006-05-08-CoalesceSubRegClass.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Coalescing from R32 to a subset R32_. Once another register coalescer bug is ; Coalescing from R32 to a subset R32_. Once another register coalescer bug is
; fixed, the movb should go away as well. ; fixed, the movb should go away as well.
; RUN: llc < %s -mtriple=i686-- -relocation-model=static | \ ; RUN: llc < %s -mtriple=i686-- -relocation-model=static | FileCheck %s
; RUN: grep movl
@B = external global i32 ; <i32*> [#uses=2] @B = external global i32 ; <i32*> [#uses=2]
@C = external global i16* ; <i16**> [#uses=2] @C = external global i16* ; <i16**> [#uses=2]
define void @test(i32 %A) { define void @test(i32 %A) {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: andb $16, %cl
; CHECK-NEXT: shll %cl, B
; CHECK-NEXT: shrl $3, %eax
; CHECK-NEXT: addl %eax, C
; CHECK-NEXT: retl
%A.upgrd.1 = trunc i32 %A to i8 ; <i8> [#uses=1] %A.upgrd.1 = trunc i32 %A to i8 ; <i8> [#uses=1]
%tmp2 = load i32, i32* @B ; <i32> [#uses=1] %tmp2 = load i32, i32* @B ; <i32> [#uses=1]
%tmp3 = and i8 %A.upgrd.1, 16 ; <i8> [#uses=1] %tmp3 = and i8 %A.upgrd.1, 16 ; <i8> [#uses=1]
%shift.upgrd.2 = zext i8 %tmp3 to i32 ; <i32> [#uses=1] %shift.upgrd.2 = zext i8 %tmp3 to i32 ; <i32> [#uses=1]
%tmp4 = shl i32 %tmp2, %shift.upgrd.2 ; <i32> [#uses=1] %tmp4 = shl i32 %tmp2, %shift.upgrd.2 ; <i32> [#uses=1]
store i32 %tmp4, i32* @B store i32 %tmp4, i32* @B
%tmp6 = lshr i32 %A, 3 ; <i32> [#uses=1] %tmp6 = lshr i32 %A, 3 ; <i32> [#uses=1]
%tmp = load i16*, i16** @C ; <i16*> [#uses=1] %tmp = load i16*, i16** @C ; <i16*> [#uses=1]
%tmp8 = ptrtoint i16* %tmp to i32 ; <i32> [#uses=1] %tmp8 = ptrtoint i16* %tmp to i32 ; <i32> [#uses=1]
%tmp9 = add i32 %tmp8, %tmp6 ; <i32> [#uses=1] %tmp9 = add i32 %tmp8, %tmp6 ; <i32> [#uses=1]
%tmp9.upgrd.3 = inttoptr i32 %tmp9 to i16* ; <i16*> [#uses=1] %tmp9.upgrd.3 = inttoptr i32 %tmp9 to i16* ; <i16*> [#uses=1]
store i16* %tmp9.upgrd.3, i16** @C store i16* %tmp9.upgrd.3, i16** @C
ret void ret void
} }

llvm/test/CodeGen/X86/2006-05-08-InstrSched.ll

; RUN: llc < %s -mtriple=i686-- -relocation-model=static | not grep "subl.*%esp" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -relocation-model=static | FileCheck %s
@A = external global i16* ; <i16**> [#uses=1] @A = external global i16* ; <i16**> [#uses=1]
@B = external global i32 ; <i32*> [#uses=1] @B = external global i32 ; <i32*> [#uses=1]
@C = external global i32 ; <i32*> [#uses=2] @C = external global i32 ; <i32*> [#uses=2]
define void @test() { define void @test() {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: movl A, %eax
; CHECK-NEXT: movzwl 2(%eax), %eax
; CHECK-NEXT: movb B, %cl
; CHECK-NEXT: movl C, %edx
; CHECK-NEXT: andb $16, %cl
; CHECK-NEXT: shll %cl, %edx
; CHECK-NEXT: xorb $16, %cl
; CHECK-NEXT: shrl %cl, %eax
; CHECK-NEXT: orl %edx, %eax
; CHECK-NEXT: movl %eax, C
; CHECK-NEXT: retl
%tmp = load i16*, i16** @A ; <i16*> [#uses=1] %tmp = load i16*, i16** @A ; <i16*> [#uses=1]
%tmp1 = getelementptr i16, i16* %tmp, i32 1 ; <i16*> [#uses=1] %tmp1 = getelementptr i16, i16* %tmp, i32 1 ; <i16*> [#uses=1]
%tmp.upgrd.1 = load i16, i16* %tmp1 ; <i16> [#uses=1] %tmp.upgrd.1 = load i16, i16* %tmp1 ; <i16> [#uses=1]
%tmp3 = zext i16 %tmp.upgrd.1 to i32 ; <i32> [#uses=1] %tmp3 = zext i16 %tmp.upgrd.1 to i32 ; <i32> [#uses=1]
%tmp.upgrd.2 = load i32, i32* @B ; <i32> [#uses=1] %tmp.upgrd.2 = load i32, i32* @B ; <i32> [#uses=1]
%tmp4 = and i32 %tmp.upgrd.2, 16 ; <i32> [#uses=1] %tmp4 = and i32 %tmp.upgrd.2, 16 ; <i32> [#uses=1]
%tmp5 = load i32, i32* @C ; <i32> [#uses=1] %tmp5 = load i32, i32* @C ; <i32> [#uses=1]
%tmp6 = trunc i32 %tmp4 to i8 ; <i8> [#uses=2] %tmp6 = trunc i32 %tmp4 to i8 ; <i8> [#uses=2]
Show All 10 Lines

llvm/test/CodeGen/X86/2006-07-28-AsmPrint-Long-As-Pointer.ll

; RUN: llc < %s -mtriple=i686-- | grep -- 4294967240 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; PR853 ; PR853
; CHECK: 4294967240
@X = global i32* inttoptr (i64 -56 to i32*) ; <i32**> [#uses=0] @X = global i32* inttoptr (i64 -56 to i32*) ; <i32**> [#uses=0]

llvm/test/CodeGen/X86/2006-08-21-ExtraMovInst.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=i386 | \ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep "movl %eax, %edx" ; RUN: llc < %s -mtriple=i686-- -mcpu=i386 | FileCheck %s
define i32 @foo(i32 %t, i32 %C) { define i32 @foo(i32 %t, i32 %C) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: decl %eax
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %cond_true
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: incl %eax
; CHECK-NEXT: cmpl $40, %ecx
; CHECK-NEXT: jl .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb12
; CHECK-NEXT: retl
entry: entry:
br label %cond_true br label %cond_true
cond_true: ; preds = %cond_true, %entry cond_true: ; preds = %cond_true, %entry
%t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=2] %t_addr.0.0 = phi i32 [ %t, %entry ], [ %tmp7, %cond_true ] ; <i32> [#uses=2]
%tmp7 = add i32 %t_addr.0.0, 1 ; <i32> [#uses=1] %tmp7 = add i32 %t_addr.0.0, 1 ; <i32> [#uses=1]
%tmp = icmp sgt i32 %C, 39 ; <i1> [#uses=1] %tmp = icmp sgt i32 %C, 39 ; <i1> [#uses=1]
br i1 %tmp, label %bb12, label %cond_true br i1 %tmp, label %bb12, label %cond_true
bb12: ; preds = %cond_true bb12: ; preds = %cond_true
ret i32 %t_addr.0.0 ret i32 %t_addr.0.0
} }

llvm/test/CodeGen/X86/2006-10-10-FindModifiedNodeSlotBug.ll

; RUN: llc < %s -mtriple=i686-- | grep shrl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; Bug in FindModifiedNodeSlot cause tmp14 load to become a zextload and shr 31 ; Bug in FindModifiedNodeSlot cause tmp14 load to become a zextload and shr 31
; is then optimized away. ; is then optimized away.
@tree_code_type = external global [0 x i32] ; <[0 x i32]*> [#uses=1] @tree_code_type = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
define void @copy_if_shared_r() { define void @copy_if_shared_r() {
; CHECK-LABEL: copy_if_shared_r:
; CHECK: # %bb.0:
; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: movzbl %al, %ecx
; CHECK-NEXT: movl tree_code_type(,%ecx,4), %ecx
; CHECK-NEXT: decl %ecx
; CHECK-NEXT: cmpl $2, %ecx
; CHECK-NEXT: ja .LBB0_2
; CHECK-NEXT: # %bb.1: # %cond_true
; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: .LBB0_2: # %cond_true17
; CHECK-NEXT: retl
%tmp = load i32, i32* null ; <i32> [#uses=1] %tmp = load i32, i32* null ; <i32> [#uses=1]
%tmp56 = and i32 %tmp, 255 ; <i32> [#uses=1] %tmp56 = and i32 %tmp, 255 ; <i32> [#uses=1]
%gep.upgrd.1 = zext i32 %tmp56 to i64 ; <i64> [#uses=1] %gep.upgrd.1 = zext i32 %tmp56 to i64 ; <i64> [#uses=1]
%tmp8 = getelementptr [0 x i32], [0 x i32]* @tree_code_type, i32 0, i64 %gep.upgrd.1 ; <i32*> [#uses=1] %tmp8 = getelementptr [0 x i32], [0 x i32]* @tree_code_type, i32 0, i64 %gep.upgrd.1 ; <i32*> [#uses=1]
%tmp9 = load i32, i32* %tmp8 ; <i32> [#uses=1] %tmp9 = load i32, i32* %tmp8 ; <i32> [#uses=1]
%tmp10 = add i32 %tmp9, -1 ; <i32> [#uses=1] %tmp10 = add i32 %tmp9, -1 ; <i32> [#uses=1]
%tmp.upgrd.2 = icmp ugt i32 %tmp10, 2 ; <i1> [#uses=1] %tmp.upgrd.2 = icmp ugt i32 %tmp10, 2 ; <i1> [#uses=1]
%tmp14 = load i32, i32* null ; <i32> [#uses=1] %tmp14 = load i32, i32* null ; <i32> [#uses=1]
Show All 14 Lines

llvm/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll

; RUN: llc < %s -mtriple=x86_64-- > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep ",%rsp)" %t ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; PR1103 ; PR1103
target datalayout = "e-p:64:64" target datalayout = "e-p:64:64"
@i6000 = global [128 x i64] zeroinitializer, align 16 @i6000 = global [128 x i64] zeroinitializer, align 16
define void @foo(i32* %a0, i32* %a1, i32* %a2, i32* %a3, i32* %a4, i32* %a5) { define void @foo(i32* %a0, i32* %a1, i32* %a2, i32* %a3, i32* %a4, i32* %a5) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %b
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: movslq (%rdi), %rax
; CHECK-NEXT: movslq (%rsi), %r8
; CHECK-NEXT: movslq (%rdx), %r10
; CHECK-NEXT: movl (%rcx), %edi
; CHECK-NEXT: movslq (%r9), %rcx
; CHECK-NEXT: movq %rsp, %rdx
; CHECK-NEXT: subl %eax, %r8d
; CHECK-NEXT: movslq %r8d, %rsi
; CHECK-NEXT: js .LBB0_1
; CHECK-NEXT: # %bb.11: # %b63
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: js .LBB0_14
; CHECK-NEXT: # %bb.12:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_13: # %a25b
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB0_13
; CHECK-NEXT: .LBB0_14: # %b85
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.15:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_16: # %a25b140
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je .LBB0_16
; CHECK-NEXT: .LBB0_1: # %a29b
; CHECK-NEXT: cmpl %r10d, %edi
; CHECK-NEXT: js .LBB0_10
; CHECK-NEXT: # %bb.2: # %b158
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movb $1, %r10b
; CHECK-NEXT: jmp .LBB0_3
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_9: # %b1606
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_10
; CHECK-NEXT: .LBB0_3: # %a29b173
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_37 Depth 2
; CHECK-NEXT: # Child Loop BB0_19 Depth 2
; CHECK-NEXT: # Child Loop BB0_20 Depth 2
; CHECK-NEXT: # Child Loop BB0_21 Depth 3
; CHECK-NEXT: # Child Loop BB0_23 Depth 2
; CHECK-NEXT: # Child Loop BB0_24 Depth 3
; CHECK-NEXT: # Child Loop BB0_26 Depth 2
; CHECK-NEXT: # Child Loop BB0_38 Depth 3
; CHECK-NEXT: # Child Loop BB0_29 Depth 3
; CHECK-NEXT: # Child Loop BB0_30 Depth 2
; CHECK-NEXT: # Child Loop BB0_39 Depth 3
; CHECK-NEXT: # Child Loop BB0_33 Depth 3
; CHECK-NEXT: # Child Loop BB0_34 Depth 2
; CHECK-NEXT: # Child Loop BB0_36 Depth 2
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: js .LBB0_4
; CHECK-NEXT: # %bb.17: # %b179
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: js .LBB0_18
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_37: # %a30b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_37
; CHECK-NEXT: .LBB0_18: # %b188
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_19: # %a30b294
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_19
; CHECK-NEXT: .LBB0_4: # %a33b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: orl %r8d, %eax
; CHECK-NEXT: movl %eax, %r9d
; CHECK-NEXT: shrl $31, %r9d
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jns .LBB0_20
; CHECK-NEXT: .LBB0_5: # %a50b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: movl %r8d, %eax
; CHECK-NEXT: orl %ecx, %eax
; CHECK-NEXT: movl %eax, %r11d
; CHECK-NEXT: shrl $31, %r11d
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jns .LBB0_26
; CHECK-NEXT: .LBB0_6: # %a57b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testb %r9b, %r9b
; CHECK-NEXT: je .LBB0_30
; CHECK-NEXT: .LBB0_7: # %a66b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testb %r11b, %r11b
; CHECK-NEXT: jne .LBB0_8
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_34: # %a74b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: jne .LBB0_34
; CHECK-NEXT: # %bb.35: # %b1582
; CHECK-NEXT: # in Loop: Header=BB0_34 Depth=2
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: jne .LBB0_34
; CHECK-NEXT: .LBB0_8: # %a93b
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=1
; CHECK-NEXT: testl %r8d, %r8d
; CHECK-NEXT: js .LBB0_9
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_36: # %a97b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: addss %xmm0, %xmm1
; CHECK-NEXT: addss %xmm0, %xmm1
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: addss %xmm0, %xmm2
; CHECK-NEXT: addss %xmm1, %xmm2
; CHECK-NEXT: movss %xmm2, {{.*}}(%rip)
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: jne .LBB0_36
; CHECK-NEXT: jmp .LBB0_9
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_22: # %b463
; CHECK-NEXT: # in Loop: Header=BB0_20 Depth=2
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_23
; CHECK-NEXT: .LBB0_20: # %b341
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB0_21 Depth 3
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: js .LBB0_22
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_21: # %a35b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_20 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_21
; CHECK-NEXT: jmp .LBB0_22
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_28: # %b1016
; CHECK-NEXT: # in Loop: Header=BB0_26 Depth=2
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: jle .LBB0_6
; CHECK-NEXT: .LBB0_26: # %b858
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB0_38 Depth 3
; CHECK-NEXT: # Child Loop BB0_29 Depth 3
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: js .LBB0_27
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_38: # %a53b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_26 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_38
; CHECK-NEXT: .LBB0_27: # %b879
; CHECK-NEXT: # in Loop: Header=BB0_26 Depth=2
; CHECK-NEXT: testb %r10b, %r10b
; CHECK-NEXT: jne .LBB0_28
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_29: # %a53b1019
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_26 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: jle .LBB0_29
; CHECK-NEXT: jmp .LBB0_28
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_32: # %b1263
; CHECK-NEXT: # in Loop: Header=BB0_30 Depth=2
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: jle .LBB0_7
; CHECK-NEXT: .LBB0_30: # %b1117
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB0_39 Depth 3
; CHECK-NEXT: # Child Loop BB0_33 Depth 3
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: js .LBB0_31
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_39: # %a63b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_30 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: jle .LBB0_39
; CHECK-NEXT: .LBB0_31: # %b1139
; CHECK-NEXT: # in Loop: Header=BB0_30 Depth=2
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: jle .LBB0_32
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_33: # %a63b1266
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_30 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testq %rcx, %rcx
; CHECK-NEXT: jle .LBB0_33
; CHECK-NEXT: jmp .LBB0_32
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_25: # %b712
; CHECK-NEXT: # in Loop: Header=BB0_23 Depth=2
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_5
; CHECK-NEXT: .LBB0_23: # %b535
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB0_24 Depth 3
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: js .LBB0_25
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_24: # %a45b
; CHECK-NEXT: # Parent Loop BB0_3 Depth=1
; CHECK-NEXT: # Parent Loop BB0_23 Depth=2
; CHECK-NEXT: # => This Inner Loop Header: Depth=3
; CHECK-NEXT: testb %dil, %dil
; CHECK-NEXT: je .LBB0_24
; CHECK-NEXT: jmp .LBB0_25
; CHECK-NEXT: .LBB0_10: # %a109b
; CHECK-NEXT: movq %rbp, %rsp
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: .cfi_def_cfa %rsp, 8
; CHECK-NEXT: retq
b: b:
%r = load i32, i32* %a0 %r = load i32, i32* %a0
%r2 = load i32, i32* %a1 %r2 = load i32, i32* %a1
%r4 = load i32, i32* %a2 %r4 = load i32, i32* %a2
%r6 = load i32, i32* %a3 %r6 = load i32, i32* %a3
%r8 = load i32, i32* %a4 %r8 = load i32, i32* %a4
%r14 = load i32, i32* %a5 %r14 = load i32, i32* %a5
%rx = sext i32 %r2 to i64 %rx = sext i32 %r2 to i64
▲ Show 20 Lines • Show All 444 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2007-02-16-BranchFold.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -enable-tail-merge=0 | FileCheck %s
; PR 1200 ; PR 1200
; RUN: llc < %s -enable-tail-merge=0 | not grep jmp
; ModuleID = '<stdin>' ; ModuleID = '<stdin>'
target datalayout = "e-p:32:32" target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.Index_Map = type { i32, %struct.item_set** } %struct.Index_Map = type { i32, %struct.item_set** }
%struct.Item = type { [4 x i16], %struct.rule* } %struct.Item = type { [4 x i16], %struct.rule* }
%struct.__sFILEX = type opaque %struct.__sFILEX = type opaque
%struct.__sbuf = type { i8*, i32 } %struct.__sbuf = type { i8*, i32 }
Show All 10 Linestarget triple = "i686-apple-darwin8"
%struct.stateMap = type { i8*, %struct.plank*, i32, i16* } %struct.stateMap = type { i8*, %struct.plank*, i32, i16* }
%struct.table = type { %struct.operator*, %struct.list*, i16*, [2 x %struct.dimension*], %struct.item_set** } %struct.table = type { %struct.operator*, %struct.list*, i16*, [2 x %struct.dimension*], %struct.item_set** }
@outfile = external global %struct.FILE* ; <%struct.FILE**> [#uses=1] @outfile = external global %struct.FILE* ; <%struct.FILE**> [#uses=1]
@str1 = external global [11 x i8] ; <[11 x i8]*> [#uses=1] @str1 = external global [11 x i8] ; <[11 x i8]*> [#uses=1]
declare i32 @fprintf(%struct.FILE*, i8*, ...) declare i32 @fprintf(%struct.FILE*, i8*, ...)
define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(%struct.list* %l_addr.01.0.i2.i.i929, %struct.operator** %tmp66.i62.i.out) { define i16 @main_bb_2E_i9_2E_i_2E_i932_2E_ce(%struct.list* %l_addr.01.0.i2.i.i929, %struct.operator** %tmp66.i62.i.out) {
; CHECK-LABEL: main_bb_2E_i9_2E_i_2E_i932_2E_ce:
; CHECK: ## %bb.0: ## %newFuncRoot
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: subl $20, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset %esi, -12
; CHECK-NEXT: .cfi_offset %edi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %edi
; CHECK-NEXT: movl 8(%edi), %eax
; CHECK-NEXT: movl L_outfile$non_lazy_ptr, %ecx
; CHECK-NEXT: movl (%ecx), %ecx
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl L_str1$non_lazy_ptr, %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, (%esp)
; CHECK-NEXT: calll _fprintf
; CHECK-NEXT: movl 20(%edi), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jle LBB0_6
; CHECK-NEXT: ## %bb.1: ## %NodeBlock4
; CHECK-NEXT: cmpl $2, %eax
; CHECK-NEXT: jge LBB0_2
; CHECK-NEXT: ## %bb.4: ## %LeafBlock2
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: jne LBB0_3
; CHECK-NEXT: ## %bb.5: ## %bb20.i.i937.exitStub
; CHECK-NEXT: movl %edi, (%esi)
; CHECK-NEXT: movw $3, %ax
; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_6: ## %NodeBlock
; CHECK-NEXT: js LBB0_9
; CHECK-NEXT: ## %bb.7: ## %LeafBlock1
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jne LBB0_3
; CHECK-NEXT: ## %bb.8: ## %bb12.i.i935.exitStub
; CHECK-NEXT: movl %edi, (%esi)
; CHECK-NEXT: movw $2, %ax
; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_2: ## %LeafBlock3
; CHECK-NEXT: jne LBB0_3
; CHECK-NEXT: ## %bb.11: ## %bb28.i.i938.exitStub
; CHECK-NEXT: movl %edi, (%esi)
; CHECK-NEXT: movw $4, %ax
; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_9: ## %LeafBlock
; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: je LBB0_10
; CHECK-NEXT: LBB0_3: ## %NewDefault
; CHECK-NEXT: movl %edi, (%esi)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_10: ## %bb.i14.i.exitStub
; CHECK-NEXT: movl %edi, (%esi)
; CHECK-NEXT: movw $1, %ax
; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
newFuncRoot: newFuncRoot:
br label %bb.i9.i.i932.ce br label %bb.i9.i.i932.ce
NewDefault: ; preds = %LeafBlock, %LeafBlock1, %LeafBlock2, %LeafBlock3 NewDefault: ; preds = %LeafBlock, %LeafBlock1, %LeafBlock2, %LeafBlock3
br label %bb36.i.i.exitStub br label %bb36.i.i.exitStub
bb36.i.i.exitStub: ; preds = %NewDefault bb36.i.i.exitStub: ; preds = %NewDefault
store %struct.operator* %tmp66.i62.i, %struct.operator** %tmp66.i62.i.out store %struct.operator* %tmp66.i62.i, %struct.operator** %tmp66.i62.i.out
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2007-03-01-SpillerCrash.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | not grep movhlps ; RUN: llc < %s -mtriple=x86_64-apple-darwin8 -mattr=+sse2 | FileCheck %s
define void @test() nounwind { define void @test() nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %test.exit
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: ud2
test.exit: test.exit:
fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:0 [#uses=4] fmul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:0 [#uses=4]
load <4 x float>, <4 x float>* null ; <<4 x float>>:1 [#uses=1] load <4 x float>, <4 x float>* null ; <<4 x float>>:1 [#uses=1]
shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:2 [#uses=1] shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:2 [#uses=1]
fmul <4 x float> %0, %2 ; <<4 x float>>:3 [#uses=1] fmul <4 x float> %0, %2 ; <<4 x float>>:3 [#uses=1]
fsub <4 x float> zeroinitializer, %3 ; <<4 x float>>:4 [#uses=1] fsub <4 x float> zeroinitializer, %3 ; <<4 x float>>:4 [#uses=1]
fmul <4 x float> %4, zeroinitializer ; <<4 x float>>:5 [#uses=2] fmul <4 x float> %4, zeroinitializer ; <<4 x float>>:5 [#uses=2]
bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:6 [#uses=1] bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:6 [#uses=1]
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll

; RUN: llc < %s -no-integrated-as | grep "mov %gs:72, %eax" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -no-integrated-as | FileCheck %s
target datalayout = "e-p:32:32" target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9" target triple = "i686-apple-darwin9"
define void @test() { define void @test() {
; CHECK-LABEL: test:
; CHECK: ## %bb.0:
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: mov %gs:72, %eax
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: retl
%tmp1 = tail call i32* asm sideeffect "mov %gs:${1:P}, $0", "=r,i,~{dirflag},~{fpsr},~{flags}"( i32 72 ) ; <%struct._pthread*> [#uses=1] %tmp1 = tail call i32* asm sideeffect "mov %gs:${1:P}, $0", "=r,i,~{dirflag},~{fpsr},~{flags}"( i32 72 ) ; <%struct._pthread*> [#uses=1]
ret void ret void
} }

llvm/test/CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll

; RUN: llc < %s | not grep "bsrl.*10" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; PR1356 ; PR1356
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
define i32 @main() { define i32 @main() {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: bsrl LCPI0_0, %eax
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: retl
entry: entry:
%tmp4 = tail call i32 asm "bsrl $1, $0", "=r,ro,~{dirflag},~{fpsr},~{flags},~{cc}"( i32 10 ) ; <i32> [#uses=1] %tmp4 = tail call i32 asm "bsrl $1, $0", "=r,ro,~{dirflag},~{fpsr},~{flags},~{cc}"( i32 10 ) ; <i32> [#uses=1]
ret i32 %tmp4 ret i32 %tmp4
} }

llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep "movb %ah, %r" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, [4 x i8], i64 } %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, [4 x i8], i64 }
%struct.PyBoolScalarObject = type { i64, %struct._typeobject*, i8 } %struct.PyBoolScalarObject = type { i64, %struct._typeobject*, i8 }
%struct.PyBufferProcs = type { i64 (%struct.PyObject*, i64, i8**)*, i64 (%struct.PyObject*, i64, i8**)*, i64 (%struct.PyObject*, i64*)*, i64 (%struct.PyObject*, i64, i8**)* } %struct.PyBufferProcs = type { i64 (%struct.PyObject*, i64, i8**)*, i64 (%struct.PyObject*, i64, i8**)*, i64 (%struct.PyObject*, i64*)*, i64 (%struct.PyObject*, i64, i8**)* }
%struct.PyGetSetDef = type { i8*, %struct.PyObject* (%struct.PyObject*, i8*)*, i32 (%struct.PyObject*, %struct.PyObject*, i8*)*, i8*, i8* } %struct.PyGetSetDef = type { i8*, %struct.PyObject* (%struct.PyObject*, i8*)*, i32 (%struct.PyObject*, %struct.PyObject*, i8*)*, i8*, i8* }
%struct.PyMappingMethods = type { i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)* } %struct.PyMappingMethods = type { i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)* }
%struct.PyMemberDef = type opaque %struct.PyMemberDef = type opaque
%struct.PyMethodDef = type { i8*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32, i8* } %struct.PyMethodDef = type { i8*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32, i8* }
%struct.PyNumberMethods = type { %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, i32 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject**, %struct.PyObject**)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)* } %struct.PyNumberMethods = type { %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, i32 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject**, %struct.PyObject**)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)* }
%struct.PyObject = type { i64, %struct._typeobject* } %struct.PyObject = type { i64, %struct._typeobject* }
%struct.PySequenceMethods = type { i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, i64)*, %struct.PyObject* (%struct.PyObject*, i64)*, %struct.PyObject* (%struct.PyObject*, i64, i64)*, i32 (%struct.PyObject*, i64, %struct.PyObject*)*, i32 (%struct.PyObject*, i64, i64, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, i64)* } %struct.PySequenceMethods = type { i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, i64)*, %struct.PyObject* (%struct.PyObject*, i64)*, %struct.PyObject* (%struct.PyObject*, i64, i64)*, i32 (%struct.PyObject*, i64, %struct.PyObject*)*, i32 (%struct.PyObject*, i64, i64, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, i64)* }
%struct.PyTupleObject = type { i64, %struct._typeobject*, i64, [1 x %struct.PyObject*] } %struct.PyTupleObject = type { i64, %struct._typeobject*, i64, [1 x %struct.PyObject*] }
%struct.__sFILEX = type opaque %struct.__sFILEX = type opaque
%struct.__sbuf = type { i8*, i32 } %struct.__sbuf = type { i8*, i32 }
%struct._typeobject = type { i64, %struct._typeobject*, i64, i8*, i64, i64, void (%struct.PyObject*)*, i32 (%struct.PyObject*, %struct.FILE*, i32)*, %struct.PyObject* (%struct.PyObject*, i8*)*, i32 (%struct.PyObject*, i8*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyNumberMethods*, %struct.PySequenceMethods*, %struct.PyMappingMethods*, i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyBufferProcs*, i64, i8*, i32 (%struct.PyObject*, i32 (%struct.PyObject*, i8*)*, i8*)*, i32 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, i32)*, i64, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyMethodDef*, %struct.PyMemberDef*, %struct.PyGetSetDef*, %struct._typeobject*, %struct.PyObject*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, i64, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct._typeobject*, i64)*, %struct.PyObject* (%struct._typeobject*, %struct.PyObject*, %struct.PyObject*)*, void (i8*)*, i32 (%struct.PyObject*)*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, void (%struct.PyObject*)* } %struct._typeobject = type { i64, %struct._typeobject*, i64, i8*, i64, i64, void (%struct.PyObject*)*, i32 (%struct.PyObject*, %struct.FILE*, i32)*, %struct.PyObject* (%struct.PyObject*, i8*)*, i32 (%struct.PyObject*, i8*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyNumberMethods*, %struct.PySequenceMethods*, %struct.PyMappingMethods*, i64 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyBufferProcs*, i64, i8*, i32 (%struct.PyObject*, i32 (%struct.PyObject*, i8*)*, i8*)*, i32 (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, i32)*, i64, %struct.PyObject* (%struct.PyObject*)*, %struct.PyObject* (%struct.PyObject*)*, %struct.PyMethodDef*, %struct.PyMemberDef*, %struct.PyGetSetDef*, %struct._typeobject*, %struct.PyObject*, %struct.PyObject* (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, i64, i32 (%struct.PyObject*, %struct.PyObject*, %struct.PyObject*)*, %struct.PyObject* (%struct._typeobject*, i64)*, %struct.PyObject* (%struct._typeobject*, %struct.PyObject*, %struct.PyObject*)*, void (i8*)*, i32 (%struct.PyObject*)*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, %struct.PyObject*, void (%struct.PyObject*)* }
@PyArray_API = external global i8** ; <i8***> [#uses=4] @PyArray_API = external global i8** ; <i8***> [#uses=4]
@PyUFunc_API = external global i8** ; <i8***> [#uses=4] @PyUFunc_API = external global i8** ; <i8***> [#uses=4]
@.str5 = external constant [14 x i8] ; <[14 x i8]*> [#uses=1] @.str5 = external constant [14 x i8] ; <[14 x i8]*> [#uses=1]
define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %b) { define %struct.PyObject* @ubyte_divmod(%struct.PyObject* %a, %struct.PyObject* %b) {
; CHECK-LABEL: ubyte_divmod:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushq %r15
; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 40
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 80
; CHECK-NEXT: .cfi_offset %rbx, -40
; CHECK-NEXT: .cfi_offset %r14, -32
; CHECK-NEXT: .cfi_offset %r15, -24
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsi, %r14
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
; CHECK-NEXT: callq __ubyte_convert_to_ctype
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: js LBB0_4
; CHECK-NEXT: ## %bb.1: ## %cond_next.i
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
; CHECK-NEXT: movq %r14, %rdi
; CHECK-NEXT: callq __ubyte_convert_to_ctype
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: sarl $31, %ecx
; CHECK-NEXT: andl %eax, %ecx
; CHECK-NEXT: cmpl $-2, %ecx
; CHECK-NEXT: je LBB0_8
; CHECK-NEXT: ## %bb.2: ## %cond_next.i
; CHECK-NEXT: cmpl $-1, %ecx
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: LBB0_3: ## %bb4
; CHECK-NEXT: movq _PyArray_API@{{.*}}(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: movq 16(%rax), %rax
; CHECK-NEXT: jmp LBB0_10
; CHECK-NEXT: LBB0_4: ## %_ubyte_convert2_to_ctypes.exit
; CHECK-NEXT: cmpl $-2, %eax
; CHECK-NEXT: je LBB0_8
; CHECK-NEXT: ## %bb.5: ## %_ubyte_convert2_to_ctypes.exit
; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: LBB0_6: ## %bb35
; CHECK-NEXT: movq _PyUFunc_API@{{.*}}(%rip), %rbp
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: callq *216(%rax)
; CHECK-NEXT: movb {{[0-9]+}}(%rsp), %dl
; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: je LBB0_11
; CHECK-NEXT: ## %bb.7: ## %cond_false.i
; CHECK-NEXT: movb {{[0-9]+}}(%rsp), %bl
; CHECK-NEXT: movzbl %bl, %ecx
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: divb %dl
; CHECK-NEXT: movl %eax, %r14d
; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne LBB0_12
; CHECK-NEXT: jmp LBB0_14
; CHECK-NEXT: LBB0_8: ## %bb17
; CHECK-NEXT: callq _PyErr_Occurred
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: ## %bb.9: ## %cond_next
; CHECK-NEXT: movq _PyArray_API@{{.*}}(%rip), %rax
; CHECK-NEXT: movq (%rax), %rax
; CHECK-NEXT: movq 80(%rax), %rax
; CHECK-NEXT: LBB0_10: ## %bb4
; CHECK-NEXT: movq 96(%rax), %rax
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movq %r14, %rsi
; CHECK-NEXT: callq *40(%rax)
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_11: ## %cond_true.i
; CHECK-NEXT: movl $4, %edi
; CHECK-NEXT: callq _feraiseexcept
; CHECK-NEXT: movb {{[0-9]+}}(%rsp), %dl
; CHECK-NEXT: movb {{[0-9]+}}(%rsp), %bl
; CHECK-NEXT: xorl %r14d, %r14d
; CHECK-NEXT: testb %bl, %bl
; CHECK-NEXT: je LBB0_14
; CHECK-NEXT: LBB0_12: ## %cond_false.i
; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: je LBB0_14
; CHECK-NEXT: ## %bb.13: ## %cond_next17.i
; CHECK-NEXT: movzbl %bl, %eax
; CHECK-NEXT: divb %dl
; CHECK-NEXT: movzbl %ah, %eax
; CHECK-NEXT: movl %eax, %r15d
; CHECK-NEXT: jmp LBB0_18
; CHECK-NEXT: LBB0_14: ## %cond_true.i200
; CHECK-NEXT: testb %dl, %dl
; CHECK-NEXT: jne LBB0_17
; CHECK-NEXT: ## %bb.16: ## %cond_true14.i
; CHECK-NEXT: movl $4, %edi
; CHECK-NEXT: callq _feraiseexcept
; CHECK-NEXT: LBB0_17: ## %ubyte_ctype_remainder.exit
; CHECK-NEXT: xorl %r15d, %r15d
; CHECK-NEXT: LBB0_18: ## %ubyte_ctype_remainder.exit
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: callq *224(%rax)
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je LBB0_21
; CHECK-NEXT: ## %bb.19: ## %cond_true61
; CHECK-NEXT: movl %eax, %ebx
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: movq _.str5@{{.*}}(%rip), %rdi
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: callq *200(%rax)
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: js LBB0_27
; CHECK-NEXT: ## %bb.20: ## %cond_next73
; CHECK-NEXT: movl $1, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rsi
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edi
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: movl %ebx, %edx
; CHECK-NEXT: callq *232(%rax)
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: LBB0_21: ## %cond_next89
; CHECK-NEXT: movl $2, %edi
; CHECK-NEXT: callq _PyTuple_New
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.22: ## %cond_next97
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: movq _PyArray_API@{{.*}}(%rip), %rbp
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: movq 200(%rax), %rdi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: callq *304(%rdi)
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: je LBB0_25
; CHECK-NEXT: ## %bb.23: ## %cond_next135
; CHECK-NEXT: movb %r14b, 16(%rax)
; CHECK-NEXT: movq %rax, 24(%rbx)
; CHECK-NEXT: movq (%rbp), %rax
; CHECK-NEXT: movq 200(%rax), %rdi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: callq *304(%rdi)
; CHECK-NEXT: testq %rax, %rax
; CHECK-NEXT: je LBB0_25
; CHECK-NEXT: ## %bb.24: ## %cond_next182
; CHECK-NEXT: movb %r15b, 16(%rax)
; CHECK-NEXT: movq %rax, 32(%rbx)
; CHECK-NEXT: movq %rbx, %rax
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_25: ## %cond_true113
; CHECK-NEXT: decq (%rbx)
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: ## %bb.26: ## %cond_true126
; CHECK-NEXT: movq 8(%rbx), %rax
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: callq *48(%rax)
; CHECK-NEXT: LBB0_27: ## %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: LBB0_28: ## %UnifiedReturnBlock
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
entry: entry:
%arg1 = alloca i8, align 1 ; <i8*> [#uses=3] %arg1 = alloca i8, align 1 ; <i8*> [#uses=3]
%arg2 = alloca i8, align 1 ; <i8*> [#uses=3] %arg2 = alloca i8, align 1 ; <i8*> [#uses=3]
%first = alloca i32, align 4 ; <i32*> [#uses=2] %first = alloca i32, align 4 ; <i32*> [#uses=2]
%bufsize = alloca i32, align 4 ; <i32*> [#uses=1] %bufsize = alloca i32, align 4 ; <i32*> [#uses=1]
%errmask = alloca i32, align 4 ; <i32*> [#uses=2] %errmask = alloca i32, align 4 ; <i32*> [#uses=2]
%errobj = alloca %struct.PyObject*, align 8 ; <%struct.PyObject**> [#uses=2] %errobj = alloca %struct.PyObject*, align 8 ; <%struct.PyObject**> [#uses=2]
%tmp3.i = call fastcc i32 @_ubyte_convert_to_ctype( %struct.PyObject* %a, i8* %arg1 ) ; <i32> [#uses=2] %tmp3.i = call fastcc i32 @_ubyte_convert_to_ctype( %struct.PyObject* %a, i8* %arg1 ) ; <i32> [#uses=2]
▲ Show 20 Lines • Show All 206 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll

; RUN: llc < %s -mtriple=i686-- | grep "movsbl" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
@X = global i32 0 ; <i32*> [#uses=1] @X = global i32 0 ; <i32*> [#uses=1]
define i32 @_Z3fooi(i32 %x) { define i32 @_Z3fooi(i32 %x) {
; CHECK-LABEL: _Z3fooi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, X
; CHECK-NEXT: movsbl %al, %eax
; CHECK-NEXT: retl
entry: entry:
store i32 %x, i32* @X, align 4 store i32 %x, i32* @X, align 4
%retval67 = trunc i32 %x to i8 ; <i8> [#uses=1] %retval67 = trunc i32 %x to i8 ; <i8> [#uses=1]
%retval = sext i8 %retval67 to i32 %retval = sext i8 %retval67 to i32
ret i32 %retval ret i32 %retval
} }

llvm/test/CodeGen/X86/2007-10-04-AvoidEFLAGSCopy.ll

; RUN: llc < %s -mtriple=i686-- | not grep pushf ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
%struct.gl_texture_image = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8* } %struct.gl_texture_image = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8* }
%struct.gl_texture_object = type { i32, i32, i32, float, [4 x i32], i32, i32, i32, i32, i32, float, [11 x %struct.gl_texture_image*], [1024 x i8], i32, i32, i32, i8, i8*, i8, void (%struct.gl_texture_object*, i32, float*, float*, float*, float*, i8*, i8*, i8*, i8*)*, %struct.gl_texture_object* } %struct.gl_texture_object = type { i32, i32, i32, float, [4 x i32], i32, i32, i32, i32, i32, float, [11 x %struct.gl_texture_image*], [1024 x i8], i32, i32, i32, i8, i8*, i8, void (%struct.gl_texture_object*, i32, float*, float*, float*, float*, i8*, i8*, i8*, i8*)*, %struct.gl_texture_object* }
define fastcc void @sample_3d_linear(%struct.gl_texture_object* %tObj, %struct.gl_texture_image* %img, float %s, float %t, float %r, i8* %red, i8* %green, i8* %blue, i8* %alpha) { define fastcc void @sample_3d_linear(%struct.gl_texture_object* %tObj, %struct.gl_texture_image* %img, float %s, float %t, float %r, i8* %red, i8* %green, i8* %blue, i8* %alpha) {
; CHECK-LABEL: sample_3d_linear:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl 0, %esi
; CHECK-NEXT: pushl $0
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: calll floorf
; CHECK-NEXT: fstp %st(0)
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: cmpl $10497, %esi # imm = 0x2901
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry: entry:
%tmp15 = load i32, i32* null, align 4 ; <i32> [#uses=1] %tmp15 = load i32, i32* null, align 4 ; <i32> [#uses=1]
%tmp16 = icmp eq i32 %tmp15, 10497 ; <i1> [#uses=1] %tmp16 = icmp eq i32 %tmp15, 10497 ; <i1> [#uses=1]
%tmp2152 = call float @floorf( float 0.000000e+00 ) ; <float> [#uses=0] %tmp2152 = call float @floorf( float 0.000000e+00 ) ; <float> [#uses=0]
br i1 %tmp16, label %cond_true, label %cond_false br i1 %tmp16, label %cond_true, label %cond_false
cond_true: ; preds = %entry cond_true: ; preds = %entry
ret void ret void
cond_false: ; preds = %entry cond_false: ; preds = %entry
ret void ret void
} }
declare float @floorf(float) declare float @floorf(float)

llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll

; RUN: llc < %s -mtriple=i686-- | not grep movb ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define signext i16 @f(i32* %bp, i32* %ss) { define signext i16 @f(i32* %bp, i32* %ss) {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %cond_next127
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl (%eax), %edx
; CHECK-NEXT: movl (%ecx), %esi
; CHECK-NEXT: andl $15, %edx
; CHECK-NEXT: andl $15, %esi
; CHECK-NEXT: addl %esi, (%ecx)
; CHECK-NEXT: cmpl $63, %edx
; CHECK-NEXT: jb .LBB0_1
; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry: entry:
br label %cond_next127 br label %cond_next127
cond_next127: ; preds = %cond_next391, %entry cond_next127: ; preds = %cond_next391, %entry
%v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ] ; <i32> [#uses=1] %v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ] ; <i32> [#uses=1]
%tmp149 = mul i32 0, %v.1 ; <i32> [#uses=0] %tmp149 = mul i32 0, %v.1 ; <i32> [#uses=0]
%tmpss = load i32, i32* %ss, align 4 ; <i32> [#uses=1] %tmpss = load i32, i32* %ss, align 4 ; <i32> [#uses=1]
%tmpbp = load i32, i32* %bp, align 4 ; <i32> [#uses=2] %tmpbp = load i32, i32* %bp, align 4 ; <i32> [#uses=2]
Show All 23 Lines

llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | grep addss | not grep esp ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
define fastcc void @fht(float* %fz, i16 signext %n) { define fastcc void @fht(float* %fz, i16 signext %n) {
; CHECK-LABEL: fht:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: xorps %xmm2, %xmm2
; CHECK-NEXT: subss %xmm1, %xmm2
; CHECK-NEXT: movaps %xmm1, %xmm3
; CHECK-NEXT: mulss %xmm0, %xmm3
; CHECK-NEXT: addss %xmm1, %xmm3
; CHECK-NEXT: movaps %xmm1, %xmm4
; CHECK-NEXT: subss %xmm3, %xmm4
; CHECK-NEXT: addss %xmm1, %xmm3
; CHECK-NEXT: xorps %xmm5, %xmm5
; CHECK-NEXT: subss %xmm2, %xmm5
; CHECK-NEXT: addss %xmm0, %xmm2
; CHECK-NEXT: mulss %xmm0, %xmm3
; CHECK-NEXT: mulss %xmm0, %xmm5
; CHECK-NEXT: addss %xmm3, %xmm5
; CHECK-NEXT: addss %xmm0, %xmm5
; CHECK-NEXT: movss %xmm5, 0
; CHECK-NEXT: movss %xmm1, (%ecx)
; CHECK-NEXT: addss %xmm0, %xmm1
; CHECK-NEXT: movss %xmm1, 0
; CHECK-NEXT: mulss %xmm0, %xmm2
; CHECK-NEXT: mulss %xmm0, %xmm4
; CHECK-NEXT: addss %xmm2, %xmm4
; CHECK-NEXT: addss %xmm0, %xmm4
; CHECK-NEXT: movss %xmm4, (%ecx)
; CHECK-NEXT: retl
entry: entry:
br i1 true, label %bb171.preheader, label %bb431 br i1 true, label %bb171.preheader, label %bb431
bb171.preheader: ; preds = %entry bb171.preheader: ; preds = %entry
%tmp176 = fadd float 0.000000e+00, 1.000000e+00 ; <float> [#uses=2] %tmp176 = fadd float 0.000000e+00, 1.000000e+00 ; <float> [#uses=2]
%gi.1 = getelementptr float, float* %fz, i32 0 ; <float*> [#uses=2] %gi.1 = getelementptr float, float* %fz, i32 0 ; <float*> [#uses=2]
%tmp240 = load float, float* %gi.1, align 4 ; <float> [#uses=1] %tmp240 = load float, float* %gi.1, align 4 ; <float> [#uses=1]
%tmp242 = fsub float %tmp240, 0.000000e+00 ; <float> [#uses=2] %tmp242 = fsub float %tmp240, 0.000000e+00 ; <float> [#uses=2]
Show All 34 Lines

llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | grep sarl | not grep esp ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s
define signext i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) { define signext i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) {
; CHECK-LABEL: t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %cond_next127
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: sarl %cl, %edx
; CHECK-NEXT: incl %edx
; CHECK-NEXT: cmpl $63, %edx
; CHECK-NEXT: jb .LBB0_1
; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
entry: entry:
br label %cond_next127 br label %cond_next127
cond_next127: ; preds = %cond_next391, %entry cond_next127: ; preds = %cond_next391, %entry
%tmp151 = add i32 0, %round ; <i32> [#uses=1] %tmp151 = add i32 0, %round ; <i32> [#uses=1]
%tmp153 = ashr i32 %tmp151, %scale ; <i32> [#uses=1] %tmp153 = ashr i32 %tmp151, %scale ; <i32> [#uses=1]
%tmp158 = xor i32 0, %tmp153 ; <i32> [#uses=1] %tmp158 = xor i32 0, %tmp153 ; <i32> [#uses=1]
%tmp160 = or i32 %tmp158, 0 ; <i32> [#uses=1] %tmp160 = or i32 %tmp158, 0 ; <i32> [#uses=1]
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll

; RUN: llc < %s -mtriple=i686-- | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define signext i16 @t() { define signext i16 @t() {
; CHECK-LABEL: t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movswl 0, %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
entry: entry:
%tmp180 = load i16, i16* null, align 2 ; <i16> [#uses=3] %tmp180 = load i16, i16* null, align 2 ; <i16> [#uses=3]
%tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1] %tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1]
%tmp185 = icmp slt i16 %tmp180, 0 ; <i1> [#uses=1] %tmp185 = icmp slt i16 %tmp180, 0 ; <i1> [#uses=1]
br i1 %tmp185, label %cond_true188, label %cond_next245 br i1 %tmp185, label %cond_true188, label %cond_next245
cond_true188: ; preds = %entry cond_true188: ; preds = %entry
%tmp195196 = trunc i16 %tmp180 to i8 ; <i8> [#uses=0] %tmp195196 = trunc i16 %tmp180 to i8 ; <i8> [#uses=0]
ret i16 0 ret i16 0
cond_next245: ; preds = %entry cond_next245: ; preds = %entry
%tmp256 = and i32 %tmp180181, 15 ; <i32> [#uses=0] %tmp256 = and i32 %tmp180181, 15 ; <i32> [#uses=0]
ret i16 0 ret i16 0
} }

llvm/test/CodeGen/X86/2007-11-06-InstrSched.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=generic -mattr=+sse2 | not grep lea ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=generic -mattr=+sse2 | FileCheck %s
define float @foo(i32* %x, float* %y, i32 %c) nounwind { define float @foo(i32* %x, float* %y, i32 %c) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb18.preheader
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_3: # %bb18
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: cvtsi2ssl (%edx,%esi,4), %xmm1
; CHECK-NEXT: mulss (%ecx,%esi,4), %xmm1
; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: incl %esi
; CHECK-NEXT: cmpl %eax, %esi
; CHECK-NEXT: jb .LBB0_3
; CHECK-NEXT: jmp .LBB0_4
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: .LBB0_4: # %bb23
; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp)
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%tmp2132 = icmp eq i32 %c, 0 ; <i1> [#uses=1] %tmp2132 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
br i1 %tmp2132, label %bb23, label %bb18 br i1 %tmp2132, label %bb23, label %bb18
bb18: ; preds = %bb18, %entry bb18: ; preds = %bb18, %entry
%i.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %tmp17, %bb18 ] ; <i32> [#uses=3] %i.0.reg2mem.0 = phi i32 [ 0, %entry ], [ %tmp17, %bb18 ] ; <i32> [#uses=3]
%res.0.reg2mem.0 = phi float [ 0.000000e+00, %entry ], [ %tmp14, %bb18 ] ; <float> [#uses=1] %res.0.reg2mem.0 = phi float [ 0.000000e+00, %entry ], [ %tmp14, %bb18 ] ; <float> [#uses=1]
%tmp3 = getelementptr i32, i32* %x, i32 %i.0.reg2mem.0 ; <i32*> [#uses=1] %tmp3 = getelementptr i32, i32* %x, i32 %i.0.reg2mem.0 ; <i32*> [#uses=1]
Show All 14 Lines

llvm/test/CodeGen/X86/2007-11-07-MulBy4.ll

; RUN: llc < %s -mtriple=i686-- | not grep imul ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
%struct.eebb = type { %struct.eebb*, i16* } %struct.eebb = type { %struct.eebb*, i16* }
%struct.hf = type { %struct.hf*, i16*, i8*, i32, i32, %struct.eebb*, i32, i32, i8*, i8*, i8*, i8*, i16*, i8*, i16*, %struct.ri, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [30 x i32], %struct.eebb, i32, i8* } %struct.hf = type { %struct.hf*, i16*, i8*, i32, i32, %struct.eebb*, i32, i32, i8*, i8*, i8*, i8*, i16*, i8*, i16*, %struct.ri, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [30 x i32], %struct.eebb, i32, i8* }
%struct.foo_data = type { i32, i32, i32, i32*, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i16*, i16*, i16*, i16*, i32, i32, i32, %struct.ri*, i8*, %struct.hf* } %struct.foo_data = type { i32, i32, i32, i32*, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i16*, i16*, i16*, i16*, i32, i32, i32, %struct.ri*, i8*, %struct.hf* }
%struct.ri = type { %struct.ri*, i32, i8*, i16*, i32*, i32 } %struct.ri = type { %struct.ri*, i32, i8*, i16*, i32*, i32 }
define fastcc i32 @foo(i16* %eptr, i8* %ecode, %struct.foo_data* %md, i32 %ims) { define fastcc i32 @foo(i16* %eptr, i8* %ecode, %struct.foo_data* %md, i32 %ims) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $0, 0
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.1: # %cond_next79
; CHECK-NEXT: cmpl $0, 0
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.2: # %cond_next130
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: .LBB0_3: # %cond_true89
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
entry: entry:
%tmp36 = load i32, i32* null, align 4 ; <i32> [#uses=1] %tmp36 = load i32, i32* null, align 4 ; <i32> [#uses=1]
%tmp37 = icmp ult i32 0, %tmp36 ; <i1> [#uses=1] %tmp37 = icmp ult i32 0, %tmp36 ; <i1> [#uses=1]
br i1 %tmp37, label %cond_next79, label %cond_true br i1 %tmp37, label %cond_next79, label %cond_true
cond_true: ; preds = %entry cond_true: ; preds = %entry
ret i32 0 ret i32 0
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2007-12-18-LoadCSEBug.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=generic | grep "(%esp)" | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=generic | FileCheck %s
; PR1872 ; PR1872
%struct.c34007g__designated___XUB = type { i32, i32, i32, i32 } %struct.c34007g__designated___XUB = type { i32, i32, i32, i32 }
%struct.c34007g__pkg__parent = type { i32*, %struct.c34007g__designated___XUB* } %struct.c34007g__pkg__parent = type { i32*, %struct.c34007g__designated___XUB* }
define void @_ada_c34007g() { define void @_ada_c34007g() {
; CHECK-LABEL: _ada_c34007g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl (%esp), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: orl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: # %bb.2: # %entry
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: .LBB0_3: # %bb5507
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl
entry: entry:
%x8 = alloca %struct.c34007g__pkg__parent, align 8 ; <%struct.c34007g__pkg__parent*> [#uses=2] %x8 = alloca %struct.c34007g__pkg__parent, align 8 ; <%struct.c34007g__pkg__parent*> [#uses=2]
%tmp1272 = getelementptr %struct.c34007g__pkg__parent, %struct.c34007g__pkg__parent* %x8, i32 0, i32 0 ; <i32**> [#uses=1] %tmp1272 = getelementptr %struct.c34007g__pkg__parent, %struct.c34007g__pkg__parent* %x8, i32 0, i32 0 ; <i32**> [#uses=1]
%x82167 = bitcast %struct.c34007g__pkg__parent* %x8 to i64* ; <i64*> [#uses=1] %x82167 = bitcast %struct.c34007g__pkg__parent* %x8 to i64* ; <i64*> [#uses=1]
br i1 true, label %bb4668, label %bb848 br i1 true, label %bb4668, label %bb848
bb4668: ; preds = %bb4648 bb4668: ; preds = %bb4648
%tmp5464 = load i64, i64* %x82167, align 8 ; <i64> [#uses=1] %tmp5464 = load i64, i64* %x82167, align 8 ; <i64> [#uses=1]
Show All 13 Lines

llvm/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll

; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 -mtriple=i686-- -mattr=+mmx | grep esi ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 -mtriple=i686-- -mattr=+mmx | FileCheck %s
; PR2082 ; PR2082
; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of ; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of
; registers. ; registers.
define void @transpose4x4(i8* %dst, i8* %src, i32 %dst_stride, i32 %src_stride) { define void @transpose4x4(i8* %dst, i8* %src, i32 %dst_stride, i32 %src_stride) {
; CHECK-LABEL: transpose4x4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %esi, -16
; CHECK-NEXT: .cfi_offset %edi, -12
; CHECK-NEXT: .cfi_offset %ebx, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: leal (%ecx,%ecx,2), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: leal (%edi,%edi,2), %ebx
; CHECK-NEXT: #APP
; CHECK-NEXT: movd (%esi), %mm0
; CHECK-NEXT: movd (%esi,%edi), %mm1
; CHECK-NEXT: movd (%esi,%edi,2), %mm2
; CHECK-NEXT: movd (%esi,%ebx), %mm3
; CHECK-NEXT: punpcklbw %mm1, %mm0 # mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3]
; CHECK-NEXT: punpcklbw %mm3, %mm2 # mm2 = mm2[0],mm3[0],mm2[1],mm3[1],mm2[2],mm3[2],mm2[3],mm3[3]
; CHECK-NEXT: movq %mm0, %mm1
; CHECK-NEXT: punpcklwd %mm2, %mm0 # mm0 = mm0[0],mm2[0],mm0[1],mm2[1]
; CHECK-NEXT: punpckhwd %mm2, %mm1 # mm1 = mm1[2],mm2[2],mm1[3],mm2[3]
; CHECK-NEXT: movd %mm0, (%eax)
; CHECK-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
; CHECK-NEXT: movd %mm0, (%eax,%ecx)
; CHECK-NEXT: movd %mm1, (%eax,%ecx,2)
; CHECK-NEXT: punpckhdq %mm1, %mm1 # mm1 = mm1[1,1]
; CHECK-NEXT: movd %mm1, (%eax,%edx)
; CHECK-EMPTY:
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: popl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry: entry:
%dst_addr = alloca i8* ; <i8**> [#uses=5] %dst_addr = alloca i8* ; <i8**> [#uses=5]
%src_addr = alloca i8* ; <i8**> [#uses=5] %src_addr = alloca i8* ; <i8**> [#uses=5]
%dst_stride_addr = alloca i32 ; <i32*> [#uses=4] %dst_stride_addr = alloca i32 ; <i32*> [#uses=4]
%src_stride_addr = alloca i32 ; <i32*> [#uses=4] %src_stride_addr = alloca i32 ; <i32*> [#uses=4]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
store i8* %dst, i8** %dst_addr store i8* %dst, i8** %dst_addr
store i8* %src, i8** %src_addr store i8* %src, i8** %src_addr
Show All 28 Linesentry:
%tmp27 = load i8*, i8** %src_addr, align 4 ; <i8*> [#uses=1] %tmp27 = load i8*, i8** %src_addr, align 4 ; <i8*> [#uses=1]
%tmp28 = getelementptr i8, i8* %tmp27, i32 %tmp26 ; <i8*> [#uses=1] %tmp28 = getelementptr i8, i8* %tmp27, i32 %tmp26 ; <i8*> [#uses=1]
%tmp2829 = bitcast i8* %tmp28 to i32* ; <i32*> [#uses=1] %tmp2829 = bitcast i8* %tmp28 to i32* ; <i32*> [#uses=1]
%tmp30 = load i32, i32* %src_stride_addr, align 4 ; <i32> [#uses=1] %tmp30 = load i32, i32* %src_stride_addr, align 4 ; <i32> [#uses=1]
%tmp31 = mul i32 %tmp30, 3 ; <i32> [#uses=1] %tmp31 = mul i32 %tmp30, 3 ; <i32> [#uses=1]
%tmp32 = load i8*, i8** %src_addr, align 4 ; <i8*> [#uses=1] %tmp32 = load i8*, i8** %src_addr, align 4 ; <i8*> [#uses=1]
%tmp33 = getelementptr i8, i8* %tmp32, i32 %tmp31 ; <i8*> [#uses=1] %tmp33 = getelementptr i8, i8* %tmp32, i32 %tmp31 ; <i8*> [#uses=1]
%tmp3334 = bitcast i8* %tmp33 to i32* ; <i32*> [#uses=1] %tmp3334 = bitcast i8* %tmp33 to i32* ; <i32*> [#uses=1]
call void asm sideeffect "movd $4, %mm0 \0A\09movd $5, %mm1 \0A\09movd $6, %mm2 \0A\09movd $7, %mm3 \0A\09punpcklbw %mm1, %mm0 \0A\09punpcklbw %mm3, %mm2 \0A\09movq %mm0, %mm1 \0A\09punpcklwd %mm2, %mm0 \0A\09punpckhwd %mm2, %mm1 \0A\09movd %mm0, $0 \0A\09punpckhdq %mm0, %mm0 \0A\09movd %mm0, $1 \0A\09movd %mm1, $2 \0A\09punpckhdq %mm1, %mm1 \0A\09movd %mm1, $3 \0A\09", "=*m,=*m,=*m,=*m,*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"( i32* %tmp12, i32* %tmp56, i32* %tmp1011, i32* %tmp1617, i32* %tmp1920, i32* %tmp2324, i32* %tmp2829, i32* %tmp3334 ) nounwind call void asm sideeffect "movd $4, %mm0 \0A\09movd $5, %mm1 \0A\09movd $6, %mm2 \0A\09movd $7, %mm3 \0A\09punpcklbw %mm1, %mm0 \0A\09punpcklbw %mm3, %mm2 \0A\09movq %mm0, %mm1 \0A\09punpcklwd %mm2, %mm0 \0A\09punpckhwd %mm2, %mm1 \0A\09movd %mm0, $0 \0A\09punpckhdq %mm0, %mm0 \0A\09movd %mm0, $1 \0A\09movd %mm1, $2 \0A\09punpckhdq %mm1, %mm1 \0A\09movd %mm1, $3 \0A\09", "=*m,=*m,=*m,=*m,*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"( i32* %tmp12, i32* %tmp56, i32* %tmp1011, i32* %tmp1617, i32* %tmp1920, i32* %tmp2324, i32* %tmp2829, i32* %tmp3334 ) nounwind
br label %return br label %return
return: ; preds = %entry return: ; preds = %entry
ret void ret void
} }

llvm/test/CodeGen/X86/2008-03-07-APIntBug.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=i386 | not grep 255 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=i386 | FileCheck %s
%struct.CONSTRAINT = type { i32, i32, i32, i32 } %struct.CONSTRAINT = type { i32, i32, i32, i32 }
%struct.FIRST_UNION = type { %struct.anon } %struct.FIRST_UNION = type { %struct.anon }
%struct.FOURTH_UNION = type { %struct.CONSTRAINT } %struct.FOURTH_UNION = type { %struct.CONSTRAINT }
%struct.LIST = type { %struct.rec*, %struct.rec* } %struct.LIST = type { %struct.rec*, %struct.rec* }
%struct.SECOND_UNION = type { { i16, i8, i8 } } %struct.SECOND_UNION = type { { i16, i8, i8 } }
%struct.THIRD_UNION = type { { [2 x i32], [2 x i32] } } %struct.THIRD_UNION = type { { [2 x i32], [2 x i32] } }
%struct.anon = type { i8, i8, i32 } %struct.anon = type { i8, i8, i32 }
%struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 } %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
%struct.rec = type { %struct.head_type } %struct.rec = type { %struct.head_type }
%struct.symbol_type = type <{ [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i16, i16, i8, i8, i8, i8 }> %struct.symbol_type = type <{ [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i16, i16, i8, i8, i8, i8 }>
%struct.word_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, [4 x i8] } %struct.word_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, [4 x i8] }
define void @InsertSym_bb1163(%struct.rec** %s) { define void @InsertSym_bb1163(%struct.rec** %s) {
; CHECK-LABEL: InsertSym_bb1163:
; CHECK: # %bb.0: # %newFuncRoot
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl (%eax), %ecx
; CHECK-NEXT: movl 28(%ecx), %ecx
; CHECK-NEXT: orb $-128, 26(%ecx)
; CHECK-NEXT: orb $2, 25(%ecx)
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: orb $1, 25(%eax)
; CHECK-NEXT: retl
newFuncRoot: newFuncRoot:
br label %bb1163 br label %bb1163
bb1233.exitStub: ; preds = %bb1163 bb1233.exitStub: ; preds = %bb1163
ret void ret void
bb1163: ; preds = %newFuncRoot bb1163: ; preds = %newFuncRoot
%tmp1164 = load %struct.rec*, %struct.rec** %s, align 4 ; <%struct.rec*> [#uses=1] %tmp1164 = load %struct.rec*, %struct.rec** %s, align 4 ; <%struct.rec*> [#uses=1]
%tmp1165 = getelementptr %struct.rec, %struct.rec* %tmp1164, i32 0, i32 0 ; <%struct.head_type*> [#uses=1] %tmp1165 = getelementptr %struct.rec, %struct.rec* %tmp1164, i32 0, i32 0 ; <%struct.head_type*> [#uses=1]
%tmp11651166 = bitcast %struct.head_type* %tmp1165 to %struct.symbol_type* ; <%struct.symbol_type*> [#uses=1] %tmp11651166 = bitcast %struct.head_type* %tmp1165 to %struct.symbol_type* ; <%struct.symbol_type*> [#uses=1]
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll

; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -frame-pointer=all | grep add | grep 12 | not grep non_lazy_ptr ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -frame-pointer=all | FileCheck %s
; Don't fold re-materialized load into a two address instruction ; Don't fold re-materialized load into a two address instruction
%"struct.Smarts::Runnable" = type { i32 (...)**, i32 } %"struct.Smarts::Runnable" = type { i32 (...)**, i32 }
%struct.__sbuf = type { i8*, i32 } %struct.__sbuf = type { i8*, i32 }
%"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %struct.__sbuf, [8 x %struct.__sbuf], i32, %struct.__sbuf*, %"struct.std::locale" } %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %struct.__sbuf, [8 x %struct.__sbuf], i32, %struct.__sbuf*, %"struct.std::locale" }
%"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 } %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 }
%"struct.std::locale" = type { %"struct.std::locale::_Impl"* } %"struct.std::locale" = type { %"struct.std::locale::_Impl"* }
%"struct.std::locale::_Impl" = type { i32, %"struct.Smarts::Runnable"**, i32, %"struct.Smarts::Runnable"**, i8** } %"struct.std::locale::_Impl" = type { i32, %"struct.Smarts::Runnable"**, i32, %"struct.Smarts::Runnable"**, i8** }
@_ZTVSt9basic_iosIcSt11char_traitsIcEE = external constant [4 x i32 (...)*] ; <[4 x i32 (...)*]*> [#uses=1] @_ZTVSt9basic_iosIcSt11char_traitsIcEE = external constant [4 x i32 (...)*] ; <[4 x i32 (...)*]*> [#uses=1]
@_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE = external constant [4 x i8*] ; <[4 x i8*]*> [#uses=1] @_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE = external constant [4 x i8*] ; <[4 x i8*]*> [#uses=1]
@_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE = external constant [10 x i32 (...)*] ; <[10 x i32 (...)*]*> [#uses=2] @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE = external constant [10 x i32 (...)*] ; <[10 x i32 (...)*]*> [#uses=2]
@_ZTVSt15basic_streambufIcSt11char_traitsIcEE = external constant [16 x i32 (...)*] ; <[16 x i32 (...)*]*> [#uses=1] @_ZTVSt15basic_streambufIcSt11char_traitsIcEE = external constant [16 x i32 (...)*] ; <[16 x i32 (...)*]*> [#uses=1]
@_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE = external constant [16 x i32 (...)*] ; <[16 x i32 (...)*]*> [#uses=1] @_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE = external constant [16 x i32 (...)*] ; <[16 x i32 (...)*]*> [#uses=1]
define void @_GLOBAL__I__ZN5Pooma5pinfoE() nounwind { define void @_GLOBAL__I__ZN5Pooma5pinfoE() nounwind {
; CHECK-LABEL: _GLOBAL__I__ZN5Pooma5pinfoE:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: calll L0$pb
; CHECK-NEXT: L0$pb:
; CHECK-NEXT: popl %edi
; CHECK-NEXT: movl L__ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE$non_lazy_ptr-L0$pb(%edi), %ebx
; CHECK-NEXT: leal 32(%ebx), %eax
; CHECK-NEXT: movl %eax, 0
; CHECK-NEXT: movl $180, (%esp)
; CHECK-NEXT: calll __Znwm
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZNSt8ios_baseC2Ev
; CHECK-NEXT: movl $0, 0
; CHECK-NEXT: addl $12, %ebx
; CHECK-NEXT: movl %ebx, (%esi)
; CHECK-NEXT: movl L__ZTVSt15basic_streambufIcSt11char_traitsIcEE$non_lazy_ptr-L0$pb(%edi), %eax
; CHECK-NEXT: addl $8, %eax
; CHECK-NEXT: movl %eax, 0
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZNSt6localeC1Ev
; CHECK-NEXT: movl L__ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE$non_lazy_ptr-L0$pb(%edi), %eax
; CHECK-NEXT: addl $8, %eax
; CHECK-NEXT: movl %eax, 0
; CHECK-NEXT: ud2
entry: entry:
store i32 (...)** getelementptr ([10 x i32 (...)*], [10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 8), i32 (...)*** null, align 4 store i32 (...)** getelementptr ([10 x i32 (...)*], [10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 8), i32 (...)*** null, align 4
%tmp96.i.i142.i = call i8* @_Znwm( i32 180 ) nounwind ; <i8*> [#uses=2] %tmp96.i.i142.i = call i8* @_Znwm( i32 180 ) nounwind ; <i8*> [#uses=2]
call void @_ZNSt8ios_baseC2Ev( %"struct.std::ios_base"* null ) nounwind call void @_ZNSt8ios_baseC2Ev( %"struct.std::ios_base"* null ) nounwind
store i32 (...)** getelementptr ([4 x i32 (...)*], [4 x i32 (...)*]* @_ZTVSt9basic_iosIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4 store i32 (...)** getelementptr ([4 x i32 (...)*], [4 x i32 (...)*]* @_ZTVSt9basic_iosIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
store i32 (...)** null, i32 (...)*** null, align 4 store i32 (...)** null, i32 (...)*** null, align 4
%ctg2242.i.i163.i = getelementptr i8, i8* %tmp96.i.i142.i, i32 0 ; <i8*> [#uses=1] %ctg2242.i.i163.i = getelementptr i8, i8* %tmp96.i.i142.i, i32 0 ; <i8*> [#uses=1]
%tmp150.i.i164.i = load i8*, i8** getelementptr ([4 x i8*], [4 x i8*]* @_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i64 2), align 4 ; <i8*> [#uses=1] %tmp150.i.i164.i = load i8*, i8** getelementptr ([4 x i8*], [4 x i8*]* @_ZTTSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i64 2), align 4 ; <i8*> [#uses=1]
%tmp150151.i.i165.i = bitcast i8* %tmp150.i.i164.i to i32 (...)** ; <i32 (...)**> [#uses=1] %tmp150151.i.i165.i = bitcast i8* %tmp150.i.i164.i to i32 (...)** ; <i32 (...)**> [#uses=1]
%tmp153.i.i166.i = bitcast i8* %ctg2242.i.i163.i to i32 (...)*** ; <i32 (...)***> [#uses=1] %tmp153.i.i166.i = bitcast i8* %ctg2242.i.i163.i to i32 (...)*** ; <i32 (...)***> [#uses=1]
store i32 (...)** %tmp150151.i.i165.i, i32 (...)*** %tmp153.i.i166.i, align 4 store i32 (...)** %tmp150151.i.i165.i, i32 (...)*** %tmp153.i.i166.i, align 4
%tmp159.i.i167.i = bitcast i8* %tmp96.i.i142.i to i32 (...)*** ; <i32 (...)***> [#uses=1] %tmp159.i.i167.i = bitcast i8* %tmp96.i.i142.i to i32 (...)*** ; <i32 (...)***> [#uses=1]
store i32 (...)** getelementptr ([10 x i32 (...)*], [10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 3), i32 (...)*** %tmp159.i.i167.i, align 4 store i32 (...)** getelementptr ([10 x i32 (...)*], [10 x i32 (...)*]* @_ZTVSt19basic_ostringstreamIcSt11char_traitsIcESaIcEE, i32 0, i32 3), i32 (...)*** %tmp159.i.i167.i, align 4
store i32 (...)** getelementptr ([16 x i32 (...)*], [16 x i32 (...)*]* @_ZTVSt15basic_streambufIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4 store i32 (...)** getelementptr ([16 x i32 (...)*], [16 x i32 (...)*]* @_ZTVSt15basic_streambufIcSt11char_traitsIcEE, i32 0, i32 2), i32 (...)*** null, align 4
call void @_ZNSt6localeC1Ev( %"struct.std::locale"* null ) nounwind call void @_ZNSt6localeC1Ev( %"struct.std::locale"* null ) nounwind
store i32 (...)** getelementptr ([16 x i32 (...)*], [16 x i32 (...)*]* @_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE, i32 0, i32 2), i32 (...)*** null, align 4 store i32 (...)** getelementptr ([16 x i32 (...)*], [16 x i32 (...)*]* @_ZTVSt15basic_stringbufIcSt11char_traitsIcESaIcEE, i32 0, i32 2), i32 (...)*** null, align 4
unreachable unreachable
} }
declare i8* @_Znwm(i32) declare i8* @_Znwm(i32)
declare void @_ZNSt8ios_baseC2Ev(%"struct.std::ios_base"*) declare void @_ZNSt8ios_baseC2Ev(%"struct.std::ios_base"*)
declare void @_ZNSt6localeC1Ev(%"struct.std::locale"*) nounwind declare void @_ZNSt6localeC1Ev(%"struct.std::locale"*) nounwind

llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll

; RUN: llc < %s -mtriple=i686-- | not grep jmp ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
%struct..0anon = type { i32 } %struct..0anon = type { i32 }
%struct.binding_level = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.binding_level*, i8, i8, i8, i8, i8, i32, %struct.tree_node* } %struct.binding_level = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.binding_level*, i8, i8, i8, i8, i8, i32, %struct.tree_node* }
%struct.lang_decl = type opaque %struct.lang_decl = type opaque
%struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] } %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
%struct.tree_decl = type { [12 x i8], i8*, i32, %struct.tree_node*, i32, i8, i8, i8, i8, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct..0anon, { %struct.rtx_def* }, %struct.tree_node*, %struct.lang_decl* } %struct.tree_decl = type { [12 x i8], i8*, i32, %struct.tree_node*, i32, i8, i8, i8, i8, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct..0anon, { %struct.rtx_def* }, %struct.tree_node*, %struct.lang_decl* }
%struct.tree_node = type { %struct.tree_decl } %struct.tree_node = type { %struct.tree_decl }
define fastcc %struct.tree_node* @pushdecl(%struct.tree_node* %x) nounwind { define fastcc %struct.tree_node* @pushdecl(%struct.tree_node* %x) nounwind {
; CHECK-LABEL: pushdecl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb17.i
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %bb160
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
entry: entry:
%tmp3.i40 = icmp eq %struct.binding_level* null, null ; <i1> [#uses=2] %tmp3.i40 = icmp eq %struct.binding_level* null, null ; <i1> [#uses=2]
br label %bb140 br label %bb140
bb140: ; preds = %entry bb140: ; preds = %entry
br i1 %tmp3.i40, label %bb160, label %bb17.i br i1 %tmp3.i40, label %bb160, label %bb17.i
bb17.i: ; preds = %bb140 bb17.i: ; preds = %bb140
ret %struct.tree_node* null ret %struct.tree_node* null
bb143: ; preds = %entry bb143: ; preds = %entry
Show All 15 Linesbb73.i: ; preds = %bb174
br i1 false, label %bb226.i, label %bb220.i br i1 false, label %bb226.i, label %bb220.i
bb220.i: ; preds = %bb73.i bb220.i: ; preds = %bb73.i
ret %struct.tree_node* null ret %struct.tree_node* null
bb226.i: ; preds = %bb73.i bb226.i: ; preds = %bb73.i
br i1 false, label %bb260, label %bb273.i br i1 false, label %bb260, label %bb273.i
bb273.i: ; preds = %bb226.i bb273.i: ; preds = %bb226.i
ret %struct.tree_node* null ret %struct.tree_node* null
bb260: ; preds = %bb226.i bb260: ; preds = %bb226.i
tail call void (i8*, i32, ...) @pedwarn_with_file_and_line( i8* %file.0, i32 %line.0, i8* null ) nounwind tail call void (i8*, i32, ...) @pedwarn_with_file_and_line( i8* %file.0, i32 %line.0, i8* null ) nounwind
ret %struct.tree_node* null ret %struct.tree_node* null
bb344: ; preds = %bb174 bb344: ; preds = %bb174
ret %struct.tree_node* null ret %struct.tree_node* null
} }
declare void @pedwarn_with_file_and_line(i8*, i32, ...) nounwind declare void @pedwarn_with_file_and_line(i8*, i32, ...) nounwind

llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll

; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | grep movw | not grep ", %e" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | FileCheck %s
%struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 } %struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 }
%struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* } %struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* }
%struct.GENV_t = type { i32, i8*, i16, i8*, i8*, i32, i32, i32, i32, %struct.DBC_t*, i16 } %struct.GENV_t = type { i32, i8*, i16, i8*, i8*, i32, i32, i32, i32, %struct.DBC_t*, i16 }
%struct.pthread_mutex_t = type { i32, [40 x i8] } %struct.pthread_mutex_t = type { i32, [40 x i8] }
@iodbcdm_global_lock = external global %struct.pthread_mutex_t ; <%struct.pthread_mutex_t*> [#uses=1] @iodbcdm_global_lock = external global %struct.pthread_mutex_t ; <%struct.pthread_mutex_t*> [#uses=1]
define i16 @SQLDriversW(i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr) nounwind { define i16 @SQLDriversW(i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr) nounwind {
; CHECK-LABEL: SQLDriversW:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: ## %bb.3: ## %bb28
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movw $-2, %si
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.4: ## %bb37
; CHECK-NEXT: movw $0, 40(%edi)
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: leal (,%ecx,4), %eax
; CHECK-NEXT: leal (,%ebx,4), %ecx
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: movzwl %bp, %edx
; CHECK-NEXT: cwtl
; CHECK-NEXT: movswl %cx, %ecx
; CHECK-NEXT: pushl $87
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: calll _SQLDrivers_Internal
; CHECK-NEXT: addl $48, %esp
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: ## %bb.5:
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: LBB0_6: ## %done
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: je LBB0_7
; CHECK-NEXT: ## %bb.8: ## %bb167
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: movl L_iodbcdm_global_lock$non_lazy_ptr, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: calll _pthread_mutex_unlock
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: jmp LBB0_2
; CHECK-NEXT: LBB0_7: ## %bb150
; CHECK-NEXT: movswl %si, %eax
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movswl %cx, %ecx
; CHECK-NEXT: movswl %bx, %edx
; CHECK-NEXT: movzwl %bp, %esi
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $1
; CHECK-NEXT: calll _trace_SQLDriversW
; CHECK-NEXT: addl $48, %esp
; CHECK-NEXT: LBB0_1: ## %bb
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: LBB0_2: ## %bb
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%tmp12 = bitcast i8* %henv to %struct.GENV_t* ; <%struct.GENV_t*> [#uses=1] %tmp12 = bitcast i8* %henv to %struct.GENV_t* ; <%struct.GENV_t*> [#uses=1]
br i1 true, label %bb28, label %bb br i1 true, label %bb28, label %bb
bb: ; preds = %entry bb: ; preds = %entry
ret i16 0 ret i16 0
bb28: ; preds = %entry bb28: ; preds = %entry
br i1 false, label %bb37, label %done br i1 false, label %bb37, label %done
bb37: ; preds = %bb28 bb37: ; preds = %bb28
Show All 9 Linesbb92: ; preds = %bb74, %bb37
br i1 false, label %done, label %bb137 br i1 false, label %done, label %bb137
bb137: ; preds = %bb92 bb137: ; preds = %bb92
ret i16 0 ret i16 0
done: ; preds = %bb92, %bb28 done: ; preds = %bb92, %bb28
%retcode.0 = phi i16 [ -2, %bb28 ], [ %tmp113, %bb92 ] ; <i16> [#uses=2] %retcode.0 = phi i16 [ -2, %bb28 ], [ %tmp113, %bb92 ] ; <i16> [#uses=2]
br i1 false, label %bb167, label %bb150 br i1 false, label %bb167, label %bb150
bb150: ; preds = %done bb150: ; preds = %done
%tmp157158 = sext i16 %retcode.0 to i32 ; <i32> [#uses=1] %tmp157158 = sext i16 %retcode.0 to i32 ; <i32> [#uses=1]
tail call void @trace_SQLDriversW( i32 1, i32 %tmp157158, i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr ) nounwind tail call void @trace_SQLDriversW( i32 1, i32 %tmp157158, i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr ) nounwind
ret i16 0 ret i16 0
bb167: ; preds = %done bb167: ; preds = %done
%tmp168 = tail call i32 @pthread_mutex_unlock( %struct.pthread_mutex_t* @iodbcdm_global_lock ) nounwind ; <i32> [#uses=0] %tmp168 = tail call i32 @pthread_mutex_unlock( %struct.pthread_mutex_t* @iodbcdm_global_lock ) nounwind ; <i32> [#uses=0]
ret i16 %retcode.0 ret i16 %retcode.0
} }
declare i32 @pthread_mutex_unlock(%struct.pthread_mutex_t*) declare i32 @pthread_mutex_unlock(%struct.pthread_mutex_t*)
declare i16 @SQLDrivers_Internal(i8*, i16 zeroext , i8*, i16 signext , i16*, i8*, i16 signext , i16*, i8 zeroext ) nounwind declare i16 @SQLDrivers_Internal(i8*, i16 zeroext , i8*, i16 signext , i16*, i8*, i16 signext , i16*, i8 zeroext ) nounwind
declare void @trace_SQLDriversW(i32, i32, i8*, i16 zeroext , i32*, i16 signext , i16*, i32*, i16 signext , i16*) declare void @trace_SQLDriversW(i32, i32, i8*, i16 zeroext , i32*, i16 signext , i16*, i32*, i16 signext , i16*)

llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll

; RUN: llc < %s -mtriple=i386-apple-darwin | grep xorl | grep "%e" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
; Make sure xorl operands are 32-bit registers. ; Make sure xorl operands are 32-bit registers.
%struct.tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8* } %struct.tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8* }
%struct.wxDateTime = type { %struct.wxLongLong } %struct.wxDateTime = type { %struct.wxLongLong }
%"struct.wxDateTime::TimeZone" = type { i32 } %"struct.wxDateTime::TimeZone" = type { i32 }
%struct.wxLongLong = type { i64 } %struct.wxLongLong = type { i64 }
%struct.wxString = type { %struct.wxStringBase } %struct.wxString = type { %struct.wxStringBase }
%struct.wxStringBase = type { i32* } %struct.wxStringBase = type { i32* }
@.str = external constant [27 x i32] ; <[27 x i32]*> [#uses=1] @.str = external constant [27 x i32] ; <[27 x i32]*> [#uses=1]
@.str4 = external constant [14 x i32] ; <[14 x i32]*> [#uses=1] @.str4 = external constant [14 x i32] ; <[14 x i32]*> [#uses=1]
@_ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__ = external constant [6 x i8] ; <[6 x i8]*> [#uses=1] @_ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__ = external constant [6 x i8] ; <[6 x i8]*> [#uses=1]
@.str33 = external constant [29 x i32] ; <[29 x i32]*> [#uses=1] @.str33 = external constant [29 x i32] ; <[29 x i32]*> [#uses=1]
@.str89 = external constant [5 x i32] ; <[5 x i32]*> [#uses=1] @.str89 = external constant [5 x i32] ; <[5 x i32]*> [#uses=1]
define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalias sret %agg.result, %struct.wxDateTime* %this, i32* %format, %"struct.wxDateTime::TimeZone"* %tz, i1 %foo) personality i32 (...)* @__gxx_personality_v0 { define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalias sret %agg.result, %struct.wxDateTime* %this, i32* %format, %"struct.wxDateTime::TimeZone"* %tz, i1 %foo) personality i32 (...)* @__gxx_personality_v0 {
; CHECK-LABEL: _ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 20
; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: .cfi_offset %esi, -20
; CHECK-NEXT: .cfi_offset %edi, -16
; CHECK-NEXT: .cfi_offset %ebx, -12
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %bl
; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.1: ## %bb116.i
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.2: ## %bb52.i.i
; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.3: ## %bb142.i
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.4:
; CHECK-NEXT: movl L_.str89$non_lazy_ptr, %edi
; CHECK-NEXT: movb $1, %bh
; CHECK-NEXT: movl $274877907, %ebp ## imm = 0x10624DD3
; CHECK-NEXT: jmp LBB0_5
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_23: ## %bb7806
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: Ltmp16:
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZN12wxStringBase6appendEmw
; CHECK-NEXT: Ltmp17:
; CHECK-NEXT: LBB0_5: ## %bb3261
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpl $37, 0
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: ## %bb.6: ## %bb3306
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: Ltmp0:
; CHECK-NEXT: movl %edi, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZN12wxStringBaseaSEPKw
; CHECK-NEXT: Ltmp1:
; CHECK-NEXT: ## %bb.7: ## %bb3314
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: cmpl $121, %eax
; CHECK-NEXT: ja LBB0_27
; CHECK-NEXT: ## %bb.8: ## %bb3314
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: jmpl *LJTI0_0(,%eax,4)
; CHECK-NEXT: LBB0_10: ## %bb5809
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: ## %bb.11: ## %bb5809
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: testb %bh, %bh
; CHECK-NEXT: je LBB0_27
; CHECK-NEXT: ## %bb.12: ## %bb91.i8504
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: je LBB0_14
; CHECK-NEXT: ## %bb.13: ## %bb155.i8541
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: Ltmp4:
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll _gmtime_r
; CHECK-NEXT: Ltmp5:
; CHECK-NEXT: LBB0_14: ## %bb182.i8560
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: testb $1, %bl
; CHECK-NEXT: je LBB0_15
; CHECK-NEXT: ## %bb.17: ## %bb278.i8617
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: je LBB0_19
; CHECK-NEXT: ## %bb.18: ## %bb440.i8663
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: Ltmp6:
; CHECK-NEXT: movl L_.str4$non_lazy_ptr, %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl L_.str33$non_lazy_ptr, %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl L__ZZNK10wxDateTime5GetTmERKNS_8TimeZoneEE12__FUNCTION__$non_lazy_ptr, %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl L_.str$non_lazy_ptr, %eax
; CHECK-NEXT: movl %eax, (%esp)
; CHECK-NEXT: movl $1717, {{[0-9]+}}(%esp) ## imm = 0x6B5
; CHECK-NEXT: calll __Z10wxOnAssertPKwiPKcS0_S0_
; CHECK-NEXT: Ltmp7:
; CHECK-NEXT: LBB0_19: ## %bb448.i8694
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: jmp LBB0_20
; CHECK-NEXT: LBB0_15: ## %bb187.i8591
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: jne LBB0_27
; CHECK-NEXT: ## %bb.16: ## %bb265.i8606
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: imull %ebp
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: shrl $6, %edx
; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: imull $1000, %edx, %eax ## imm = 0x3E8
; CHECK-NEXT: negl %eax
; CHECK-NEXT: LBB0_20: ## %invcont5814
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: movzwl %ax, %eax
; CHECK-NEXT: Ltmp8:
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZN8wxString6FormatEPKwz
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: Ltmp9:
; CHECK-NEXT: ## %bb.21: ## %invcont5831
; CHECK-NEXT: ## in Loop: Header=BB0_5 Depth=1
; CHECK-NEXT: Ltmp10:
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZN12wxStringBase10ConcatSelfEmPKwm
; CHECK-NEXT: Ltmp11:
; CHECK-NEXT: jmp LBB0_5
; CHECK-NEXT: LBB0_22: ## %bb5968
; CHECK-NEXT: Ltmp2:
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZN8wxString6FormatEPKwz
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: Ltmp3:
; CHECK-NEXT: jmp LBB0_27
; CHECK-NEXT: LBB0_9: ## %bb5657
; CHECK-NEXT: Ltmp13:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, (%esp)
; CHECK-NEXT: calll __ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE
; CHECK-NEXT: Ltmp14:
; CHECK-NEXT: LBB0_27: ## %bb115.critedge.i
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl $4
; CHECK-NEXT: LBB0_25: ## %lpad.loopexit.split-lp
; CHECK-NEXT: Ltmp15:
; CHECK-NEXT: jmp LBB0_27
; CHECK-NEXT: LBB0_26: ## %lpad8185
; CHECK-NEXT: Ltmp12:
; CHECK-NEXT: jmp LBB0_27
; CHECK-NEXT: LBB0_24: ## %lpad.loopexit
; CHECK-NEXT: Ltmp18:
; CHECK-NEXT: jmp LBB0_27
; CHECK-NEXT: Lfunc_end0:
entry: entry:
br i1 %foo, label %bb116.i, label %bb115.critedge.i br i1 %foo, label %bb116.i, label %bb115.critedge.i
bb115.critedge.i: ; preds = %entry bb115.critedge.i: ; preds = %entry
ret void ret void
bb116.i: ; preds = %entry bb116.i: ; preds = %entry
br i1 %foo, label %bb52.i.i, label %bb3118 br i1 %foo, label %bb52.i.i, label %bb3118
bb3118: ; preds = %bb116.i bb3118: ; preds = %bb116.i
ret void ret void
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linesbb3626: ; preds = %bb3314, %bb3314
ret void ret void
bb5184: ; preds = %bb3314 bb5184: ; preds = %bb3314
ret void ret void
bb5334: ; preds = %bb3314 bb5334: ; preds = %bb3314
ret void ret void
bb5484: ; preds = %bb3314 bb5484: ; preds = %bb3314
ret void ret void
bb5657: ; preds = %bb3314 bb5657: ; preds = %bb3314
%tmp5661 = invoke zeroext i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE( %struct.wxDateTime* %this, %"struct.wxDateTime::TimeZone"* %tz ) %tmp5661 = invoke zeroext i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE( %struct.wxDateTime* %this, %"struct.wxDateTime::TimeZone"* %tz )
to label %invcont5660 unwind label %lpad ; <i16> [#uses=0] to label %invcont5660 unwind label %lpad ; <i16> [#uses=0]
invcont5660: ; preds = %bb5657 invcont5660: ; preds = %bb5657
ret void ret void
bb5809: ; preds = %bb3314 bb5809: ; preds = %bb3314
%tmp61.i.i8486 = icmp sgt i64 0, -1 ; <i1> [#uses=1] %tmp61.i.i8486 = icmp sgt i64 0, -1 ; <i1> [#uses=1]
%tmp95.i.i8490 = icmp slt i64 0, 2147483647000 ; <i1> [#uses=1] %tmp95.i.i8490 = icmp slt i64 0, 2147483647000 ; <i1> [#uses=1]
%bothcond9308 = and i1 %tmp61.i.i8486, %tmp95.i.i8490 ; <i1> [#uses=1] %bothcond9308 = and i1 %tmp61.i.i8486, %tmp95.i.i8490 ; <i1> [#uses=1]
br i1 %bothcond9308, label %bb91.i8504, label %bb115.critedge.i.i8492 br i1 %bothcond9308, label %bb91.i8504, label %bb115.critedge.i.i8492
Show All 28 Linesbb448.i8694: ; preds = %bb440.i8663, %bb278.i8617
%tmp477478.i8670 = trunc i32 %tmp477.i8669 to i16 ; <i16> [#uses=1] %tmp477478.i8670 = trunc i32 %tmp477.i8669 to i16 ; <i16> [#uses=1]
br label %invcont5814 br label %invcont5814
invcont5814: ; preds = %bb448.i8694, %bb265.i8606 invcont5814: ; preds = %bb448.i8694, %bb265.i8606
%tmp812.0.0 = phi i16 [ %tmp477478.i8670, %bb448.i8694 ], [ %tmp273274.i8595, %bb265.i8606 ] ; <i16> [#uses=1] %tmp812.0.0 = phi i16 [ %tmp477478.i8670, %bb448.i8694 ], [ %tmp273274.i8595, %bb265.i8606 ] ; <i16> [#uses=1]
%tmp58165817 = zext i16 %tmp812.0.0 to i32 ; <i32> [#uses=1] %tmp58165817 = zext i16 %tmp812.0.0 to i32 ; <i32> [#uses=1]
invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 %tmp58165817 ) invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 %tmp58165817 )
to label %invcont5831 unwind label %lpad to label %invcont5831 unwind label %lpad
invcont5831: ; preds = %invcont5814 invcont5831: ; preds = %invcont5814
%tmp5862 = invoke zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm( %struct.wxStringBase* null, i32 0, i32* null, i32 0 ) %tmp5862 = invoke zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm( %struct.wxStringBase* null, i32 0, i32* null, i32 0 )
to label %bb7834 unwind label %lpad8185 ; <i8> [#uses=0] to label %bb7834 unwind label %lpad8185 ; <i8> [#uses=0]
bb5968: ; preds = %bb3314 bb5968: ; preds = %bb3314
invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 0 ) invoke void (%struct.wxString*, i32*, ...) @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 0 )
to label %invcont5981 unwind label %lpad to label %invcont5981 unwind label %lpad
invcont5981: ; preds = %bb5968 invcont5981: ; preds = %bb5968
ret void ret void
bb6118: ; preds = %bb3314 bb6118: ; preds = %bb3314
ret void ret void
Show All 25 Lines
lpad8185: ; preds = %invcont5831 lpad8185: ; preds = %invcont5831
%exn8185 = landingpad {i8*, i32} %exn8185 = landingpad {i8*, i32}
cleanup cleanup
ret void ret void
} }
declare void @_Z10wxOnAssertPKwiPKcS0_S0_(i32*, i32, i8*, i32*, i32*) declare void @_Z10wxOnAssertPKwiPKcS0_S0_(i32*, i32, i8*, i32*, i32*)
declare zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm(%struct.wxStringBase*, i32, i32*, i32) declare zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm(%struct.wxStringBase*, i32, i32*, i32)
declare %struct.tm* @gmtime_r(i32*, %struct.tm*) declare %struct.tm* @gmtime_r(i32*, %struct.tm*)
declare zeroext i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE(%struct.wxDateTime*, %"struct.wxDateTime::TimeZone"*) declare zeroext i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE(%struct.wxDateTime*, %"struct.wxDateTime::TimeZone"*)
declare %struct.wxStringBase* @_ZN12wxStringBase6appendEmw(%struct.wxStringBase*, i32, i32) declare %struct.wxStringBase* @_ZN12wxStringBase6appendEmw(%struct.wxStringBase*, i32, i32)
declare %struct.wxStringBase* @_ZN12wxStringBaseaSEPKw(%struct.wxStringBase*, i32*) declare %struct.wxStringBase* @_ZN12wxStringBaseaSEPKw(%struct.wxStringBase*, i32*)
declare void @_ZN8wxString6FormatEPKwz(%struct.wxString* noalias sret , i32*, ...) declare void @_ZN8wxString6FormatEPKwz(%struct.wxString* noalias sret , i32*, ...)
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)

llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll

; RUN: llc < %s -mtriple=i686-- | not grep 120 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; Don't accidentally add the offset twice for trailing bytes. ; Don't accidentally add the offset twice for trailing bytes.
%struct.S63 = type { [63 x i8] } %struct.S63 = type { [63 x i8] }
@g1s63 = external global %struct.S63 ; <%struct.S63*> [#uses=1] @g1s63 = external global %struct.S63 ; <%struct.S63*> [#uses=1]
declare void @test63(%struct.S63* byval align 4 ) nounwind declare void @test63(%struct.S63* byval align 4 ) nounwind
define void @testit63_entry_2E_ce() nounwind { define void @testit63_entry_2E_ce() nounwind {
; CHECK-LABEL: testit63_entry_2E_ce:
; CHECK: # %bb.0:
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $64, %esp
; CHECK-NEXT: movl $15, %ecx
; CHECK-NEXT: movl %esp, %edi
; CHECK-NEXT: movl $g1s63, %esi
; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
; CHECK-NEXT: movb g1s63+62, %al
; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl g1s63+60, %eax
; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)
; CHECK-NEXT: calll test63
; CHECK-NEXT: addl $64, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl
tail call void @test63( %struct.S63* byval align 4 @g1s63 ) nounwind tail call void @test63( %struct.S63* byval align 4 @g1s63 ) nounwind
ret void ret void
} }

llvm/test/CodeGen/X86/2008-04-28-CoalescerBug.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep "r[abcd]x" %t ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; RUN: not grep "r[ds]i" %t
; RUN: not grep "r[bs]p" %t
%struct.BITMAP = type { i16, i16, i32, i32, i32, i32, i32, i32, i8*, i8* } %struct.BITMAP = type { i16, i16, i32, i32, i32, i32, i32, i32, i8*, i8* }
%struct.BltData = type { float, float, float, float } %struct.BltData = type { float, float, float, float }
%struct.BltDepth = type { i32, i8**, i32, %struct.BITMAP* (%struct.BltDepth**, %struct.BITMAP*, i32, i32, float*, float, i32)*, i32 (%struct.BltDepth**, %struct.BltOp*)*, i32 (%struct.BltDepth**, %struct.BltOp*, %struct.BltImg*)*, i32 (%struct.BltDepth**, %struct.BltOp*, %struct.BltSh*)*, [28 x [2 x [2 x i32]]]*, %struct.BltData* } %struct.BltDepth = type { i32, i8**, i32, %struct.BITMAP* (%struct.BltDepth**, %struct.BITMAP*, i32, i32, float*, float, i32)*, i32 (%struct.BltDepth**, %struct.BltOp*)*, i32 (%struct.BltDepth**, %struct.BltOp*, %struct.BltImg*)*, i32 (%struct.BltDepth**, %struct.BltOp*, %struct.BltSh*)*, [28 x [2 x [2 x i32]]]*, %struct.BltData* }
%struct.BltImg = type { i32, i8, i8, i8, float, float*, float*, i32, i32, float*, i32 (i8*, i8*, i8**, i32*, i8**, i32*)*, i8* } %struct.BltImg = type { i32, i8, i8, i8, float, float*, float*, i32, i32, float*, i32 (i8*, i8*, i8**, i32*, i8**, i32*)*, i8* }
%struct.BltOp = type { i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i8* } %struct.BltOp = type { i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i8* }
%struct.BltSh = type { i8, i8, i8, i8, float, float*, float*, float*, float*, i32, i32, float*, float*, float* } %struct.BltSh = type { i8, i8, i8, i8, float, float*, float*, float*, float*, i32, i32, float*, float*, float* }
define void @t(%struct.BltDepth* %depth, %struct.BltOp* %bop, i32 %mode) nounwind { define void @t(%struct.BltDepth* %depth, %struct.BltOp* %bop, i32 %mode) nounwind {
; CHECK-LABEL: t:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: cmpl $18, %edx
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: ## %bb.1: ## %entry
; CHECK-NEXT: cmpl $1, %edx
; CHECK-NEXT: jne LBB0_10
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_2: ## %bb2898.us
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: jmp LBB0_2
; CHECK-NEXT: LBB0_3: ## %bb13086.preheader
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_4: ## %bb13088
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_5
; CHECK-NEXT: ## %bb.6: ## %bb13101
; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: jmp LBB0_7
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_5: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: movl $65535, %ecx ## imm = 0xFFFF
; CHECK-NEXT: LBB0_7: ## %bb13107
; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: movl %ecx, %edx
; CHECK-NEXT: shll $16, %edx
; CHECK-NEXT: subl %ecx, %edx
; CHECK-NEXT: incl %edx
; CHECK-NEXT: shrl $16, %edx
; CHECK-NEXT: subl %edx, %ecx
; CHECK-NEXT: testw %cx, %cx
; CHECK-NEXT: je LBB0_4
; CHECK-NEXT: ## %bb.8: ## %bb13236
; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: cmpw $-1, %cx
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne LBB0_4
; CHECK-NEXT: ## %bb.9: ## %bb13572
; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: movzwl %cx, %ecx
; CHECK-NEXT: movl %ecx, %edx
; CHECK-NEXT: shll $16, %edx
; CHECK-NEXT: subl %ecx, %edx
; CHECK-NEXT: incl %edx
; CHECK-NEXT: shrl $16, %edx
; CHECK-NEXT: movw %dx, 0
; CHECK-NEXT: jmp LBB0_4
; CHECK-NEXT: LBB0_10: ## %return
; CHECK-NEXT: retq
entry: entry:
switch i32 %mode, label %return [ switch i32 %mode, label %return [
i32 1, label %bb2898.us i32 1, label %bb2898.us
i32 18, label %bb13086.preheader i32 18, label %bb13086.preheader
] ]
bb13086.preheader: ; preds = %entry bb13086.preheader: ; preds = %entry
%tmp13098 = icmp eq i32 0, 0 ; <i1> [#uses=1] %tmp13098 = icmp eq i32 0, 0 ; <i1> [#uses=1]
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll

; RUN: llc < %s -enable-unsafe-fp-math -mtriple=i686-- | grep jp ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -enable-unsafe-fp-math -mtriple=i686-- | FileCheck %s
; rdar://5902801 ; rdar://5902801
declare void @test2() declare void @test2()
define i32 @test(double %p) nounwind { define i32 @test(double %p) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: fucomp %st(0)
; CHECK-NEXT: fnstsw %ax
; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
; CHECK-NEXT: sahf
; CHECK-NEXT: jp .LBB0_1
; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: calll test2
; CHECK-NEXT: movl $17, %eax
; CHECK-NEXT: retl
%tmp5 = fcmp uno double %p, 0.000000e+00 %tmp5 = fcmp uno double %p, 0.000000e+00
br i1 %tmp5, label %bb, label %UnifiedReturnBlock br i1 %tmp5, label %bb, label %UnifiedReturnBlock
bb: bb:
call void @test2() call void @test2()
ret i32 17 ret i32 17
UnifiedReturnBlock: UnifiedReturnBlock:
ret i32 42 ret i32 42
} }

llvm/test/CodeGen/X86/2008-05-12-tailmerge-5.ll

; RUN: llc < %s | grep abort | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; Calls to abort should all be merged ; Calls to abort should all be merged
; ModuleID = '5898899.c' ; ModuleID = '5898899.c'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8" target triple = "x86_64-apple-darwin8"
%struct.BoundaryAlignment = type { [3 x i8], i8, i16, i16, i8, [2 x i8] } %struct.BoundaryAlignment = type { [3 x i8], i8, i16, i16, i8, [2 x i8] }
define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind optsize { define void @passing2(i64 %str.0, i64 %str.1, i16 signext %s, i32 %j, i8 signext %c, i16 signext %t, i16 signext %u, i8 signext %d) nounwind optsize {
; CHECK-LABEL: passing2:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movq %rsi, %rax
; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %ah, {{[0-9]+}}(%rsp)
; CHECK-NEXT: shrq $16, %rsi
; CHECK-NEXT: movb %sil, {{[0-9]+}}(%rsp)
; CHECK-NEXT: shrq $24, %rax
; CHECK-NEXT: movb %al, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %dx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %r8b, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %r9w, {{[0-9]+}}(%rsp)
; CHECK-NEXT: shll $14, %edi
; CHECK-NEXT: sarl $23, %edi
; CHECK-NEXT: cmpl %ecx, %edi
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.1: ## %bb27
; CHECK-NEXT: movb {{[0-9]+}}(%rsp), %al
; CHECK-NEXT: cmpb {{[0-9]+}}(%rsp), %al
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.2: ## %bb35
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: shll $7, %eax
; CHECK-NEXT: cwtl
; CHECK-NEXT: shrl $7, %eax
; CHECK-NEXT: cmpw {{[0-9]+}}(%rsp), %ax
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.3: ## %bb51
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: shll $7, %eax
; CHECK-NEXT: cwtl
; CHECK-NEXT: shrl $7, %eax
; CHECK-NEXT: cmpw {{[0-9]+}}(%rsp), %ax
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.4: ## %bb67
; CHECK-NEXT: movb {{[0-9]+}}(%rsp), %al
; CHECK-NEXT: cmpb {{[0-9]+}}(%rsp), %al
; CHECK-NEXT: jne LBB0_6
; CHECK-NEXT: ## %bb.5: ## %bb75
; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_6: ## %bb
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq _abort
entry: entry:
%str_addr = alloca %struct.BoundaryAlignment ; <%struct.BoundaryAlignment*> [#uses=7] %str_addr = alloca %struct.BoundaryAlignment ; <%struct.BoundaryAlignment*> [#uses=7]
%s_addr = alloca i16 ; <i16*> [#uses=1] %s_addr = alloca i16 ; <i16*> [#uses=1]
%j_addr = alloca i32 ; <i32*> [#uses=2] %j_addr = alloca i32 ; <i32*> [#uses=2]
%c_addr = alloca i8 ; <i8*> [#uses=2] %c_addr = alloca i8 ; <i8*> [#uses=2]
%t_addr = alloca i16 ; <i16*> [#uses=2] %t_addr = alloca i16 ; <i16*> [#uses=2]
%u_addr = alloca i16 ; <i16*> [#uses=2] %u_addr = alloca i16 ; <i16*> [#uses=2]
%d_addr = alloca i8 ; <i8*> [#uses=2] %d_addr = alloca i8 ; <i8*> [#uses=2]
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%sextr2223 = sext i16 %sextr22 to i32 ; <i32> [#uses=1] %sextr2223 = sext i16 %sextr22 to i32 ; <i32> [#uses=1]
%tmp24 = load i32, i32* %j_addr, align 4 ; <i32> [#uses=1] %tmp24 = load i32, i32* %j_addr, align 4 ; <i32> [#uses=1]
%tmp25 = icmp ne i32 %sextr2223, %tmp24 ; <i1> [#uses=1] %tmp25 = icmp ne i32 %sextr2223, %tmp24 ; <i1> [#uses=1]
%tmp2526 = zext i1 %tmp25 to i8 ; <i8> [#uses=1] %tmp2526 = zext i1 %tmp25 to i8 ; <i8> [#uses=1]
%toBool = icmp ne i8 %tmp2526, 0 ; <i1> [#uses=1] %toBool = icmp ne i8 %tmp2526, 0 ; <i1> [#uses=1]
br i1 %toBool, label %bb, label %bb27 br i1 %toBool, label %bb, label %bb27
bb: ; preds = %entry bb: ; preds = %entry
call void (...) @abort( ) noreturn nounwind call void (...) @abort( ) noreturn nounwind
unreachable unreachable
bb27: ; preds = %entry bb27: ; preds = %entry
%tmp28 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 1 ; <i8*> [#uses=1] %tmp28 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 1 ; <i8*> [#uses=1]
%tmp29 = load i8, i8* %tmp28, align 4 ; <i8> [#uses=1] %tmp29 = load i8, i8* %tmp28, align 4 ; <i8> [#uses=1]
%tmp30 = load i8, i8* %c_addr, align 1 ; <i8> [#uses=1] %tmp30 = load i8, i8* %c_addr, align 1 ; <i8> [#uses=1]
%tmp31 = icmp ne i8 %tmp29, %tmp30 ; <i1> [#uses=1] %tmp31 = icmp ne i8 %tmp29, %tmp30 ; <i1> [#uses=1]
%tmp3132 = zext i1 %tmp31 to i8 ; <i8> [#uses=1] %tmp3132 = zext i1 %tmp31 to i8 ; <i8> [#uses=1]
%toBool33 = icmp ne i8 %tmp3132, 0 ; <i1> [#uses=1] %toBool33 = icmp ne i8 %tmp3132, 0 ; <i1> [#uses=1]
br i1 %toBool33, label %bb34, label %bb35 br i1 %toBool33, label %bb34, label %bb35
bb34: ; preds = %bb27 bb34: ; preds = %bb27
call void (...) @abort( ) noreturn nounwind call void (...) @abort( ) noreturn nounwind
unreachable unreachable
bb35: ; preds = %bb27 bb35: ; preds = %bb27
%tmp36 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 2 ; <i16*> [#uses=1] %tmp36 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 2 ; <i16*> [#uses=1]
%tmp37 = load i16, i16* %tmp36, align 4 ; <i16> [#uses=1] %tmp37 = load i16, i16* %tmp36, align 4 ; <i16> [#uses=1]
%tmp38 = shl i16 %tmp37, 7 ; <i16> [#uses=1] %tmp38 = shl i16 %tmp37, 7 ; <i16> [#uses=1]
%tmp39 = ashr i16 %tmp38, 7 ; <i16> [#uses=1] %tmp39 = ashr i16 %tmp38, 7 ; <i16> [#uses=1]
%sextl40 = shl i16 %tmp39, 7 ; <i16> [#uses=1] %sextl40 = shl i16 %tmp39, 7 ; <i16> [#uses=1]
%sextr41 = ashr i16 %sextl40, 7 ; <i16> [#uses=2] %sextr41 = ashr i16 %sextl40, 7 ; <i16> [#uses=2]
%sextl42 = shl i16 %sextr41, 7 ; <i16> [#uses=1] %sextl42 = shl i16 %sextr41, 7 ; <i16> [#uses=1]
%sextr43 = ashr i16 %sextl42, 7 ; <i16> [#uses=0] %sextr43 = ashr i16 %sextl42, 7 ; <i16> [#uses=0]
%sextl44 = shl i16 %sextr41, 7 ; <i16> [#uses=1] %sextl44 = shl i16 %sextr41, 7 ; <i16> [#uses=1]
%sextr45 = ashr i16 %sextl44, 7 ; <i16> [#uses=1] %sextr45 = ashr i16 %sextl44, 7 ; <i16> [#uses=1]
%tmp46 = load i16, i16* %t_addr, align 2 ; <i16> [#uses=1] %tmp46 = load i16, i16* %t_addr, align 2 ; <i16> [#uses=1]
%tmp47 = icmp ne i16 %sextr45, %tmp46 ; <i1> [#uses=1] %tmp47 = icmp ne i16 %sextr45, %tmp46 ; <i1> [#uses=1]
%tmp4748 = zext i1 %tmp47 to i8 ; <i8> [#uses=1] %tmp4748 = zext i1 %tmp47 to i8 ; <i8> [#uses=1]
%toBool49 = icmp ne i8 %tmp4748, 0 ; <i1> [#uses=1] %toBool49 = icmp ne i8 %tmp4748, 0 ; <i1> [#uses=1]
br i1 %toBool49, label %bb50, label %bb51 br i1 %toBool49, label %bb50, label %bb51
bb50: ; preds = %bb35 bb50: ; preds = %bb35
call void (...) @abort( ) noreturn nounwind call void (...) @abort( ) noreturn nounwind
unreachable unreachable
bb51: ; preds = %bb35 bb51: ; preds = %bb35
%tmp52 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 3 ; <i16*> [#uses=1] %tmp52 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 3 ; <i16*> [#uses=1]
%tmp53 = load i16, i16* %tmp52, align 4 ; <i16> [#uses=1] %tmp53 = load i16, i16* %tmp52, align 4 ; <i16> [#uses=1]
%tmp54 = shl i16 %tmp53, 7 ; <i16> [#uses=1] %tmp54 = shl i16 %tmp53, 7 ; <i16> [#uses=1]
%tmp55 = ashr i16 %tmp54, 7 ; <i16> [#uses=1] %tmp55 = ashr i16 %tmp54, 7 ; <i16> [#uses=1]
%sextl56 = shl i16 %tmp55, 7 ; <i16> [#uses=1] %sextl56 = shl i16 %tmp55, 7 ; <i16> [#uses=1]
%sextr57 = ashr i16 %sextl56, 7 ; <i16> [#uses=2] %sextr57 = ashr i16 %sextl56, 7 ; <i16> [#uses=2]
%sextl58 = shl i16 %sextr57, 7 ; <i16> [#uses=1] %sextl58 = shl i16 %sextr57, 7 ; <i16> [#uses=1]
%sextr59 = ashr i16 %sextl58, 7 ; <i16> [#uses=0] %sextr59 = ashr i16 %sextl58, 7 ; <i16> [#uses=0]
%sextl60 = shl i16 %sextr57, 7 ; <i16> [#uses=1] %sextl60 = shl i16 %sextr57, 7 ; <i16> [#uses=1]
%sextr61 = ashr i16 %sextl60, 7 ; <i16> [#uses=1] %sextr61 = ashr i16 %sextl60, 7 ; <i16> [#uses=1]
%tmp62 = load i16, i16* %u_addr, align 2 ; <i16> [#uses=1] %tmp62 = load i16, i16* %u_addr, align 2 ; <i16> [#uses=1]
%tmp63 = icmp ne i16 %sextr61, %tmp62 ; <i1> [#uses=1] %tmp63 = icmp ne i16 %sextr61, %tmp62 ; <i1> [#uses=1]
%tmp6364 = zext i1 %tmp63 to i8 ; <i8> [#uses=1] %tmp6364 = zext i1 %tmp63 to i8 ; <i8> [#uses=1]
%toBool65 = icmp ne i8 %tmp6364, 0 ; <i1> [#uses=1] %toBool65 = icmp ne i8 %tmp6364, 0 ; <i1> [#uses=1]
br i1 %toBool65, label %bb66, label %bb67 br i1 %toBool65, label %bb66, label %bb67
bb66: ; preds = %bb51 bb66: ; preds = %bb51
call void (...) @abort( ) noreturn nounwind call void (...) @abort( ) noreturn nounwind
unreachable unreachable
bb67: ; preds = %bb51 bb67: ; preds = %bb51
%tmp68 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 4 ; <i8*> [#uses=1] %tmp68 = getelementptr %struct.BoundaryAlignment, %struct.BoundaryAlignment* %str_addr, i32 0, i32 4 ; <i8*> [#uses=1]
%tmp69 = load i8, i8* %tmp68, align 4 ; <i8> [#uses=1] %tmp69 = load i8, i8* %tmp68, align 4 ; <i8> [#uses=1]
%tmp70 = load i8, i8* %d_addr, align 1 ; <i8> [#uses=1] %tmp70 = load i8, i8* %d_addr, align 1 ; <i8> [#uses=1]
%tmp71 = icmp ne i8 %tmp69, %tmp70 ; <i1> [#uses=1] %tmp71 = icmp ne i8 %tmp69, %tmp70 ; <i1> [#uses=1]
%tmp7172 = zext i1 %tmp71 to i8 ; <i8> [#uses=1] %tmp7172 = zext i1 %tmp71 to i8 ; <i8> [#uses=1]
%toBool73 = icmp ne i8 %tmp7172, 0 ; <i1> [#uses=1] %toBool73 = icmp ne i8 %tmp7172, 0 ; <i1> [#uses=1]
br i1 %toBool73, label %bb74, label %bb75 br i1 %toBool73, label %bb74, label %bb75
bb74: ; preds = %bb67 bb74: ; preds = %bb67
call void (...) @abort( ) noreturn nounwind call void (...) @abort( ) noreturn nounwind
unreachable unreachable
bb75: ; preds = %bb67 bb75: ; preds = %bb67
br label %return br label %return
return: ; preds = %bb75 return: ; preds = %bb75
ret void ret void
} }
declare void @abort(...) noreturn nounwind declare void @abort(...) noreturn nounwind

llvm/test/CodeGen/X86/2008-05-21-CoalescerBug.ll

; RUN: llc < %s -mtriple=i686-- -O0 -fast-isel=false -optimize-regalloc -regalloc=basic | grep mov | count 5 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -O0 -fast-isel=false -optimize-regalloc -regalloc=basic | FileCheck %s
; PR2343 ; PR2343
%llvm.dbg.anchor.type = type { i32, i32 } %llvm.dbg.anchor.type = type { i32, i32 }
%struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
%struct.VEC_basic_block_base = type { i32, i32, [1 x %struct.basic_block_def*] } %struct.VEC_basic_block_base = type { i32, i32, [1 x %struct.basic_block_def*] }
%struct.VEC_basic_block_gc = type { %struct.VEC_basic_block_base } %struct.VEC_basic_block_gc = type { %struct.VEC_basic_block_base }
%struct.VEC_edge_base = type { i32, i32, [1 x %struct.edge_def*] } %struct.VEC_edge_base = type { i32, i32, [1 x %struct.edge_def*] }
%struct.VEC_edge_gc = type { %struct.VEC_edge_base } %struct.VEC_edge_gc = type { %struct.VEC_edge_base }
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; PR2343
%struct.unnamed_section = type { %struct.cfg_stats_d, void (i8*)*, i8*, %struct.section* } %struct.unnamed_section = type { %struct.cfg_stats_d, void (i8*)*, i8*, %struct.section* }
%struct.use_optype_d = type { %struct.use_optype_d*, %struct.ssa_use_operand_d } %struct.use_optype_d = type { %struct.use_optype_d*, %struct.ssa_use_operand_d }
%struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* } %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }
%struct.varasm_status = type opaque %struct.varasm_status = type opaque
%struct.vuse_optype_d = type { %struct.vuse_optype_d*, %struct.tree_node*, %struct.ssa_use_operand_d } %struct.vuse_optype_d = type { %struct.vuse_optype_d*, %struct.tree_node*, %struct.ssa_use_operand_d }
@llvm.used = appending global [1 x i8*] [ i8* bitcast (%struct.edge_def* (%struct.edge_def*, %struct.basic_block_def*)* @tree_redirect_edge_and_branch to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] @llvm.used = appending global [1 x i8*] [ i8* bitcast (%struct.edge_def* (%struct.edge_def*, %struct.basic_block_def*)* @tree_redirect_edge_and_branch to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define %struct.edge_def* @tree_redirect_edge_and_branch(%struct.edge_def* %e1, %struct.basic_block_def* %dest2) nounwind { define %struct.edge_def* @tree_redirect_edge_and_branch(%struct.edge_def* %e1, %struct.basic_block_def* %dest2) nounwind {
; CHECK-LABEL: tree_redirect_edge_and_branch:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movb $1, %cl
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: # implicit-def: $esi
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .LBB0_1: # %bb483
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: movl 0, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .LBB0_2: # %bb497
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: jmp .LBB0_3
; CHECK-NEXT: .LBB0_3: # %bb502
; CHECK-NEXT: testb $1, %cl
; CHECK-NEXT: je .LBB0_5
; CHECK-NEXT: jmp .LBB0_4
; CHECK-NEXT: .LBB0_4: # %bb507
; CHECK-NEXT: movl $0, (%esi)
; CHECK-NEXT: jmp .LBB0_5
; CHECK-NEXT: .LBB0_5: # %bb841
entry: entry:
br label %bb497 br label %bb497
bb483: ; preds = %bb497 bb483: ; preds = %bb497
%tmp496 = load %struct.tree_node*, %struct.tree_node** null, align 4 ; <%struct.tree_node*> [#uses=1] %tmp496 = load %struct.tree_node*, %struct.tree_node** null, align 4 ; <%struct.tree_node*> [#uses=1]
br label %bb497 br label %bb497
bb497: ; preds = %bb483, %entry bb497: ; preds = %bb483, %entry
Show All 18 Lines

llvm/test/CodeGen/X86/2008-06-13-VolatileLoadStore.ll

; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movsd | count 5 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | grep movl | count 2 ; RUN: llc < %s -mtriple=i686-linux -mattr=+sse2 | FileCheck %s
@atomic = global double 0.000000e+00 ; <double*> [#uses=1] @atomic = global double 0.000000e+00 ; <double*> [#uses=1]
@atomic2 = global double 0.000000e+00 ; <double*> [#uses=1] @atomic2 = global double 0.000000e+00 ; <double*> [#uses=1]
@anything = global i64 0 ; <i64*> [#uses=1] @anything = global i64 0 ; <i64*> [#uses=1]
@ioport = global i32 0 ; <i32*> [#uses=2] @ioport = global i32 0 ; <i32*> [#uses=2]
define i16 @f(i64 %x, double %y) { define i16 @f(i64 %x, double %y) {
; CHECK-LABEL: f:
; CHECK: # %bb.0:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: movsd %xmm1, atomic
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movsd %xmm1, atomic2
; CHECK-NEXT: movsd %xmm0, anything
; CHECK-NEXT: movl ioport, %ecx
; CHECK-NEXT: movl ioport, %eax
; CHECK-NEXT: shrl $16, %eax
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
%b = bitcast i64 %x to double ; <double> [#uses=1] %b = bitcast i64 %x to double ; <double> [#uses=1]
store volatile double %b, double* @atomic ; one processor operation only store volatile double %b, double* @atomic ; one processor operation only
store volatile double 0.000000e+00, double* @atomic2 ; one processor operation only store volatile double 0.000000e+00, double* @atomic2 ; one processor operation only
%b2 = bitcast double %y to i64 ; <i64> [#uses=1] %b2 = bitcast double %y to i64 ; <i64> [#uses=1]
store volatile i64 %b2, i64* @anything ; may transform to store of double store volatile i64 %b2, i64* @anything ; may transform to store of double
%l = load volatile i32, i32* @ioport ; must not narrow %l = load volatile i32, i32* @ioport ; must not narrow
%t = trunc i32 %l to i16 ; <i16> [#uses=1] %t = trunc i32 %l to i16 ; <i16> [#uses=1]
%l2 = load volatile i32, i32* @ioport ; must not narrow %l2 = load volatile i32, i32* @ioport ; must not narrow
%tmp = lshr i32 %l2, 16 ; <i32> [#uses=1] %tmp = lshr i32 %l2, 16 ; <i32> [#uses=1]
%t2 = trunc i32 %tmp to i16 ; <i16> [#uses=1] %t2 = trunc i32 %tmp to i16 ; <i16> [#uses=1]
%f = add i16 %t, %t2 ; <i16> [#uses=1] %f = add i16 %t, %t2 ; <i16> [#uses=1]
ret i16 %f ret i16 %f
} }

llvm/test/CodeGen/X86/2008-06-16-SubregsBug.ll

; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 4 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
define i16 @test(i16* %tmp179) nounwind { define i16 @test(i16* %tmp179) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movzwl (%eax), %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: andl $64512, %ecx ## imm = 0xFC00
; CHECK-NEXT: cmpl $32768, %ecx ## imm = 0x8000
; CHECK-NEXT: jne LBB0_2
; CHECK-NEXT: ## %bb.1: ## %bb189
; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_2: ## %bb288
; CHECK-NEXT: movw $32, %ax
; CHECK-NEXT: retl
%tmp180 = load i16, i16* %tmp179, align 2 ; <i16> [#uses=2] %tmp180 = load i16, i16* %tmp179, align 2 ; <i16> [#uses=2]
%tmp184 = and i16 %tmp180, -1024 ; <i16> [#uses=1] %tmp184 = and i16 %tmp180, -1024 ; <i16> [#uses=1]
%tmp186 = icmp eq i16 %tmp184, -32768 ; <i1> [#uses=1] %tmp186 = icmp eq i16 %tmp184, -32768 ; <i1> [#uses=1]
br i1 %tmp186, label %bb189, label %bb288 br i1 %tmp186, label %bb189, label %bb288
bb189: ; preds = %0 bb189: ; preds = %0
ret i16 %tmp180 ret i16 %tmp180
bb288: ; preds = %0 bb288: ; preds = %0
ret i16 32 ret i16 32
} }

llvm/test/CodeGen/X86/2008-06-25-VecISelBug.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | not grep pslldq ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
define void @t() nounwind { define void @t() nounwind {
; CHECK-LABEL: t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0.0E+0,0.0E+0,0.0E+0,1.0E+0]
; CHECK-NEXT: movaps %xmm0, 0
entry: entry:
%tmp1 = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > %tmp1 = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 0, i32 1, i32 4, i32 5 >
%tmp2 = insertelement <4 x float> %tmp1, float 1.000000e+00, i32 3 %tmp2 = insertelement <4 x float> %tmp1, float 1.000000e+00, i32 3
store <4 x float> %tmp2, <4 x float>* null, align 16 store <4 x float> %tmp2, <4 x float>* null, align 16
unreachable unreachable
} }

llvm/test/CodeGen/X86/2008-07-09-ELFSectionAttributes.ll

; RUN: llc < %s | grep ax ; RUN: llc < %s | FileCheck %s
; PR2024 ; PR2024
; CHECK: .init.text,"ax"
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu" target triple = "i386-pc-linux-gnu"
define i32 @foo(i32 %A, i32 %B) nounwind section ".init.text" { define i32 @foo(i32 %A, i32 %B) nounwind section ".init.text" {
entry: entry:
tail call i32 @bar( i32 %A, i32 %B ) nounwind ; <i32>:0 [#uses=1] tail call i32 @bar( i32 %A, i32 %B ) nounwind ; <i32>:0 [#uses=1]
ret i32 %0 ret i32 %0
} }
declare i32 @bar(i32, i32) declare i32 @bar(i32, i32)

llvm/test/CodeGen/X86/2008-07-11-SHLBy1.ll

; RUN: llc < %s -mtriple=x86_64-- -o - | not grep shr ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define i128 @sl(i128 %x) { define i128 @sl(i128 %x) {
; CHECK-LABEL: sl:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: shldq $1, %rdi, %rdx
; CHECK-NEXT: leaq (%rdi,%rdi), %rax
; CHECK-NEXT: retq
%t = shl i128 %x, 1 %t = shl i128 %x, 1
ret i128 %t ret i128 %t
} }

llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll

; RUN: llc -mtriple=x86_64-- < %s -o - | grep "cmpl \$[1], %" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- < %s | FileCheck %s
@.str = internal constant [4 x i8] c"%d\0A\00" @.str = internal constant [4 x i8] c"%d\0A\00"
declare i32 @printf(i8* noalias , ...) nounwind declare i32 @printf(i8* noalias , ...) nounwind
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movl $10271, %ebx # imm = 0x281F
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %forbody
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl $.str, %edi
; CHECK-NEXT: movl %ebx, %esi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq printf
; CHECK-NEXT: addl $-10, %ebx
; CHECK-NEXT: cmpl $1, %ebx
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %afterfor
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
entry: entry:
br label %forbody br label %forbody
forbody: forbody:
%i.0 = phi i32 [ 0, %entry ], [ %inc, %forbody ] ; <i32>[#uses=3] %i.0 = phi i32 [ 0, %entry ], [ %inc, %forbody ] ; <i32>[#uses=3]
%sub14 = sub i32 1027, %i.0 ; <i32> [#uses=1] %sub14 = sub i32 1027, %i.0 ; <i32> [#uses=1]
%mul15 = mul i32 %sub14, 10 ; <i32> [#uses=1] %mul15 = mul i32 %sub14, 10 ; <i32> [#uses=1]
%add166 = or i32 %mul15, 1 ; <i32> [#uses=1] * %add166 = or i32 %mul15, 1 ; <i32> [#uses=1] *
call i32 (i8*, ...) @printf( i8* noalias getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %add166 ) nounwind call i32 (i8*, ...) @printf( i8* noalias getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %add166 ) nounwind
%inc = add i32 %i.0, 1 ; <i32> [#uses=3] %inc = add i32 %i.0, 1 ; <i32> [#uses=3]
%cmp = icmp ne i32 %inc, 1027 ; <i1> [#uses=1] %cmp = icmp ne i32 %inc, 1027 ; <i1> [#uses=1]
br i1 %cmp, label %forbody, label %afterfor br i1 %cmp, label %forbody, label %afterfor
afterfor: ; preds = %forcond afterfor: ; preds = %forcond
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xorl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind { define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: ucomiss %xmm1, %xmm0
; CHECK-NEXT: setae %al
; CHECK-NEXT: retq
entry: entry:
tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
ret i32 %0 ret i32 %0
} }
declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone

llvm/test/CodeGen/X86/2008-09-25-sseregparm-1.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | grep movs | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | grep fld | count 2 ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
; check 'inreg' attribute for sse_regparm ; check 'inreg' attribute for sse_regparm
define inreg double @foo1() nounwind { define inreg double @foo1() nounwind {
; CHECK-LABEL: foo1:
; CHECK: # %bb.0:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: retl
ret double 1.0 ret double 1.0
} }
define inreg float @foo2() nounwind { define inreg float @foo2() nounwind {
; CHECK-LABEL: foo2:
; CHECK: # %bb.0:
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: retl
ret float 1.0 ret float 1.0
} }
define double @bar() nounwind { define double @bar() nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: fld1
; CHECK-NEXT: retl
ret double 1.0 ret double 1.0
} }
define float @bar2() nounwind { define float @bar2() nounwind {
; CHECK-LABEL: bar2:
; CHECK: # %bb.0:
; CHECK-NEXT: fld1
; CHECK-NEXT: retl
ret float 1.0 ret float 1.0
} }

llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mattr=-sse2,-sse3,-sse | FileCheck %s
; ModuleID = 'nan.bc' ; ModuleID = 'nan.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
; RUN: llc < %s -mattr=-sse2,-sse3,-sse | grep fldl
; This NaN should be shortened to a double (not a float). ; This NaN should be shortened to a double (not a float).
declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f) declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f)
define i32 @main() { define i32 @main() {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry_nan.main
; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldl LCPI0_0
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: retl
entry_nan.main: entry_nan.main:
call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFFC001234000000800) call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFFC001234000000800)
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/2008-10-06-x87ld-nan-2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; ModuleID = 'nan.bc' ; ModuleID = 'nan.bc'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-f80:32:32-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
; RUN: llc < %s -mattr=-sse2,-sse3,-sse | grep fldt | count 3 ; RUN: llc < %s -mattr=-sse2,-sse3,-sse | FileCheck %s
; it is not safe to shorten any of these NaNs. ; it is not safe to shorten any of these NaNs.
declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f) declare x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %f)
@_D3nan4rvale = global x86_fp80 0xK7FFF8001234000000000 ; <x86_fp80*> [#uses=1] @_D3nan4rvale = global x86_fp80 0xK7FFF8001234000000000 ; <x86_fp80*> [#uses=1]
define i32 @main() { define i32 @main() {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry_nan.main
; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: fldt __D3nan4rvale
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: fldt LCPI0_0
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: fldt LCPI0_1
; CHECK-NEXT: fstpt (%esp)
; CHECK-NEXT: calll __D3nan5printFeZv
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: retl
entry_nan.main: entry_nan.main:
%tmp = load x86_fp80, x86_fp80* @_D3nan4rvale ; <x86_fp80> [#uses=1] %tmp = load x86_fp80, x86_fp80* @_D3nan4rvale ; <x86_fp80> [#uses=1]
call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %tmp) call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 %tmp)
call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFF8001234000000000) call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFF8001234000000000)
call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFFC001234000000400) call x86_stdcallcc void @_D3nan5printFeZv(x86_fp80 0xK7FFFC001234000000400)
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/2008-10-24-FlippedCompare.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -o - | not grep "ucomiss[^,]*esp" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
define void @f(float %wt) { define void @f(float %wt) {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl $44
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: calll g
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm0, %xmm1
; CHECK-NEXT: retl
entry: entry:
%0 = fcmp ogt float %wt, 0.000000e+00 ; <i1> [#uses=1] %0 = fcmp ogt float %wt, 0.000000e+00 ; <i1> [#uses=1]
%1 = tail call i32 @g(i32 44) ; <i32> [#uses=3] %1 = tail call i32 @g(i32 44) ; <i32> [#uses=3]
%2 = inttoptr i32 %1 to i8* ; <i8*> [#uses=2] %2 = inttoptr i32 %1 to i8* ; <i8*> [#uses=2]
br i1 %0, label %bb, label %bb1 br i1 %0, label %bb, label %bb1
bb: ; preds = %entry bb: ; preds = %entry
ret void ret void
bb1: ; preds = %entry bb1: ; preds = %entry
ret void ret void
} }
declare i32 @g(i32) declare i32 @g(i32)

llvm/test/CodeGen/X86/2008-11-29-ULT-Sign.ll

; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep "jns" | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu" target triple = "i686-pc-linux-gnu"
define i32 @a(i32 %x) nounwind { define i32 @a(i32 %x) nounwind {
; CHECK-LABEL: a:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: jns .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: calll b
; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
entry: entry:
%cmp = icmp ult i32 %x, -2147483648 ; <i1> [#uses=1] %cmp = icmp ult i32 %x, -2147483648 ; <i1> [#uses=1]
br i1 %cmp, label %if.end, label %if.then br i1 %cmp, label %if.end, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%call = call i32 (...) @b() ; <i32> [#uses=0] %call = call i32 (...) @b() ; <i32> [#uses=0]
br label %if.end br label %if.end
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llvm/test/CodeGen/X86/2008-12-01-loop-iv-used-outside-loop.ll

; RUN: llc < %s -mtriple=i386-apple-darwin | not grep lea ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
; The inner loop should use [reg] addressing, not [reg+reg] addressing. ; The inner loop should use [reg] addressing, not [reg+reg] addressing.
; rdar://6403965 ; rdar://6403965
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5" target triple = "i386-apple-darwin9.5"
define i8* @test(i8* %Q, i32* %L) nounwind { define i8* @test(i8* %Q, i32* %L) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: jmp LBB0_2
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_1: ## %bb
; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: incl %eax
; CHECK-NEXT: LBB0_2: ## %bb1
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movzbl (%eax), %ecx
; CHECK-NEXT: cmpb $12, %cl
; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: ## %bb.3: ## %bb1
; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: cmpb $42, %cl
; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: ## %bb.4: ## %bb3
; CHECK-NEXT: movb $4, 2(%eax)
; CHECK-NEXT: retl
entry: entry:
br label %bb1 br label %bb1
bb: ; preds = %bb1, %bb1 bb: ; preds = %bb1, %bb1
%indvar.next = add i32 %P.0.rec, 1 ; <i32> [#uses=1] %indvar.next = add i32 %P.0.rec, 1 ; <i32> [#uses=1]
br label %bb1 br label %bb1
bb1: ; preds = %bb, %entry bb1: ; preds = %bb, %entry
Show All 14 Lines

llvm/test/CodeGen/X86/2008-12-02-dagcombine-1.ll

; RUN: llc < %s | grep "(%esp)" | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5" target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P ; a - a should be found and removed, leaving refs to only L and P
define i8* @test(i8* %a, i8* %L, i8* %P) nounwind { define i8* @test(i8* %a, i8* %L, i8* %P) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: addl $-2, %eax
; CHECK-NEXT: retl
entry: entry:
%0 = ptrtoint i8* %a to i32 %0 = ptrtoint i8* %a to i32
%1 = sub i32 -2, %0 %1 = sub i32 -2, %0
%2 = ptrtoint i8* %P to i32 %2 = ptrtoint i8* %P to i32
%3 = sub i32 0, %2 %3 = sub i32 0, %2
%4 = ptrtoint i8* %L to i32 %4 = ptrtoint i8* %L to i32
%5 = add i32 %4, %3 %5 = add i32 %4, %3
%6 = add i32 %5, %1 ; <i32> [#uses=1] %6 = add i32 %5, %1 ; <i32> [#uses=1]
%7 = getelementptr i8, i8* %a, i32 %6 ; <i8*> [#uses=1] %7 = getelementptr i8, i8* %a, i32 %6 ; <i8*> [#uses=1]
br label %return br label %return
return: ; preds = %bb3 return: ; preds = %bb3
ret i8* %7 ret i8* %7
} }

llvm/test/CodeGen/X86/2008-12-02-dagcombine-2.ll

; RUN: llc < %s | grep "(%esp)" | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5" target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P ; a - a should be found and removed, leaving refs to only L and P
define i8* @test(i8* %a, i8* %L, i8* %P) nounwind { define i8* @test(i8* %a, i8* %L, i8* %P) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: retl
entry: entry:
%0 = ptrtoint i8* %a to i32 %0 = ptrtoint i8* %a to i32
%1 = ptrtoint i8* %P to i32 %1 = ptrtoint i8* %P to i32
%2 = sub i32 %1, %0 %2 = sub i32 %1, %0
%3 = ptrtoint i8* %L to i32 %3 = ptrtoint i8* %L to i32
%4 = sub i32 %2, %3 ; <i32> [#uses=1] %4 = sub i32 %2, %3 ; <i32> [#uses=1]
%5 = getelementptr i8, i8* %a, i32 %4 ; <i8*> [#uses=1] %5 = getelementptr i8, i8* %a, i32 %4 ; <i8*> [#uses=1]
br label %return br label %return
return: ; preds = %bb3 return: ; preds = %bb3
ret i8* %5 ret i8* %5
} }

llvm/test/CodeGen/X86/2008-12-02-dagcombine-3.ll

; RUN: llc < %s | grep add | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | grep sub | grep -v subsections | count 1 ; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5" target triple = "i386-apple-darwin9.5"
; this should be rearranged to have two +s and one - ; this should be rearranged to have two +s and one -
define i32 @test(i8* %a, i8* %L, i8* %P) nounwind { define i32 @test(i8* %a, i8* %L, i8* %P) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: addl $-2, %eax
; CHECK-NEXT: retl
entry: entry:
%0 = ptrtoint i8* %P to i32 %0 = ptrtoint i8* %P to i32
%1 = sub i32 -2, %0 %1 = sub i32 -2, %0
%2 = ptrtoint i8* %L to i32 %2 = ptrtoint i8* %L to i32
%3 = ptrtoint i8* %a to i32 %3 = ptrtoint i8* %a to i32
%4 = sub i32 %2, %3 ; <i32> [#uses=1] %4 = sub i32 %2, %3 ; <i32> [#uses=1]
%5 = add i32 %1, %4 ; <i32> [#uses=1] %5 = add i32 %1, %4 ; <i32> [#uses=1]
br label %return br label %return
return: ; preds = %bb3 return: ; preds = %bb3
ret i32 %5 ret i32 %5
} }

llvm/test/CodeGen/X86/2008-12-16-dagcombine-4.ll

; RUN: llc < %s | grep "(%esp)" | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5" target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P ; a - a should be found and removed, leaving refs to only L and P
define i32 @test(i32 %a, i32 %L, i32 %P) nounwind { define i32 @test(i32 %a, i32 %L, i32 %P) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: retl
entry: entry:
%0 = sub i32 %a, %L %0 = sub i32 %a, %L
%1 = add i32 %P, %0 %1 = add i32 %P, %0
%2 = sub i32 %1, %a %2 = sub i32 %1, %a
br label %return br label %return
return: ; preds = %bb3 return: ; preds = %bb3
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/X86/2008-12-22-dagcombine-5.ll

; RUN: llc < %s | grep "(%esp)" | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5" target triple = "i386-apple-darwin9.5"
; -(-a) - a should be found and removed, leaving refs to only L and P ; -(-a) - a should be found and removed, leaving refs to only L and P
define i32 @test(i32 %a, i32 %L, i32 %P) nounwind { define i32 @test(i32 %a, i32 %L, i32 %P) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: retl
entry: entry:
%0 = sub i32 %L, %a %0 = sub i32 %L, %a
%1 = sub i32 %P, %0 %1 = sub i32 %P, %0
%2 = sub i32 %1, %a %2 = sub i32 %1, %a
br label %return br label %return
return: ; preds = %bb3 return: ; preds = %bb3
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/X86/2008-12-23-crazy-address.ll

; RUN: llc < %s -mtriple=i686-- -relocation-model=static | grep "lea.*X.*esp" | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -relocation-model=static | FileCheck %s
@X = external global [0 x i32] @X = external global [0 x i32]
define void @foo() nounwind { define void @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: calll frob
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: leal X(%esp), %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: calll borf
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl
entry: entry:
%Y = alloca i32 %Y = alloca i32
call void @frob(i32* %Y) nounwind call void @frob(i32* %Y) nounwind
%Y3 = bitcast i32* %Y to i8* %Y3 = bitcast i32* %Y to i8*
%ctg2 = getelementptr i8, i8* %Y3, i32 ptrtoint ([0 x i32]* @X to i32) %ctg2 = getelementptr i8, i8* %Y3, i32 ptrtoint ([0 x i32]* @X to i32)
%0 = ptrtoint i8* %ctg2 to i32 %0 = ptrtoint i8* %ctg2 to i32
call void @borf(i32 %0) nounwind call void @borf(i32 %0) nounwind
ret void ret void
} }
define void @bar(i32 %i) nounwind { define void @bar(i32 %i) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $40, %esp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: calll frob
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: leal X(%esp,%esi,4), %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: calll borf
; CHECK-NEXT: addl $44, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%Y = alloca [10 x i32] %Y = alloca [10 x i32]
%0 = getelementptr [10 x i32], [10 x i32]* %Y, i32 0, i32 0 %0 = getelementptr [10 x i32], [10 x i32]* %Y, i32 0, i32 0
call void @frob(i32* %0) nounwind call void @frob(i32* %0) nounwind
%1 = getelementptr [0 x i32], [0 x i32]* @X, i32 0, i32 %i %1 = getelementptr [0 x i32], [0 x i32]* @X, i32 0, i32 %i
%2 = getelementptr [10 x i32], [10 x i32]* %Y, i32 0, i32 0 %2 = getelementptr [10 x i32], [10 x i32]* %Y, i32 0, i32 0
%3 = ptrtoint i32* %2 to i32 %3 = ptrtoint i32* %2 to i32
%4 = bitcast i32* %1 to i8* %4 = bitcast i32* %1 to i8*
Show All 9 Lines

llvm/test/CodeGen/X86/2008-12-23-dagcombine-6.ll

; RUN: llc < %s | grep "(%esp)" | count 4 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.5" target triple = "i386-apple-darwin9.5"
; a - a should be found and removed, leaving refs to only L and P ; a - a should be found and removed, leaving refs to only L and P
define i32 @test(i32 %a, i32 %L, i32 %P) nounwind { define i32 @test(i32 %a, i32 %L, i32 %P) nounwind {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: retl
entry: entry:
%0 = add i32 %a, %L %0 = add i32 %a, %L
%1 = add i32 %P, %0 %1 = add i32 %P, %0
%2 = sub i32 %1, %a %2 = sub i32 %1, %a
br label %return br label %return
return: ; preds = %bb3 return: ; preds = %bb3
ret i32 %2 ret i32 %2
} }
define i32 @test2(i32 %a, i32 %L, i32 %P) nounwind { define i32 @test2(i32 %a, i32 %L, i32 %P) nounwind {
; CHECK-LABEL: test2:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: retl
entry: entry:
%0 = add i32 %L, %a %0 = add i32 %L, %a
%1 = add i32 %P, %0 %1 = add i32 %P, %0
%2 = sub i32 %1, %a %2 = sub i32 %1, %a
br label %return br label %return
return: ; preds = %bb3 return: ; preds = %bb3
ret i32 %2 ret i32 %2
} }

llvm/test/CodeGen/X86/2009-01-31-BigShift.ll

; RUN: llc < %s -mtriple=i686-- | not grep and ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; PR3401 ; PR3401
define void @x(i288 %i) nounwind { define void @x(i288 %i) nounwind {
; CHECK-LABEL: x:
; CHECK: # %bb.0:
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: calll add
; CHECK-NEXT: addl $36, %esp
; CHECK-NEXT: retl
call void @add(i288 %i) call void @add(i288 %i)
ret void ret void
} }
declare void @add(i288) declare void @add(i288)

llvm/test/CodeGen/X86/2009-01-31-BigShift2.ll

; RUN: llc < %s -mtriple=i686-- | grep "mov.*56" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; PR3449 ; PR3449
define void @test(<8 x double>* %P, i64* %Q) nounwind { define void @test(<8 x double>* %P, i64* %Q) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl 56(%ecx), %edx
; CHECK-NEXT: movl 60(%ecx), %ecx
; CHECK-NEXT: movl %ecx, 4(%eax)
; CHECK-NEXT: movl %edx, (%eax)
; CHECK-NEXT: retl
%A = load <8 x double>, <8 x double>* %P ; <<8 x double>> [#uses=1] %A = load <8 x double>, <8 x double>* %P ; <<8 x double>> [#uses=1]
%B = bitcast <8 x double> %A to i512 ; <i512> [#uses=1] %B = bitcast <8 x double> %A to i512 ; <i512> [#uses=1]
%C = lshr i512 %B, 448 ; <i512> [#uses=1] %C = lshr i512 %B, 448 ; <i512> [#uses=1]
%D = trunc i512 %C to i64 ; <i64> [#uses=1] %D = trunc i512 %C to i64 ; <i64> [#uses=1]
store volatile i64 %D, i64* %Q store volatile i64 %D, i64* %Q
ret void ret void
} }

llvm/test/CodeGen/X86/2009-02-21-ExtWeakInitializer.ll

; RUN: llc < %s | grep weak | count 3 ; RUN: llc < %s | FileCheck %s
; PR3629 ; PR3629
; CHECK: weak
; CHECK-NEXT: weak
; CHECK-NEXT: weak
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "x86_64-unknown-freebsd7.1" target triple = "x86_64-unknown-freebsd7.1"
module asm ".ident\09\22$FreeBSD$\22" module asm ".ident\09\22$FreeBSD$\22"
%struct.anon = type <{ %struct.uart_devinfo* }> %struct.anon = type <{ %struct.uart_devinfo* }>
%struct.lock_object = type <{ i8*, i32, i32, %struct.witness* }> %struct.lock_object = type <{ i8*, i32, i32, %struct.witness* }>
%struct.mtx = type <{ %struct.lock_object, i64 }> %struct.mtx = type <{ %struct.lock_object, i64 }>
%struct.uart_bas = type <{ i64, i64, i32, i32, i32, i8, i8, i8, i8 }> %struct.uart_bas = type <{ i64, i64, i32, i32, i32, i8, i8, i8, i8 }>
%struct.uart_class = type opaque %struct.uart_class = type opaque
Show All 9 Lines

llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; REQUIRES: asserts ; REQUIRES: asserts
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 -relocation-model=static -o /dev/null -stats -info-output-file - > %t ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 -relocation-model=static | FileCheck %s
; RUN: not grep spill %t
; RUN: not grep "%rsp" %t
; RUN: not grep "%rbp" %t
; The register-pressure scheduler should be able to schedule this in a ; The register-pressure scheduler should be able to schedule this in a
; way that does not require spills. ; way that does not require spills.
@X = external global i64 ; <i64*> [#uses=25] @X = external global i64 ; <i64*> [#uses=25]
define fastcc i64 @foo() nounwind { define fastcc i64 @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %r15
; CHECK-NEXT: pushq %r14
; CHECK-NEXT: pushq %r12
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movq {{.*}}(%rip), %r8
; CHECK-NEXT: movq {{.*}}(%rip), %r10
; CHECK-NEXT: movq {{.*}}(%rip), %r9
; CHECK-NEXT: movq {{.*}}(%rip), %r12
; CHECK-NEXT: movq {{.*}}(%rip), %r15
; CHECK-NEXT: movq {{.*}}(%rip), %r14
; CHECK-NEXT: movq {{.*}}(%rip), %r11
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: addq %r15, %rdx
; CHECK-NEXT: movq {{.*}}(%rip), %rsi
; CHECK-NEXT: bswapq %rsi
; CHECK-NEXT: leaq (%r11,%r14), %rbx
; CHECK-NEXT: addq %r15, %rbx
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: leaq (%r9,%r10), %rsi
; CHECK-NEXT: leaq (%rsi,%r8), %rdx
; CHECK-NEXT: addq %rsi, %rdx
; CHECK-NEXT: movq {{.*}}(%rip), %rdi
; CHECK-NEXT: addq %rbx, %r12
; CHECK-NEXT: addq %r8, %rdx
; CHECK-NEXT: bswapq %rdi
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: leaq (%r15,%r14), %rsi
; CHECK-NEXT: addq %r12, %rsi
; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: leaq (%r10,%r8), %rbx
; CHECK-NEXT: leaq (%rdx,%rbx), %rsi
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r12, %rdi
; CHECK-NEXT: addq %rdi, %r9
; CHECK-NEXT: addq %rdx, %rsi
; CHECK-NEXT: addq %rdi, %rsi
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r12,%r15), %rdi
; CHECK-NEXT: addq %r9, %rdi
; CHECK-NEXT: addq %r14, %rbx
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: leaq (%rdx,%r8), %rax
; CHECK-NEXT: leaq (%rsi,%rax), %rdi
; CHECK-NEXT: addq %rax, %rdi
; CHECK-NEXT: movq {{.*}}(%rip), %rcx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: bswapq %rcx
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: leaq (%r9,%r12), %rax
; CHECK-NEXT: addq %r10, %rax
; CHECK-NEXT: addq %r15, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: leaq (%rdi,%rbx), %r11
; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r10, %rcx
; CHECK-NEXT: addq %rcx, %r8
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: addq %rcx, %r11
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r10,%r9), %rcx
; CHECK-NEXT: addq %r8, %rcx
; CHECK-NEXT: addq %r12, %rbx
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: leaq (%r11,%rax), %r14
; CHECK-NEXT: addq %rax, %r14
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: addq %r11, %r14
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: addq %rbx, %r14
; CHECK-NEXT: leaq (%r8,%r10), %rbx
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %r9, %rax
; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%r11,%rdi), %rbx
; CHECK-NEXT: leaq (%r14,%rbx), %r9
; CHECK-NEXT: addq %rbx, %r9
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: addq %r14, %r9
; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%rdx,%r8), %rax
; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: addq %r10, %rbx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%r14,%r11), %rax
; CHECK-NEXT: leaq (%r9,%rax), %r10
; CHECK-NEXT: addq %rax, %r10
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: addq %r9, %r10
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: addq %r8, %rax
; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%r9,%r14), %rbx
; CHECK-NEXT: leaq (%r10,%rbx), %r8
; CHECK-NEXT: addq %rbx, %r8
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: addq %rax, %r11
; CHECK-NEXT: addq %r10, %r8
; CHECK-NEXT: addq %rax, %r8
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%r10,%r9), %rax
; CHECK-NEXT: leaq (%r8,%rax), %r15
; CHECK-NEXT: addq %rax, %r15
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: addq %r11, %rbx
; CHECK-NEXT: addq %rbx, %r14
; CHECK-NEXT: addq %r8, %r15
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: addq %rbx, %r15
; CHECK-NEXT: leaq (%r11,%rdi), %rbx
; CHECK-NEXT: addq %r14, %rbx
; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%r8,%r10), %rbx
; CHECK-NEXT: leaq (%r15,%rbx), %rsi
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r14, %rax
; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: addq %r15, %rsi
; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r14,%r11), %rax
; CHECK-NEXT: addq %r9, %rax
; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%r15,%r8), %rax
; CHECK-NEXT: leaq (%rsi,%rax), %r12
; CHECK-NEXT: addq %rax, %r12
; CHECK-NEXT: movq {{.*}}(%rip), %rcx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %rsi, %r12
; CHECK-NEXT: bswapq %rcx
; CHECK-NEXT: addq %rbx, %r12
; CHECK-NEXT: leaq (%r9,%r14), %rax
; CHECK-NEXT: addq %r10, %rax
; CHECK-NEXT: addq %r11, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%r15), %rbx
; CHECK-NEXT: leaq (%r12,%rbx), %rax
; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r10, %rcx
; CHECK-NEXT: addq %rcx, %r8
; CHECK-NEXT: addq %r12, %rax
; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r10,%r9), %rcx
; CHECK-NEXT: addq %r8, %rcx
; CHECK-NEXT: addq %r14, %rbx
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: leaq (%r12,%rsi), %rdx
; CHECK-NEXT: leaq (%rax,%rdx), %rcx
; CHECK-NEXT: addq %rdx, %rcx
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rbx, %r15
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: bswapq %rdx
; CHECK-NEXT: addq %rbx, %rcx
; CHECK-NEXT: leaq (%r8,%r10), %rbx
; CHECK-NEXT: addq %r15, %rbx
; CHECK-NEXT: addq %r9, %rdx
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: leaq (%rax,%r12), %r9
; CHECK-NEXT: leaq (%rcx,%r9), %rbx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %r15, %rdx
; CHECK-NEXT: addq %rdx, %rsi
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: bswapq %rdx
; CHECK-NEXT: addq %r10, %rdx
; CHECK-NEXT: leaq (%r15,%r8), %rdi
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: addq %rdi, %rdx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: leaq (%rbx,%rcx), %rdi
; CHECK-NEXT: addq %rcx, %rdi
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: addq %rsi, %rdx
; CHECK-NEXT: addq %rdx, %r12
; CHECK-NEXT: addq %rdx, %rdi
; CHECK-NEXT: addq %r15, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: addq %r8, %rax
; CHECK-NEXT: addq %r12, %rsi
; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: addq %r12, %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r12
; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15
; CHECK-NEXT: retq
%tmp = load volatile i64, i64* @X ; <i64> [#uses=7] %tmp = load volatile i64, i64* @X ; <i64> [#uses=7]
%tmp1 = load volatile i64, i64* @X ; <i64> [#uses=5] %tmp1 = load volatile i64, i64* @X ; <i64> [#uses=5]
%tmp2 = load volatile i64, i64* @X ; <i64> [#uses=3] %tmp2 = load volatile i64, i64* @X ; <i64> [#uses=3]
%tmp3 = load volatile i64, i64* @X ; <i64> [#uses=1] %tmp3 = load volatile i64, i64* @X ; <i64> [#uses=1]
%tmp4 = load volatile i64, i64* @X ; <i64> [#uses=5] %tmp4 = load volatile i64, i64* @X ; <i64> [#uses=5]
%tmp5 = load volatile i64, i64* @X ; <i64> [#uses=3] %tmp5 = load volatile i64, i64* @X ; <i64> [#uses=3]
%tmp6 = load volatile i64, i64* @X ; <i64> [#uses=2] %tmp6 = load volatile i64, i64* @X ; <i64> [#uses=2]
%tmp7 = load volatile i64, i64* @X ; <i64> [#uses=1] %tmp7 = load volatile i64, i64* @X ; <i64> [#uses=1]
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2009-04-12-picrel.ll

; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -relocation-model=static -code-model=small > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep leaq %t | count 1 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -relocation-model=static -code-model=small | FileCheck %s
@dst = external global [131072 x i32] @dst = external global [131072 x i32]
@ptr = external global i32* @ptr = external global i32*
define void @off01(i64 %i) nounwind { define void @off01(i64 %i) nounwind {
; CHECK-LABEL: off01:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: leaq dst+64(,%rdi,4), %rax
; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: retq
entry: entry:
%.sum = add i64 %i, 16 %.sum = add i64 %i, 16
%0 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %.sum %0 = getelementptr [131072 x i32], [131072 x i32]* @dst, i64 0, i64 %.sum
store i32* %0, i32** @ptr, align 8 store i32* %0, i32** @ptr, align 8
ret void ret void
} }

llvm/test/CodeGen/X86/2009-04-14-IllegalRegs.ll

; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=fast | not grep sil ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=fast | FileCheck %s
; rdar://6787136 ; rdar://6787136
%struct.X = type { i8, [32 x i8] } %struct.X = type { i8, [32 x i8] }
@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @z to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @z to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define i32 @z() nounwind ssp { define i32 @z() nounwind ssp {
; CHECK-LABEL: z:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $144, %esp
; CHECK-NEXT: movl L___stack_chk_guard$non_lazy_ptr, %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movb $48, {{[0-9]+}}(%esp)
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK-NEXT: movb %cl, {{[0-9]+}}(%esp)
; CHECK-NEXT: movb $15, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: movl $8, %edx
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %edx, %ecx
; CHECK-NEXT: movl %eax, %edi
; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: addl $36, %ecx
; CHECK-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl %edx, %ecx
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi ## 4-byte Reload
; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
; CHECK-NEXT: movb {{[0-9]+}}(%esp), %bl
; CHECK-NEXT: movb %bl, 32(%eax)
; CHECK-NEXT: movb %bl, 68(%eax)
; CHECK-NEXT: calll _f
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: ## %bb.1: ## %return
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl L___stack_chk_guard$non_lazy_ptr, %ecx
; CHECK-NEXT: movl (%ecx), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: cmpl %edx, %ecx
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: jne LBB0_3
; CHECK-NEXT: ## %bb.2: ## %SP_return
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: addl $144, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_3: ## %CallStackCheckFailBlk
; CHECK-NEXT: calll ___stack_chk_fail
; CHECK-NEXT: ud2
entry: entry:
%retval = alloca i32 ; <i32*> [#uses=2] %retval = alloca i32 ; <i32*> [#uses=2]
%xxx = alloca %struct.X ; <%struct.X*> [#uses=6] %xxx = alloca %struct.X ; <%struct.X*> [#uses=6]
%0 = alloca i32 ; <i32*> [#uses=2] %0 = alloca i32 ; <i32*> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%1 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1] %1 = getelementptr %struct.X, %struct.X* %xxx, i32 0, i32 1 ; <[32 x i8]*> [#uses=1]
%2 = getelementptr [32 x i8], [32 x i8]* %1, i32 0, i32 31 ; <i8*> [#uses=1] %2 = getelementptr [32 x i8], [32 x i8]* %1, i32 0, i32 31 ; <i8*> [#uses=1]
store i8 48, i8* %2, align 1 store i8 48, i8* %2, align 1
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llvm/test/CodeGen/X86/2009-04-25-CoalescerBug.ll

; RUN: llc < %s -mtriple=x86_64-- | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; rdar://6806252 ; rdar://6806252
define i64 @test(i32* %tmp13) nounwind { define i64 @test(i32* %tmp13) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %while.cond
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: testb $1, %al
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %while.end
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: retq
entry: entry:
br label %while.cond br label %while.cond
while.cond: ; preds = %while.cond, %entry while.cond: ; preds = %while.cond, %entry
%tmp15 = load i32, i32* %tmp13 ; <i32> [#uses=2] %tmp15 = load i32, i32* %tmp13 ; <i32> [#uses=2]
%bf.lo = lshr i32 %tmp15, 1 ; <i32> [#uses=1] %bf.lo = lshr i32 %tmp15, 1 ; <i32> [#uses=1]
%bf.lo.cleared = and i32 %bf.lo, 2147483647 ; <i32> [#uses=1] %bf.lo.cleared = and i32 %bf.lo, 2147483647 ; <i32> [#uses=1]
%conv = zext i32 %bf.lo.cleared to i64 ; <i64> [#uses=1] %conv = zext i32 %bf.lo.cleared to i64 ; <i64> [#uses=1]
%bf.lo.cleared25 = and i32 %tmp15, 1 ; <i32> [#uses=1] %bf.lo.cleared25 = and i32 %tmp15, 1 ; <i32> [#uses=1]
%tobool = icmp ne i32 %bf.lo.cleared25, 0 ; <i1> [#uses=1] %tobool = icmp ne i32 %bf.lo.cleared25, 0 ; <i1> [#uses=1]
br i1 %tobool, label %while.cond, label %while.end br i1 %tobool, label %while.cond, label %while.end
while.end: ; preds = %while.cond while.end: ; preds = %while.cond
ret i64 %conv ret i64 %conv
} }

llvm/test/CodeGen/X86/2009-04-29-IndirectDestOperands.ll

; RUN: llc < %s | grep "movl.*%ebx, 8(%esi)" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.0" target triple = "i386-apple-darwin9.0"
define void @cpuid(i32* %data) nounwind { define void @cpuid(i32* %data) nounwind {
; CHECK-LABEL: cpuid:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl 20(%esi), %eax
; CHECK-NEXT: movl 24(%esi), %ebx
; CHECK-NEXT: movl 28(%esi), %ecx
; CHECK-NEXT: movl 32(%esi), %edx
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: cpuid
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: movl %ebx, 8(%esi)
; CHECK-NEXT: movl %ecx, 12(%esi)
; CHECK-NEXT: movl %edx, 16(%esi)
; CHECK-NEXT: movl %eax, 4(%esi)
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: retl
entry: entry:
%arrayidx = getelementptr i32, i32* %data, i32 1 ; <i32*> [#uses=1] %arrayidx = getelementptr i32, i32* %data, i32 1 ; <i32*> [#uses=1]
%arrayidx2 = getelementptr i32, i32* %data, i32 2 ; <i32*> [#uses=1] %arrayidx2 = getelementptr i32, i32* %data, i32 2 ; <i32*> [#uses=1]
%arrayidx4 = getelementptr i32, i32* %data, i32 3 ; <i32*> [#uses=1] %arrayidx4 = getelementptr i32, i32* %data, i32 3 ; <i32*> [#uses=1]
%arrayidx6 = getelementptr i32, i32* %data, i32 4 ; <i32*> [#uses=1] %arrayidx6 = getelementptr i32, i32* %data, i32 4 ; <i32*> [#uses=1]
%arrayidx8 = getelementptr i32, i32* %data, i32 5 ; <i32*> [#uses=1] %arrayidx8 = getelementptr i32, i32* %data, i32 5 ; <i32*> [#uses=1]
%tmp9 = load i32, i32* %arrayidx8 ; <i32> [#uses=1] %tmp9 = load i32, i32* %arrayidx8 ; <i32> [#uses=1]
%arrayidx11 = getelementptr i32, i32* %data, i32 6 ; <i32*> [#uses=1] %arrayidx11 = getelementptr i32, i32* %data, i32 6 ; <i32*> [#uses=1]
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llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll

; RUN: llc < %s -mtriple=x86_64-- | not grep "movzbl %[abcd]h," ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define void @BZ2_bzDecompress_bb5_2E_outer_bb35_2E_i_bb54_2E_i(i32*, i32 %c_nblock_used.2.i, i32 %.reload51, i32* %.out, i32* %.out1, i32* %.out2, i32* %.out3) nounwind { define void @BZ2_bzDecompress_bb5_2E_outer_bb35_2E_i_bb54_2E_i(i32*, i32 %c_nblock_used.2.i, i32 %.reload51, i32* %.out, i32* %.out1, i32* %.out2, i32* %.out3) nounwind {
; CHECK-LABEL: BZ2_bzDecompress_bb5_2E_outer_bb35_2E_i_bb54_2E_i:
; CHECK: # %bb.0: # %newFuncRoot
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %r10
; CHECK-NEXT: movl %edx, %edx
; CHECK-NEXT: movl (%rdi,%rdx,4), %edx
; CHECK-NEXT: movzbl %dl, %eax
; CHECK-NEXT: shrq $6, %rdx
; CHECK-NEXT: andl $67108860, %edx # imm = 0x3FFFFFC
; CHECK-NEXT: addl $4, %eax
; CHECK-NEXT: movl (%rdi,%rdx), %edx
; CHECK-NEXT: movzbl %dl, %edi
; CHECK-NEXT: shrl $8, %edx
; CHECK-NEXT: addl $5, %esi
; CHECK-NEXT: movl %eax, (%rcx)
; CHECK-NEXT: movl %edi, (%r8)
; CHECK-NEXT: movl %edx, (%r9)
; CHECK-NEXT: movl %esi, (%r10)
; CHECK-NEXT: retq
newFuncRoot: newFuncRoot:
br label %bb54.i br label %bb54.i
bb35.i.backedge.exitStub: ; preds = %bb54.i bb35.i.backedge.exitStub: ; preds = %bb54.i
store i32 %6, i32* %.out store i32 %6, i32* %.out
store i32 %10, i32* %.out1 store i32 %10, i32* %.out1
store i32 %11, i32* %.out2 store i32 %11, i32* %.out2
store i32 %12, i32* %.out3 store i32 %12, i32* %.out3
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llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll

; RUN: llc < %s -tailcallopt -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep fstpt ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -tailcallopt -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep xmm ; RUN: llc < %s -tailcallopt -mattr=+sse2 -mtriple=x86_64-apple-darwin | FileCheck %s
; Check that x86-64 tail calls support x86_fp80 and v2f32 types. (Tail call ; Check that x86-64 tail calls support x86_fp80 and v2f32 types. (Tail call
; calling convention out of sync with standard c calling convention on x86_64) ; calling convention out of sync with standard c calling convention on x86_64)
; Bug 4278. ; Bug 4278.
declare fastcc double @tailcallee(x86_fp80, <2 x float>) declare fastcc double @tailcallee(x86_fp80, <2 x float>)
define fastcc double @tailcall() { define fastcc double @tailcall() {
; CHECK-LABEL: tailcall:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fld1
; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps {{.*#+}} xmm0 = <1.0E+0,1.0E+0,u,u>
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: jmp _tailcallee ## TAILCALL
entry: entry:
%tmp = fpext float 1.000000e+00 to x86_fp80 %tmp = fpext float 1.000000e+00 to x86_fp80
%tmp2 = tail call fastcc double @tailcallee( x86_fp80 %tmp, <2 x float> <float 1.000000e+00, float 1.000000e+00>) %tmp2 = tail call fastcc double @tailcallee( x86_fp80 %tmp, <2 x float> <float 1.000000e+00, float 1.000000e+00>)
ret double %tmp2 ret double %tmp2
} }

llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll

; RUN: llc < %s -mtriple=i686-- -tailcallopt | not grep TAILCALL ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -tailcallopt | FileCheck %s
; Bug 4396. This tail call can NOT be optimized. ; Bug 4396. This tail call can NOT be optimized.
declare fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() nounwind declare fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() nounwind
define fastcc i8* @_D3gcx2GC12callocNoSyncMFmkZPv() nounwind { define fastcc i8* @_D3gcx2GC12callocNoSyncMFmkZPv() nounwind {
; CHECK-LABEL: _D3gcx2GC12callocNoSyncMFmkZPv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: calll _D3gcx2GC12mallocNoSyncMFmkZPv
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl $2
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: calll memset
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%tmp6 = tail call fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() ; <i8*> [#uses=2] %tmp6 = tail call fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() ; <i8*> [#uses=2]
%tmp9 = tail call i8* @memset(i8* %tmp6, i32 0, i64 2) ; <i8*> [#uses=0] %tmp9 = tail call i8* @memset(i8* %tmp6, i32 0, i64 2) ; <i8*> [#uses=0]
ret i8* %tmp6 ret i8* %tmp6
} }
declare i8* @memset(i8*, i32, i64) declare i8* @memset(i8*, i32, i64)

llvm/test/CodeGen/X86/2009-08-12-badswitch.ll

; RUN: llc < %s | grep LJT ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin10" target triple = "x86_64-apple-darwin10"
declare void @f1() nounwind readnone declare void @f1() nounwind readnone
declare void @f2() nounwind readnone declare void @f2() nounwind readnone
declare void @f3() nounwind readnone declare void @f3() nounwind readnone
declare void @f4() nounwind readnone declare void @f4() nounwind readnone
declare void @f5() nounwind readnone declare void @f5() nounwind readnone
Show All 15 Lines
declare void @f21() nounwind readnone declare void @f21() nounwind readnone
declare void @f22() nounwind readnone declare void @f22() nounwind readnone
declare void @f23() nounwind readnone declare void @f23() nounwind readnone
declare void @f24() nounwind readnone declare void @f24() nounwind readnone
declare void @f25() nounwind readnone declare void @f25() nounwind readnone
declare void @f26() nounwind readnone declare void @f26() nounwind readnone
define internal fastcc i32 @foo(i64 %bar) nounwind ssp { define internal fastcc i32 @foo(i64 %bar) nounwind ssp {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: addq $-2, %rdi
; CHECK-NEXT: cmpq $25, %rdi
; CHECK-NEXT: ja LBB0_2
; CHECK-NEXT: ## %bb.1: ## %bb49
; CHECK-NEXT: leaq {{.*}}(%rip), %rax
; CHECK-NEXT: movslq (%rax,%rdi,4), %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: jmpq *%rcx
; CHECK-NEXT: LBB0_3: ## %RRETURN_6
; CHECK-NEXT: callq _f2
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_2: ## %RETURN
; CHECK-NEXT: callq _f1
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_4: ## %RRETURN_7
; CHECK-NEXT: callq _f3
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_5: ## %RRETURN_14
; CHECK-NEXT: callq _f4
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_6: ## %RRETURN_15
; CHECK-NEXT: callq _f5
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_7: ## %RRETURN_16
; CHECK-NEXT: callq _f6
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_8: ## %RRETURN_17
; CHECK-NEXT: callq _f7
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_9: ## %RRETURN_18
; CHECK-NEXT: callq _f8
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_10: ## %RRETURN_19
; CHECK-NEXT: callq _f9
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_11: ## %RRETURN_20
; CHECK-NEXT: callq _f10
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_12: ## %RRETURN_21
; CHECK-NEXT: callq _f11
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_13: ## %RRETURN_22
; CHECK-NEXT: callq _f12
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_14: ## %RRETURN_24
; CHECK-NEXT: callq _f13
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_15: ## %RRETURN_26
; CHECK-NEXT: callq _f14
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_16: ## %RRETURN_27
; CHECK-NEXT: callq _f15
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_17: ## %RRETURN_28
; CHECK-NEXT: callq _f16
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_18: ## %RRETURN_29
; CHECK-NEXT: callq _f17
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_19: ## %RRETURN_30
; CHECK-NEXT: callq _f18
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_20: ## %RRETURN_31
; CHECK-NEXT: callq _f19
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_21: ## %RRETURN_38
; CHECK-NEXT: callq _f20
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_22: ## %RRETURN_40
; CHECK-NEXT: callq _f21
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_23: ## %RRETURN_42
; CHECK-NEXT: callq _f22
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_24: ## %RRETURN_44
; CHECK-NEXT: callq _f23
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_25: ## %RRETURN_48
; CHECK-NEXT: callq _f24
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_26: ## %RRETURN_52
; CHECK-NEXT: callq _f25
; CHECK-NEXT: jmp LBB0_28
; CHECK-NEXT: LBB0_27: ## %RRETURN_1
; CHECK-NEXT: callq _f26
; CHECK-NEXT: LBB0_28: ## %EXIT
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
; CHECK-NEXT: .p2align 2, 0x90
; CHECK-NEXT: .data_region jt32
; CHECK-NEXT: .set L0_0_set_3, LBB0_3-LJTI0_0
; CHECK-NEXT: .set L0_0_set_4, LBB0_4-LJTI0_0
; CHECK-NEXT: .set L0_0_set_5, LBB0_5-LJTI0_0
; CHECK-NEXT: .set L0_0_set_6, LBB0_6-LJTI0_0
; CHECK-NEXT: .set L0_0_set_7, LBB0_7-LJTI0_0
; CHECK-NEXT: .set L0_0_set_8, LBB0_8-LJTI0_0
; CHECK-NEXT: .set L0_0_set_9, LBB0_9-LJTI0_0
; CHECK-NEXT: .set L0_0_set_10, LBB0_10-LJTI0_0
; CHECK-NEXT: .set L0_0_set_11, LBB0_11-LJTI0_0
; CHECK-NEXT: .set L0_0_set_12, LBB0_12-LJTI0_0
; CHECK-NEXT: .set L0_0_set_13, LBB0_13-LJTI0_0
; CHECK-NEXT: .set L0_0_set_14, LBB0_14-LJTI0_0
; CHECK-NEXT: .set L0_0_set_15, LBB0_15-LJTI0_0
; CHECK-NEXT: .set L0_0_set_16, LBB0_16-LJTI0_0
; CHECK-NEXT: .set L0_0_set_17, LBB0_17-LJTI0_0
; CHECK-NEXT: .set L0_0_set_18, LBB0_18-LJTI0_0
; CHECK-NEXT: .set L0_0_set_19, LBB0_19-LJTI0_0
; CHECK-NEXT: .set L0_0_set_20, LBB0_20-LJTI0_0
; CHECK-NEXT: .set L0_0_set_21, LBB0_21-LJTI0_0
; CHECK-NEXT: .set L0_0_set_22, LBB0_22-LJTI0_0
; CHECK-NEXT: .set L0_0_set_23, LBB0_23-LJTI0_0
; CHECK-NEXT: .set L0_0_set_24, LBB0_24-LJTI0_0
; CHECK-NEXT: .set L0_0_set_25, LBB0_25-LJTI0_0
; CHECK-NEXT: .set L0_0_set_26, LBB0_26-LJTI0_0
; CHECK-NEXT: .set L0_0_set_27, LBB0_27-LJTI0_0
; CHECK-NEXT: LJTI0_0:
; CHECK-NEXT: .long L0_0_set_3
; CHECK-NEXT: .long L0_0_set_3
; CHECK-NEXT: .long L0_0_set_4
; CHECK-NEXT: .long L0_0_set_5
; CHECK-NEXT: .long L0_0_set_6
; CHECK-NEXT: .long L0_0_set_7
; CHECK-NEXT: .long L0_0_set_8
; CHECK-NEXT: .long L0_0_set_9
; CHECK-NEXT: .long L0_0_set_10
; CHECK-NEXT: .long L0_0_set_11
; CHECK-NEXT: .long L0_0_set_12
; CHECK-NEXT: .long L0_0_set_13
; CHECK-NEXT: .long L0_0_set_14
; CHECK-NEXT: .long L0_0_set_15
; CHECK-NEXT: .long L0_0_set_16
; CHECK-NEXT: .long L0_0_set_17
; CHECK-NEXT: .long L0_0_set_18
; CHECK-NEXT: .long L0_0_set_19
; CHECK-NEXT: .long L0_0_set_20
; CHECK-NEXT: .long L0_0_set_21
; CHECK-NEXT: .long L0_0_set_22
; CHECK-NEXT: .long L0_0_set_23
; CHECK-NEXT: .long L0_0_set_24
; CHECK-NEXT: .long L0_0_set_25
; CHECK-NEXT: .long L0_0_set_26
; CHECK-NEXT: .long L0_0_set_27
; CHECK-NEXT: .end_data_region
entry: entry:
br label %bb49 br label %bb49
bb49: bb49:
switch i64 %bar, label %RETURN [ switch i64 %bar, label %RETURN [
i64 2, label %RRETURN_2 i64 2, label %RRETURN_2
i64 3, label %RRETURN_6 i64 3, label %RRETURN_6
i64 4, label %RRETURN_7 i64 4, label %RRETURN_7
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llvm/test/CodeGen/X86/20090313-signext.ll

; RUN: llc < %s -mtriple=x86_64-- -relocation-model=pic > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "movswl %ax, %edi" %t ; RUN: llc < %s -mtriple=x86_64-- -relocation-model=pic | FileCheck %s
; RUN: grep "movw (%rax), %ax" %t
; XFAIL: *
@x = common global i16 0 @x = common global i16 0
define signext i16 @f() nounwind { define signext i16 @f() nounwind {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq h@PLT
; CHECK-NEXT: movswl %ax, %edi
; CHECK-NEXT: callq g@PLT
; CHECK-NEXT: movq x@{{.*}}(%rip), %rax
; CHECK-NEXT: movzwl (%rax), %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
entry: entry:
%0 = tail call signext i16 @h() nounwind %0 = tail call signext i16 @h() nounwind
%1 = sext i16 %0 to i32 %1 = sext i16 %0 to i32
tail call void @g(i32 %1) nounwind tail call void @g(i32 %1) nounwind
%2 = load i16, i16* @x, align 2 %2 = load i16, i16* @x, align 2
ret i16 %2 ret i16 %2
} }
declare signext i16 @h() declare signext i16 @h()
declare void @g(i32) declare void @g(i32)

llvm/test/CodeGen/X86/SwitchLowering.ll

; RUN: llc < %s -mtriple=i686-- | grep cmp | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; PR964 ; PR964
define i8* @FindChar(i8* %CurPtr) { define i8* @FindChar(i8* %CurPtr) {
; CHECK-LABEL: FindChar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: .cfi_offset %esi, -12
; CHECK-NEXT: .cfi_offset %edi, -8
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movzbl (%esi,%edi), %eax
; CHECK-NEXT: incl %edi
; CHECK-NEXT: cmpb $120, %al
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.2: # %bb
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: .LBB0_3: # %bb7
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: calll foo
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: .cfi_adjust_cfa_offset -4
; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry: entry:
br label %bb br label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3] %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=3]
%CurPtr_addr.0.rec = bitcast i32 %indvar to i32 ; <i32> [#uses=1] %CurPtr_addr.0.rec = bitcast i32 %indvar to i32 ; <i32> [#uses=1]
%gep.upgrd.1 = zext i32 %indvar to i64 ; <i64> [#uses=1] %gep.upgrd.1 = zext i32 %indvar to i64 ; <i64> [#uses=1]
%CurPtr_addr.0 = getelementptr i8, i8* %CurPtr, i64 %gep.upgrd.1 ; <i8*> [#uses=1] %CurPtr_addr.0 = getelementptr i8, i8* %CurPtr, i64 %gep.upgrd.1 ; <i8*> [#uses=1]
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llvm/test/CodeGen/X86/addr-label-difference.ll

; RUN: llc %s -o - | grep "__TEXT,__const" ; RUN: llc < %s | FileCheck %s
; PR5929 ; PR5929
; CHECK: .section __TEXT,__const
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
target triple = "i386-apple-darwin10.0" target triple = "i386-apple-darwin10.0"
; This array should go into the __TEXT,__const section, not into the ; This array should go into the __TEXT,__const section, not into the
; __DATA,__const section, because the elements don't need relocations. ; __DATA,__const section, because the elements don't need relocations.
@test.array = internal unnamed_addr constant [3 x i32] [i32 sub (i32 ptrtoint (i8* blockaddress(@test, %foo) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@test, %bar) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@test, %hack) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32))] ; <[3 x i32]*> [#uses=1] @test.array = internal unnamed_addr constant [3 x i32] [i32 sub (i32 ptrtoint (i8* blockaddress(@test, %foo) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@test, %bar) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32)), i32 sub (i32 ptrtoint (i8* blockaddress(@test, %hack) to i32), i32 ptrtoint (i8* blockaddress(@test, %foo) to i32))] ; <[3 x i32]*> [#uses=1]
define void @test(i32 %i) nounwind ssp { define void @test(i32 %i) nounwind ssp {
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llvm/test/CodeGen/X86/aligned-comm.ll

; RUN: llc < %s -mtriple=i686-- ; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefix=i686
; RUN: llc < %s -mtriple=i386-apple-darwin10 | grep "array,16512,7" ; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s --check-prefix=DARWIN
; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep "array,16512,7" ; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s --check-prefix=DARWIN
; RUN: llc < %s -mtriple=i386-apple-darwin8 | FileCheck %s --check-prefix=DARWIN8
; i686: array,16512
; DARWIN8: array,16512
; DARWIN: array,16512,7
; Darwin 9+ should get alignment on common symbols. ; Darwin 9+ should get alignment on common symbols.
@array = common global [4128 x i32] zeroinitializer, align 128 @array = common global [4128 x i32] zeroinitializer, align 128

llvm/test/CodeGen/X86/arg-cast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; This should compile to movl $2147483647, %eax + andl only. ; This should compile to movl $2147483647, %eax + andl only.
; RUN: llc < %s | grep andl ; RUN: llc < %s | FileCheck %s
; RUN: llc < %s | not grep movsd
; RUN: llc < %s | grep esp | not grep add
; rdar://5736574 ; rdar://5736574
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
define i32 @foo(double %x) nounwind { define i32 @foo(double %x) nounwind {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl $2147483647, %eax ## imm = 0x7FFFFFFF
; CHECK-NEXT: andl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: retl
entry: entry:
%x15 = bitcast double %x to i64 ; <i64> [#uses=1] %x15 = bitcast double %x to i64 ; <i64> [#uses=1]
%tmp713 = lshr i64 %x15, 32 ; <i64> [#uses=1] %tmp713 = lshr i64 %x15, 32 ; <i64> [#uses=1]
%tmp714 = trunc i64 %tmp713 to i32 ; <i32> [#uses=1] %tmp714 = trunc i64 %tmp713 to i32 ; <i32> [#uses=1]
%tmp8 = and i32 %tmp714, 2147483647 ; <i32> [#uses=1] %tmp8 = and i32 %tmp714, 2147483647 ; <i32> [#uses=1]
ret i32 %tmp8 ret i32 %tmp8
} }

llvm/test/CodeGen/X86/bitcast2.ll

; RUN: llc < %s -mtriple=x86_64-- -mattr=-avx | grep movq | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=-avx | not grep rsp ; RUN: llc < %s -mtriple=x86_64-- -mattr=-avx | FileCheck %s
define i64 @test1(double %A) { define i64 @test1(double %A) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %xmm0, %rax
; CHECK-NEXT: retq
%B = bitcast double %A to i64 %B = bitcast double %A to i64
ret i64 %B ret i64 %B
} }
define double @test2(i64 %A) { define double @test2(i64 %A) {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %xmm0
; CHECK-NEXT: retq
%B = bitcast i64 %A to double %B = bitcast i64 %A to double
ret double %B ret double %B
} }

llvm/test/CodeGen/X86/break-anti-dependencies.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Without list-burr scheduling we may not see the difference in codegen here. ; Without list-burr scheduling we may not see the difference in codegen here.
; Use a subtarget that has post-RA scheduling enabled because the anti-dependency ; Use a subtarget that has post-RA scheduling enabled because the anti-dependency
; breaker requires liveness information to be kept. ; breaker requires liveness information to be kept.
; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -enable-misched=false -post-RA-scheduler -pre-RA-sched=list-burr -break-anti-dependencies=none > %t ; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -enable-misched=false -post-RA-scheduler -pre-RA-sched=list-burr -break-anti-dependencies=none | FileCheck %s --check-prefix=none
; RUN: grep "%xmm0" %t | count 14 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -post-RA-scheduler -break-anti-dependencies=critical | FileCheck %s --check-prefix=critical
; RUN: not grep "%xmm1" %t
; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -post-RA-scheduler -break-anti-dependencies=critical > %t
; RUN: grep "%xmm0" %t | count 7
; RUN: grep "%xmm1" %t | count 7
define void @goo(double* %r, double* %p, double* %q) nounwind { define void @goo(double* %r, double* %p, double* %q) nounwind {
; none-LABEL: goo:
; none: # %bb.0: # %entry
; none-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; none-NEXT: addsd {{.*}}(%rip), %xmm0
; none-NEXT: mulsd {{.*}}(%rip), %xmm0
; none-NEXT: addsd {{.*}}(%rip), %xmm0
; none-NEXT: mulsd {{.*}}(%rip), %xmm0
; none-NEXT: addsd {{.*}}(%rip), %xmm0
; none-NEXT: cvttsd2si %xmm0, %eax
; none-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; none-NEXT: addsd {{.*}}(%rip), %xmm0
; none-NEXT: mulsd {{.*}}(%rip), %xmm0
; none-NEXT: addsd {{.*}}(%rip), %xmm0
; none-NEXT: mulsd {{.*}}(%rip), %xmm0
; none-NEXT: addsd {{.*}}(%rip), %xmm0
; none-NEXT: cvttsd2si %xmm0, %ecx
; none-NEXT: cmpl %eax, %ecx
; none-NEXT: jge .LBB0_2
; none-NEXT: # %bb.1: # %bb
; none-NEXT: movabsq $4621425052621576602, %rax # imm = 0x402299999999999A
; none-NEXT: movq %rax, (%rdx)
; none-NEXT: .LBB0_2: # %return
; none-NEXT: retq
;
; critical-LABEL: goo:
; critical: # %bb.0: # %entry
; critical-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; critical-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; critical-NEXT: addsd {{.*}}(%rip), %xmm0
; critical-NEXT: addsd {{.*}}(%rip), %xmm1
; critical-NEXT: mulsd {{.*}}(%rip), %xmm0
; critical-NEXT: mulsd {{.*}}(%rip), %xmm1
; critical-NEXT: addsd {{.*}}(%rip), %xmm0
; critical-NEXT: addsd {{.*}}(%rip), %xmm1
; critical-NEXT: mulsd {{.*}}(%rip), %xmm0
; critical-NEXT: mulsd {{.*}}(%rip), %xmm1
; critical-NEXT: addsd {{.*}}(%rip), %xmm0
; critical-NEXT: addsd {{.*}}(%rip), %xmm1
; critical-NEXT: cvttsd2si %xmm0, %eax
; critical-NEXT: cvttsd2si %xmm1, %ecx
; critical-NEXT: cmpl %ecx, %eax
; critical-NEXT: jge .LBB0_2
; critical-NEXT: # %bb.1: # %bb
; critical-NEXT: movabsq $4621425052621576602, %rax # imm = 0x402299999999999A
; critical-NEXT: movq %rax, (%rdx)
; critical-NEXT: .LBB0_2: # %return
; critical-NEXT: retq
entry: entry:
%0 = load double, double* %p, align 8 %0 = load double, double* %p, align 8
%1 = fadd double %0, 1.100000e+00 %1 = fadd double %0, 1.100000e+00
%2 = fmul double %1, 1.200000e+00 %2 = fmul double %1, 1.200000e+00
%3 = fadd double %2, 1.300000e+00 %3 = fadd double %2, 1.300000e+00
%4 = fmul double %3, 1.400000e+00 %4 = fmul double %3, 1.400000e+00
%5 = fadd double %4, 1.500000e+00 %5 = fadd double %4, 1.500000e+00
%6 = fptosi double %5 to i32 %6 = fptosi double %5 to i32
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llvm/test/CodeGen/X86/byval6.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=generic -mtriple=i686-- | grep add | not grep 16 ; RUN: llc < %s -mcpu=generic -mtriple=i686-- | FileCheck %s
%struct.W = type { x86_fp80, x86_fp80 } %struct.W = type { x86_fp80, x86_fp80 }
@B = global %struct.W { x86_fp80 0xK4001A000000000000000, x86_fp80 0xK4001C000000000000000 }, align 32 @B = global %struct.W { x86_fp80 0xK4001A000000000000000, x86_fp80 0xK4001C000000000000000 }, align 32
@.cpx = internal constant %struct.W { x86_fp80 0xK4001E000000000000000, x86_fp80 0xK40028000000000000000 } @.cpx = internal constant %struct.W { x86_fp80 0xK4001E000000000000000, x86_fp80 0xK40028000000000000000 }
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl .cpx+20, %eax
; CHECK-NEXT: movl .cpx+16, %ecx
; CHECK-NEXT: movl .cpx+12, %edx
; CHECK-NEXT: movl .cpx+8, %esi
; CHECK-NEXT: movl .cpx+4, %edi
; CHECK-NEXT: movl .cpx, %ebx
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl $3
; CHECK-NEXT: calll bar
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: movl B+20, %eax
; CHECK-NEXT: movl B+16, %ecx
; CHECK-NEXT: movl B+12, %edx
; CHECK-NEXT: movl B+8, %esi
; CHECK-NEXT: movl B+4, %edi
; CHECK-NEXT: movl B, %ebx
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl $3
; CHECK-NEXT: calll baz
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: retl
entry: entry:
tail call void (i32, ...) @bar( i32 3, %struct.W* byval @.cpx ) nounwind tail call void (i32, ...) @bar( i32 3, %struct.W* byval @.cpx ) nounwind
tail call void (i32, ...) @baz( i32 3, %struct.W* byval @B ) nounwind tail call void (i32, ...) @baz( i32 3, %struct.W* byval @B ) nounwind
ret i32 undef ret i32 undef
} }
declare void @bar(i32, ...) declare void @bar(i32, ...)
declare void @baz(i32, ...) declare void @baz(i32, ...)

llvm/test/CodeGen/X86/coalesce-esp.ll

; RUN: llc < %s | grep "movl %esp, %ebp" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; PR4572 ; PR4572
; Don't coalesce with %esp if it would end up putting %esp in ; Don't coalesce with %esp if it would end up putting %esp in
; the index position of an address, because that can't be ; the index position of an address, because that can't be
; encoded on x86. It would actually be slightly better to ; encoded on x86. It would actually be slightly better to
; swap the address operands though, since there's no scale. ; swap the address operands though, since there's no scale.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-mingw32" target triple = "i386-pc-mingw32"
%"struct.std::valarray<unsigned int>" = type { i32, i32* } %"struct.std::valarray<unsigned int>" = type { i32, i32* }
define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, %"struct.std::valarray<unsigned int>"* nocapture %__l, %"struct.std::valarray<unsigned int>"* nocapture %__s, %"struct.std::valarray<unsigned int>"* nocapture %__i) nounwind { define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, %"struct.std::valarray<unsigned int>"* nocapture %__l, %"struct.std::valarray<unsigned int>"* nocapture %__s, %"struct.std::valarray<unsigned int>"* nocapture %__i) nounwind {
; CHECK-LABEL: _ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.5: # %return
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %bb4.preheader
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: jmp .LBB0_2
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_4: # %bb7.backedge
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: addl $-4, %edx
; CHECK-NEXT: .LBB0_2: # %bb4
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb %cl, %cl
; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: # %bb.3: # %bb5
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: movl $0, (%eax,%edx)
; CHECK-NEXT: jmp .LBB0_4
entry: entry:
%0 = alloca i32, i32 undef, align 4 ; <i32*> [#uses=1] %0 = alloca i32, i32 undef, align 4 ; <i32*> [#uses=1]
br i1 undef, label %return, label %bb4 br i1 undef, label %return, label %bb4
bb4: ; preds = %bb7.backedge, %entry bb4: ; preds = %bb7.backedge, %entry
%indvar = phi i32 [ %indvar.next, %bb7.backedge ], [ 0, %entry ] ; <i32> [#uses=2] %indvar = phi i32 [ %indvar.next, %bb7.backedge ], [ 0, %entry ] ; <i32> [#uses=2]
%scevgep24.sum = sub i32 undef, %indvar ; <i32> [#uses=2] %scevgep24.sum = sub i32 undef, %indvar ; <i32> [#uses=2]
%scevgep25 = getelementptr i32, i32* %0, i32 %scevgep24.sum ; <i32*> [#uses=1] %scevgep25 = getelementptr i32, i32* %0, i32 %scevgep24.sum ; <i32*> [#uses=1]
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llvm/test/CodeGen/X86/coalescer-commute1.ll

; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | not grep movaps ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | FileCheck %s
; PR1877 ; PR1877
@NNTOT = weak global i32 0 ; <i32*> [#uses=1] @NNTOT = weak global i32 0 ; <i32*> [#uses=1]
@G = weak global float 0.000000e+00 ; <float*> [#uses=1] @G = weak global float 0.000000e+00 ; <float*> [#uses=1]
define void @runcont(i32* %source) nounwind { define void @runcont(i32* %source) nounwind {
; CHECK-LABEL: runcont:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl L_NNTOT$non_lazy_ptr, %ecx
; CHECK-NEXT: movl (%ecx), %ecx
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_1: ## %bb
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vcvtsi2ssl (%eax,%edx,4), %xmm2, %xmm1
; CHECK-NEXT: vaddss %xmm0, %xmm1, %xmm0
; CHECK-NEXT: incl %edx
; CHECK-NEXT: cmpl %edx, %ecx
; CHECK-NEXT: jne LBB0_1
; CHECK-NEXT: ## %bb.2: ## %bb13
; CHECK-NEXT: movl L_G$non_lazy_ptr, %eax
; CHECK-NEXT: vmovss %xmm0, (%eax)
; CHECK-NEXT: retl
entry: entry:
%tmp10 = load i32, i32* @NNTOT, align 4 ; <i32> [#uses=1] %tmp10 = load i32, i32* @NNTOT, align 4 ; <i32> [#uses=1]
br label %bb br label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
%neuron.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] %neuron.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
%thesum.0 = phi float [ 0.000000e+00, %entry ], [ %tmp6, %bb ] ; <float> [#uses=1] %thesum.0 = phi float [ 0.000000e+00, %entry ], [ %tmp6, %bb ] ; <float> [#uses=1]
%tmp2 = getelementptr i32, i32* %source, i32 %neuron.0 ; <i32*> [#uses=1] %tmp2 = getelementptr i32, i32* %source, i32 %neuron.0 ; <i32*> [#uses=1]
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llvm/test/CodeGen/X86/coalescer-commute3.ll

; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -no-x86-call-frame-opt | grep mov | count 6 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -no-x86-call-frame-opt | FileCheck %s
%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
define i32 @perimeter(%struct.quad_struct* %tree, i32 %size) nounwind { define i32 @perimeter(%struct.quad_struct* %tree, i32 %size) nounwind {
; CHECK-LABEL: perimeter:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: ## %bb.1: ## %entry
; CHECK-NEXT: cmpl $2, %eax
; CHECK-NEXT: jne LBB0_3
; CHECK-NEXT: ## %bb.2: ## %bb
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll _perimeter
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll _perimeter
; CHECK-NEXT: addl %esi, %eax
; CHECK-NEXT: jmp LBB0_4
; CHECK-NEXT: LBB0_3: ## %UnifiedReturnBlock
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: LBB0_4: ## %UnifiedReturnBlock
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
switch i32 %size, label %UnifiedReturnBlock [ switch i32 %size, label %UnifiedReturnBlock [
i32 2, label %bb i32 2, label %bb
i32 0, label %bb50 i32 0, label %bb50
] ]
bb: ; preds = %entry bb: ; preds = %entry
%tmp31 = tail call i32 @perimeter( %struct.quad_struct* null, i32 0 ) nounwind ; <i32> [#uses=1] %tmp31 = tail call i32 @perimeter( %struct.quad_struct* null, i32 0 ) nounwind ; <i32> [#uses=1]
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llvm/test/CodeGen/X86/coalescer-commute4.ll

; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
; PR1501 ; PR1501
define float @foo(i32* %x, float* %y, i32 %c) nounwind { define float @foo(i32* %x, float* %y, i32 %c) nounwind {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: je LBB0_1
; CHECK-NEXT: ## %bb.2: ## %bb.preheader
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_3: ## %bb
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: cvtsi2ssl (%edx,%esi,4), %xmm1
; CHECK-NEXT: mulss (%ecx,%esi,4), %xmm1
; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: incl %esi
; CHECK-NEXT: cmpl %eax, %esi
; CHECK-NEXT: jb LBB0_3
; CHECK-NEXT: jmp LBB0_4
; CHECK-NEXT: LBB0_1:
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: LBB0_4: ## %bb23
; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp)
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%tmp2132 = icmp eq i32 %c, 0 ; <i1> [#uses=2] %tmp2132 = icmp eq i32 %c, 0 ; <i1> [#uses=2]
br i1 %tmp2132, label %bb23, label %bb.preheader br i1 %tmp2132, label %bb23, label %bb.preheader
bb.preheader: ; preds = %entry bb.preheader: ; preds = %entry
%umax = select i1 %tmp2132, i32 1, i32 %c ; <i32> [#uses=1] %umax = select i1 %tmp2132, i32 1, i32 %c ; <i32> [#uses=1]
br label %bb br label %bb
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llvm/test/CodeGen/X86/coalescer-commute5.ll

; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
define i32 @t() { define i32 @t() {
; CHECK-LABEL: t:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
entry: entry:
br i1 true, label %bb1664, label %bb1656 br i1 true, label %bb1664, label %bb1656
bb1656: ; preds = %entry bb1656: ; preds = %entry
ret i32 0 ret i32 0
bb1664: ; preds = %entry bb1664: ; preds = %entry
%tmp4297 = bitcast <16 x i8> zeroinitializer to <2 x i64> ; <<2 x i64>> [#uses=2] %tmp4297 = bitcast <16 x i8> zeroinitializer to <2 x i64> ; <<2 x i64>> [#uses=2]
%tmp4351 = call <16 x i8> @llvm.x86.sse2.pcmpeq.b( <16 x i8> zeroinitializer, <16 x i8> zeroinitializer ) nounwind readnone ; <<16 x i8>> [#uses=0] %tmp4351 = call <16 x i8> @llvm.x86.sse2.pcmpeq.b( <16 x i8> zeroinitializer, <16 x i8> zeroinitializer ) nounwind readnone ; <<16 x i8>> [#uses=0]
br i1 false, label %bb5310, label %bb4743 br i1 false, label %bb5310, label %bb4743
bb4743: ; preds = %bb1664 bb4743: ; preds = %bb1664
%tmp4360.not28 = or <2 x i64> zeroinitializer, %tmp4297 ; <<2 x i64>> [#uses=1] %tmp4360.not28 = or <2 x i64> zeroinitializer, %tmp4297 ; <<2 x i64>> [#uses=1]
br label %bb5310 br label %bb5310
bb5310: ; preds = %bb4743, %bb1664 bb5310: ; preds = %bb4743, %bb1664
%tmp4360.not28.pn = phi <2 x i64> [ %tmp4360.not28, %bb4743 ], [ %tmp4297, %bb1664 ] ; <<2 x i64>> [#uses=1] %tmp4360.not28.pn = phi <2 x i64> [ %tmp4360.not28, %bb4743 ], [ %tmp4297, %bb1664 ] ; <<2 x i64>> [#uses=1]
%tmp4415.not.pn = or <2 x i64> zeroinitializer, %tmp4360.not28.pn ; <<2 x i64>> [#uses=0] %tmp4415.not.pn = or <2 x i64> zeroinitializer, %tmp4360.not28.pn ; <<2 x i64>> [#uses=0]
ret i32 0 ret i32 0
} }
declare <16 x i8> @llvm.x86.sse2.pcmpeq.b(<16 x i8>, <16 x i8>) nounwind readnone declare <16 x i8> @llvm.x86.sse2.pcmpeq.b(<16 x i8>, <16 x i8>) nounwind readnone

llvm/test/CodeGen/X86/coalescer-remat.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xor | count 3 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
@val = internal global i64 0 @val = internal global i64 0
@"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00" @"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00"
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl $1, %ecx
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: lock cmpxchgq %rcx, {{.*}}(%rip)
; CHECK-NEXT: leaq {{.*}}(%rip), %rdi
; CHECK-NEXT: movq %rax, %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq _printf
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
entry: entry:
%t0 = cmpxchg i64* @val, i64 0, i64 1 monotonic monotonic %t0 = cmpxchg i64* @val, i64 0, i64 1 monotonic monotonic
%0 = extractvalue { i64, i1 } %t0, 0 %0 = extractvalue { i64, i1 } %t0, 0
%1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i64 0), i64 %0) nounwind
ret i32 0 ret i32 0
} }
declare i32 @printf(i8*, ...) nounwind declare i32 @printf(i8*, ...) nounwind

llvm/test/CodeGen/X86/compare-add.ll

; RUN: llc < %s -mtriple=i686-- | not grep add ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i1 @X(i32 %X) { define i1 @X(i32 %X) {
; CHECK-LABEL: X:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpl $12331, {{[0-9]+}}(%esp) # imm = 0x302B
; CHECK-NEXT: setne %al
; CHECK-NEXT: retl
%Y = add i32 %X, 14 ; <i32> [#uses=1] %Y = add i32 %X, 14 ; <i32> [#uses=1]
%Z = icmp ne i32 %Y, 12345 ; <i1> [#uses=1] %Z = icmp ne i32 %Y, 12345 ; <i1> [#uses=1]
ret i1 %Z ret i1 %Z
} }

llvm/test/CodeGen/X86/compare_folding.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | \ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep movsd | count 1 ; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s
; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | \
; RUN: grep ucomisd
declare i1 @llvm.isunordered.f64(double, double)
declare i1 @llvm.isunordered.f64(double, double)
define i1 @test1(double %X, double %Y) { define i1 @test1(double %X, double %Y) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: ucomisd {{[0-9]+}}(%esp), %xmm0
; CHECK-NEXT: setp %al
; CHECK-NEXT: retl
%COM = fcmp uno double %X, %Y ; <i1> [#uses=1] %COM = fcmp uno double %X, %Y ; <i1> [#uses=1]
ret i1 %COM ret i1 %COM
} }

llvm/test/CodeGen/X86/cstring.ll

; RUN: llc < %s -mtriple=i386-apple-darwin | not grep comm ; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
; rdar://6479858 ; rdar://6479858
; CHECK-NOT: comm
@str1 = internal constant [1 x i8] zeroinitializer @str1 = internal constant [1 x i8] zeroinitializer

llvm/test/CodeGen/X86/empty-struct-return-type.ll

; RUN: llc < %s | grep call ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; PR4688 ; PR4688
; Return types can be empty structs, which can be awkward. ; Return types can be empty structs, which can be awkward.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define void @_ZN15QtSharedPointer22internalSafetyCheckAddEPVKv(i8* %ptr) { define void @_ZN15QtSharedPointer22internalSafetyCheckAddEPVKv(i8* %ptr) {
; CHECK-LABEL: _ZN15QtSharedPointer22internalSafetyCheckAddEPVKv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq _ZNK5QHashIPv15QHashDummyValueE5valueERKS0_
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry: entry:
%0 = call { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** undef) ; <{ }> [#uses=0] %0 = call { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** undef) ; <{ }> [#uses=0]
ret void ret void
} }
declare hidden { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** nocapture) nounwind declare hidden { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** nocapture) nounwind

llvm/test/CodeGen/X86/extend.ll

; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | grep movzx | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | grep movsx | count 1 ; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | FileCheck %s
@G1 = internal global i8 0 ; <i8*> [#uses=1] @G1 = internal global i8 0 ; <i8*> [#uses=1]
@G2 = internal global i8 0 ; <i8*> [#uses=1] @G2 = internal global i8 0 ; <i8*> [#uses=1]
define i16 @test1() { define i16 @test1() {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: movzx eax, byte ptr [G1]
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: ret
%tmp.0 = load i8, i8* @G1 ; <i8> [#uses=1] %tmp.0 = load i8, i8* @G1 ; <i8> [#uses=1]
%tmp.3 = zext i8 %tmp.0 to i16 ; <i16> [#uses=1] %tmp.3 = zext i8 %tmp.0 to i16 ; <i16> [#uses=1]
ret i16 %tmp.3 ret i16 %tmp.3
} }
define i16 @test2() { define i16 @test2() {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
; CHECK-NEXT: movsx eax, byte ptr [G2]
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: ret
%tmp.0 = load i8, i8* @G2 ; <i8> [#uses=1] %tmp.0 = load i8, i8* @G2 ; <i8> [#uses=1]
%tmp.3 = sext i8 %tmp.0 to i16 ; <i16> [#uses=1] %tmp.3 = sext i8 %tmp.0 to i16 ; <i16> [#uses=1]
ret i16 %tmp.3 ret i16 %tmp.3
} }

llvm/test/CodeGen/X86/extmul128.ll

; RUN: llc < %s -mtriple=x86_64-- | grep mul | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define i128 @i64_sext_i128(i64 %a, i64 %b) { define i128 @i64_sext_i128(i64 %a, i64 %b) {
; CHECK-LABEL: i64_sext_i128:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: imulq %rsi
; CHECK-NEXT: retq
%aa = sext i64 %a to i128 %aa = sext i64 %a to i128
%bb = sext i64 %b to i128 %bb = sext i64 %b to i128
%cc = mul i128 %aa, %bb %cc = mul i128 %aa, %bb
ret i128 %cc ret i128 %cc
} }
define i128 @i64_zext_i128(i64 %a, i64 %b) { define i128 @i64_zext_i128(i64 %a, i64 %b) {
; CHECK-LABEL: i64_zext_i128:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: mulq %rsi
; CHECK-NEXT: retq
%aa = zext i64 %a to i128 %aa = zext i64 %a to i128
%bb = zext i64 %b to i128 %bb = zext i64 %b to i128
%cc = mul i128 %aa, %bb %cc = mul i128 %aa, %bb
ret i128 %cc ret i128 %cc
} }

llvm/test/CodeGen/X86/extmul64.ll

; RUN: llc < %s -mtriple=i686-- | grep mul | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i64 @i32_sext_i64(i32 %a, i32 %b) { define i64 @i32_sext_i64(i32 %a, i32 %b) {
; CHECK-LABEL: i32_sext_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: imull {{[0-9]+}}(%esp)
; CHECK-NEXT: retl
%aa = sext i32 %a to i64 %aa = sext i32 %a to i64
%bb = sext i32 %b to i64 %bb = sext i32 %b to i64
%cc = mul i64 %aa, %bb %cc = mul i64 %aa, %bb
ret i64 %cc ret i64 %cc
} }
define i64 @i32_zext_i64(i32 %a, i32 %b) { define i64 @i32_zext_i64(i32 %a, i32 %b) {
; CHECK-LABEL: i32_zext_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: mull {{[0-9]+}}(%esp)
; CHECK-NEXT: retl
%aa = zext i32 %a to i64 %aa = zext i32 %a to i64
%bb = zext i32 %b to i64 %bb = zext i32 %b to i64
%cc = mul i64 %aa, %bb %cc = mul i64 %aa, %bb
ret i64 %cc ret i64 %cc
} }

llvm/test/CodeGen/X86/extractps.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=penryn > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep movd %t ; RUN: llc < %s -mtriple=i686-- -mcpu=penryn | FileCheck %s
; RUN: grep "movss %xmm" %t | count 1
; RUN: grep "extractps \$1, %xmm0, " %t | count 1
; PR2647 ; PR2647
@0 = external global float, align 16 ; <float*>:0 [#uses=2] @0 = external global float, align 16 ; <float*>:0 [#uses=2]
define internal void @""() nounwind { define internal void @a() nounwind {
; CHECK-LABEL: a:
; CHECK: # %bb.0:
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: rsqrtss %xmm0, %xmm0
; CHECK-NEXT: movss %xmm0, __unnamed_1
; CHECK-NEXT: retl
load float, float* @0, align 16 ; <float>:1 [#uses=1] load float, float* @0, align 16 ; <float>:1 [#uses=1]
insertelement <4 x float> undef, float %1, i32 0 ; <<4 x float>>:2 [#uses=1] insertelement <4 x float> undef, float %1, i32 0 ; <<4 x float>>:2 [#uses=1]
call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 ) ; <<4 x float>>:3 [#uses=1] call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 ) ; <<4 x float>>:3 [#uses=1]
extractelement <4 x float> %3, i32 0 ; <float>:4 [#uses=1] extractelement <4 x float> %3, i32 0 ; <float>:4 [#uses=1]
store float %4, float* @0, align 16 store float %4, float* @0, align 16
ret void ret void
} }
define internal void @""() nounwind { define internal void @b() nounwind {
; CHECK-LABEL: b:
; CHECK: # %bb.0:
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
; CHECK-NEXT: rsqrtss %xmm0, %xmm0
; CHECK-NEXT: extractps $1, %xmm0, __unnamed_1
; CHECK-NEXT: retl
load float, float* @0, align 16 ; <float>:1 [#uses=1] load float, float* @0, align 16 ; <float>:1 [#uses=1]
insertelement <4 x float> undef, float %1, i32 1 ; <<4 x float>>:2 [#uses=1] insertelement <4 x float> undef, float %1, i32 1 ; <<4 x float>>:2 [#uses=1]
call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 ) ; <<4 x float>>:3 [#uses=1] call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 ) ; <<4 x float>>:3 [#uses=1]
extractelement <4 x float> %3, i32 1 ; <float>:4 [#uses=1] extractelement <4 x float> %3, i32 1 ; <float>:4 [#uses=1]
store float %4, float* @0, align 16 store float %4, float* @0, align 16
ret void ret void
} }
declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone

llvm/test/CodeGen/X86/field-extract-use-trunc.ll

; RUN: llc < %s -mtriple=i686-- | grep sar | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | not grep sar ; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefix=i686
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=x86_64
define i32 @test(i32 %f12) nounwind { define i32 @test(i32 %f12) nounwind {
; i686-LABEL: test:
; i686: # %bb.0:
; i686-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; i686-NEXT: retl
;
; x86_64-LABEL: test:
; x86_64: # %bb.0:
; x86_64-NEXT: shrl $16, %edi
; x86_64-NEXT: movsbl %dil, %eax
; x86_64-NEXT: retq
%tmp7.25 = lshr i32 %f12, 16 %tmp7.25 = lshr i32 %f12, 16
%tmp7.26 = trunc i32 %tmp7.25 to i8 %tmp7.26 = trunc i32 %tmp7.25 to i8
%tmp78.2 = sext i8 %tmp7.26 to i32 %tmp78.2 = sext i8 %tmp7.26 to i32
ret i32 %tmp78.2 ret i32 %tmp78.2
} }
define i32 @test2(i32 %f12) nounwind { define i32 @test2(i32 %f12) nounwind {
; i686-LABEL: test2:
; i686: # %bb.0:
; i686-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; i686-NEXT: retl
;
; x86_64-LABEL: test2:
; x86_64: # %bb.0:
; x86_64-NEXT: shrl $16, %edi
; x86_64-NEXT: movsbl %dil, %eax
; x86_64-NEXT: retq
%f11 = shl i32 %f12, 8 %f11 = shl i32 %f12, 8
%tmp7.25 = ashr i32 %f11, 24 %tmp7.25 = ashr i32 %f11, 24
ret i32 %tmp7.25 ret i32 %tmp7.25
} }
define i32 @test3(i32 %f12) nounwind { define i32 @test3(i32 %f12) nounwind {
; i686-LABEL: test3:
; i686: # %bb.0:
; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; i686-NEXT: shrl $11, %eax
; i686-NEXT: movsbl %al, %eax
; i686-NEXT: retl
;
; x86_64-LABEL: test3:
; x86_64: # %bb.0:
; x86_64-NEXT: shrl $11, %edi
; x86_64-NEXT: movsbl %dil, %eax
; x86_64-NEXT: retq
%f11 = shl i32 %f12, 13 %f11 = shl i32 %f12, 13
%tmp7.25 = ashr i32 %f11, 24 %tmp7.25 = ashr i32 %f11, 24
ret i32 %tmp7.25 ret i32 %tmp7.25
} }
define i64 @test4(i64 %f12) nounwind { define i64 @test4(i64 %f12) nounwind {
; i686-LABEL: test4:
; i686: # %bb.0:
; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; i686-NEXT: movl %eax, %edx
; i686-NEXT: sarl $31, %edx
; i686-NEXT: retl
;
; x86_64-LABEL: test4:
; x86_64: # %bb.0:
; x86_64-NEXT: movslq %edi, %rax
; x86_64-NEXT: retq
%f11 = shl i64 %f12, 32 %f11 = shl i64 %f12, 32
%tmp7.25 = ashr i64 %f11, 32 %tmp7.25 = ashr i64 %f11, 32
ret i64 %tmp7.25 ret i64 %tmp7.25
} }
define i16 @test5(i16 %f12) nounwind { define i16 @test5(i16 %f12) nounwind {
; i686-LABEL: test5:
; i686: # %bb.0:
; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; i686-NEXT: shrl $6, %eax
; i686-NEXT: movsbl %al, %eax
; i686-NEXT: # kill: def $ax killed $ax killed $eax
; i686-NEXT: retl
;
; x86_64-LABEL: test5:
; x86_64: # %bb.0:
; x86_64-NEXT: shrl $6, %edi
; x86_64-NEXT: movsbl %dil, %eax
; x86_64-NEXT: # kill: def $ax killed $ax killed $eax
; x86_64-NEXT: retq
%f11 = shl i16 %f12, 2 %f11 = shl i16 %f12, 2
%tmp7.25 = ashr i16 %f11, 8 %tmp7.25 = ashr i16 %f11, 8
ret i16 %tmp7.25 ret i16 %tmp7.25
} }
define i16 @test6(i16 %f12) nounwind { define i16 @test6(i16 %f12) nounwind {
; i686-LABEL: test6:
; i686: # %bb.0:
; i686-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; i686-NEXT: # kill: def $ax killed $ax killed $eax
; i686-NEXT: retl
;
; x86_64-LABEL: test6:
; x86_64: # %bb.0:
; x86_64-NEXT: movsbl %dil, %eax
; x86_64-NEXT: # kill: def $ax killed $ax killed $eax
; x86_64-NEXT: retq
%f11 = shl i16 %f12, 8 %f11 = shl i16 %f12, 8
%tmp7.25 = ashr i16 %f11, 8 %tmp7.25 = ashr i16 %f11, 8
ret i16 %tmp7.25 ret i16 %tmp7.25
} }

llvm/test/CodeGen/X86/fildll.ll

; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=att -mattr=-sse2 | grep fildll | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=att -mattr=-sse2 | FileCheck %s
define fastcc double @sint64_to_fp(i64 %X) { define fastcc double @sint64_to_fp(i64 %X) {
; CHECK-LABEL: sint64_to_fp:
; CHECK: # %bb.0:
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, (%esp)
; CHECK-NEXT: fildll (%esp)
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl
%R = sitofp i64 %X to double ; <double> [#uses=1] %R = sitofp i64 %X to double ; <double> [#uses=1]
ret double %R ret double %R
} }
define fastcc double @uint64_to_fp(i64 %X) { define fastcc double @uint64_to_fp(i64 %X) {
; CHECK-LABEL: uint64_to_fp:
; CHECK: # %bb.0:
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, (%esp)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testl %edx, %edx
; CHECK-NEXT: setns %al
; CHECK-NEXT: fildll (%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl
%R = uitofp i64 %X to double ; <double> [#uses=1] %R = uitofp i64 %X to double ; <double> [#uses=1]
ret double %R ret double %R
} }

llvm/test/CodeGen/X86/fold-call-2.ll

; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
@f = external global void ()* ; <void ()**> [#uses=1] @f = external global void ()* ; <void ()**> [#uses=1]
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: movl L_f$non_lazy_ptr, %eax
; CHECK-NEXT: calll *(%eax)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
entry: entry:
load void ()*, void ()** @f, align 8 ; <void ()*>:0 [#uses=1] load void ()*, void ()** @f, align 8 ; <void ()*>:0 [#uses=1]
tail call void %0( ) nounwind tail call void %0( ) nounwind
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/fold-call-3.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep call | grep 560 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; rdar://6522427 ; rdar://6522427
; This command line used to crash due to dangling nodes left after PreprocessISelDAG ; This command line used to crash due to dangling nodes left after PreprocessISelDAG
; RUN: llc < %s -mtriple=x86_64-apple-darwin -pre-RA-sched=linearize ; RUN: llc < %s -mtriple=x86_64-apple-darwin -pre-RA-sched=linearize | FileCheck %s --check-prefix=pre-RA
%"struct.clang::Action" = type { %"struct.clang::ActionBase" } %"struct.clang::Action" = type { %"struct.clang::ActionBase" }
%"struct.clang::ActionBase" = type { i32 (...)** } %"struct.clang::ActionBase" = type { i32 (...)** }
%"struct.clang::ActionBase::ActionResult<0u>" = type { i8*, i8 } %"struct.clang::ActionBase::ActionResult<0u>" = type { i8*, i8 }
@NumTrials = internal global i32 10000000 ; <i32*> [#uses=2] @NumTrials = internal global i32 10000000 ; <i32*> [#uses=2]
@llvm.used = appending global [1 x i8*] [ i8* bitcast (void (i8*, %"struct.clang::Action"*)* @_Z25RawPointerPerformanceTestPvRN5clang6ActionE to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] @llvm.used = appending global [1 x i8*] [ i8* bitcast (void (i8*, %"struct.clang::Action"*)* @_Z25RawPointerPerformanceTestPvRN5clang6ActionE to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.clang::Action"* %Actions) nounwind { define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.clang::Action"* %Actions) nounwind {
; CHECK-LABEL: _Z25RawPointerPerformanceTestPvRN5clang6ActionE:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: cmpl $0, {{.*}}(%rip)
; CHECK-NEXT: je LBB0_3
; CHECK-NEXT: ## %bb.1: ## %bb.nph
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_2: ## %bb
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq (%rbx), %rcx
; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movq %rax, %rsi
; CHECK-NEXT: callq *560(%rcx)
; CHECK-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: incl %ebp
; CHECK-NEXT: cmpl {{.*}}(%rip), %ebp
; CHECK-NEXT: jb LBB0_2
; CHECK-NEXT: LBB0_3: ## %return
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
;
; pre-RA-LABEL: _Z25RawPointerPerformanceTestPvRN5clang6ActionE:
; pre-RA: ## %bb.0: ## %entry
; pre-RA-NEXT: pushq %rbp
; pre-RA-NEXT: pushq %rbx
; pre-RA-NEXT: subq $24, %rsp
; pre-RA-NEXT: cmpl $0, {{.*}}(%rip)
; pre-RA-NEXT: je LBB0_3
; pre-RA-NEXT: ## %bb.1: ## %bb.nph
; pre-RA-NEXT: movq %rsi, %rbx
; pre-RA-NEXT: movq %rdi, %rax
; pre-RA-NEXT: xorl %ebp, %ebp
; pre-RA-NEXT: .p2align 4, 0x90
; pre-RA-NEXT: LBB0_2: ## %bb
; pre-RA-NEXT: ## =>This Inner Loop Header: Depth=1
; pre-RA-NEXT: movq (%rbx), %rcx
; pre-RA-NEXT: movq %rbx, %rdi
; pre-RA-NEXT: movq %rax, %rsi
; pre-RA-NEXT: callq *560(%rcx)
; pre-RA-NEXT: incl %ebp
; pre-RA-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; pre-RA-NEXT: movq %rdx, {{[0-9]+}}(%rsp)
; pre-RA-NEXT: cmpl {{.*}}(%rip), %ebp
; pre-RA-NEXT: jb LBB0_2
; pre-RA-NEXT: LBB0_3: ## %return
; pre-RA-NEXT: addq $24, %rsp
; pre-RA-NEXT: popq %rbx
; pre-RA-NEXT: popq %rbp
; pre-RA-NEXT: retq
entry: entry:
%0 = alloca %"struct.clang::ActionBase::ActionResult<0u>", align 8 ; <%"struct.clang::ActionBase::ActionResult<0u>"*> [#uses=3] %0 = alloca %"struct.clang::ActionBase::ActionResult<0u>", align 8 ; <%"struct.clang::ActionBase::ActionResult<0u>"*> [#uses=3]
%1 = load i32, i32* @NumTrials, align 4 ; <i32> [#uses=1] %1 = load i32, i32* @NumTrials, align 4 ; <i32> [#uses=1]
%2 = icmp eq i32 %1, 0 ; <i1> [#uses=1] %2 = icmp eq i32 %1, 0 ; <i1> [#uses=1]
br i1 %2, label %return, label %bb.nph br i1 %2, label %return, label %bb.nph
bb.nph: ; preds = %entry bb.nph: ; preds = %entry
%3 = getelementptr %"struct.clang::Action", %"struct.clang::Action"* %Actions, i64 0, i32 0, i32 0 ; <i32 (...)***> [#uses=1] %3 = getelementptr %"struct.clang::Action", %"struct.clang::Action"* %Actions, i64 0, i32 0, i32 0 ; <i32 (...)***> [#uses=1]
Show All 27 Lines

llvm/test/CodeGen/X86/fold-sext-trunc.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movslq | count 1 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR ; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR
; PR4050 ; PR4050
%0 = type { i64 } %0 = type { i64 }
%struct.S1 = type { i16, i32 } %struct.S1 = type { i16, i32 }
@g_10 = external global %struct.S1 @g_10 = external global %struct.S1
declare void @func_28(i64, i64) declare void @func_28(i64, i64)
; CHECK: movslq g_10+4(%rip), %rdi
define void @int322(i32 %foo) !dbg !5 { define void @int322(i32 %foo) !dbg !5 {
entry: entry:
%val = load i64, i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0), !dbg !16 %val = load i64, i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0), !dbg !16
%0 = load i32, i32* getelementptr inbounds (%struct.S1, %struct.S1* @g_10, i32 0, i32 1), align 4, !dbg !17 %0 = load i32, i32* getelementptr inbounds (%struct.S1, %struct.S1* @g_10, i32 0, i32 1), align 4, !dbg !17
; MIR: renamable {{\$r[a-z]+}} = MOVSX64rm32 {{.*}}, @g_10 + 4,{{.*}} debug-location !17 :: (dereferenceable load 4 from `i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0)` + 4) ; MIR: renamable {{\$r[a-z]+}} = MOVSX64rm32 {{.*}}, @g_10 + 4,{{.*}} debug-location !17 :: (dereferenceable load 4 from `i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0)` + 4)
%1 = sext i32 %0 to i64, !dbg !18 %1 = sext i32 %0 to i64, !dbg !18
%tmp4.i = lshr i64 %val, 32, !dbg !19 %tmp4.i = lshr i64 %val, 32, !dbg !19
%tmp5.i = trunc i64 %tmp4.i to i32, !dbg !20 %tmp5.i = trunc i64 %tmp4.i to i32, !dbg !20
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fp-stack-2results.ll

; RUN: llc < %s -mtriple=i686-- | grep fldz ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | grep fld1 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,i686
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s -check-prefixes=ALL,x86_64
%0 = type { x86_fp80, x86_fp80 } %0 = type { x86_fp80, x86_fp80 }
; This is basically this code on x86-64: ; This is basically this code on x86-64:
; _Complex long double test() { return 1.0; } ; _Complex long double test() { return 1.0; }
define %0 @test() { define %0 @test() {
; ALL-LABEL: test:
; ALL: # %bb.0:
; ALL-NEXT: fldz
; ALL-NEXT: fld1
; ALL-NEXT: ret{{[l|q]}}
%A = fpext double 1.0 to x86_fp80 %A = fpext double 1.0 to x86_fp80
%B = fpext double 0.0 to x86_fp80 %B = fpext double 0.0 to x86_fp80
%mrv = insertvalue %0 undef, x86_fp80 %A, 0 %mrv = insertvalue %0 undef, x86_fp80 %A, 0
%mrv1 = insertvalue %0 %mrv, x86_fp80 %B, 1 %mrv1 = insertvalue %0 %mrv, x86_fp80 %B, 1
ret %0 %mrv1 ret %0 %mrv1
} }
;_test2: ;_test2:
; fld1 ; fld1
; fld %st(0) ; fld %st(0)
; ret ; ret
define %0 @test2() { define %0 @test2() {
; ALL-LABEL: test2:
; ALL: # %bb.0:
; ALL-NEXT: fld1
; ALL-NEXT: fld %st(0)
; ALL-NEXT: ret{{[l|q]}}
%A = fpext double 1.0 to x86_fp80 %A = fpext double 1.0 to x86_fp80
%mrv = insertvalue %0 undef, x86_fp80 %A, 0 %mrv = insertvalue %0 undef, x86_fp80 %A, 0
%mrv1 = insertvalue %0 %mrv, x86_fp80 %A, 1 %mrv1 = insertvalue %0 %mrv, x86_fp80 %A, 1
ret %0 %mrv1 ret %0 %mrv1
} }
; Uses both values. ; Uses both values.
define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) { define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-LABEL: call1:
; i686: # %bb.0:
; i686-NEXT: pushl %edi
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: pushl %esi
; i686-NEXT: .cfi_def_cfa_offset 12
; i686-NEXT: .cfi_offset %esi, -12
; i686-NEXT: .cfi_offset %edi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; i686-NEXT: calll test
; i686-NEXT: fstpt (%edi)
; i686-NEXT: fstpt (%esi)
; i686-NEXT: popl %esi
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: popl %edi
; i686-NEXT: .cfi_def_cfa_offset 4
; i686-NEXT: retl
;
; x86_64-LABEL: call1:
; x86_64: # %bb.0:
; x86_64-NEXT: pushq %r14
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: pushq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 24
; x86_64-NEXT: pushq %rax
; x86_64-NEXT: .cfi_def_cfa_offset 32
; x86_64-NEXT: .cfi_offset %rbx, -24
; x86_64-NEXT: .cfi_offset %r14, -16
; x86_64-NEXT: movq %rsi, %r14
; x86_64-NEXT: movq %rdi, %rbx
; x86_64-NEXT: callq test
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: fstpt (%r14)
; x86_64-NEXT: addq $8, %rsp
; x86_64-NEXT: .cfi_def_cfa_offset 24
; x86_64-NEXT: popq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: popq %r14
; x86_64-NEXT: .cfi_def_cfa_offset 8
; x86_64-NEXT: retq
%a = call %0 @test() %a = call %0 @test()
%b = extractvalue %0 %a, 0 %b = extractvalue %0 %a, 0
store x86_fp80 %b, x86_fp80* %P1 store x86_fp80 %b, x86_fp80* %P1
%c = extractvalue %0 %a, 1 %c = extractvalue %0 %a, 1
store x86_fp80 %c, x86_fp80* %P2 store x86_fp80 %c, x86_fp80* %P2
ret void ret void
} }
; Uses both values, requires fxch ; Uses both values, requires fxch
define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) { define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-LABEL: call2:
; i686: # %bb.0:
; i686-NEXT: pushl %edi
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: pushl %esi
; i686-NEXT: .cfi_def_cfa_offset 12
; i686-NEXT: .cfi_offset %esi, -12
; i686-NEXT: .cfi_offset %edi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; i686-NEXT: calll test
; i686-NEXT: fxch %st(1)
; i686-NEXT: fstpt (%edi)
; i686-NEXT: fstpt (%esi)
; i686-NEXT: popl %esi
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: popl %edi
; i686-NEXT: .cfi_def_cfa_offset 4
; i686-NEXT: retl
;
; x86_64-LABEL: call2:
; x86_64: # %bb.0:
; x86_64-NEXT: pushq %r14
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: pushq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 24
; x86_64-NEXT: pushq %rax
; x86_64-NEXT: .cfi_def_cfa_offset 32
; x86_64-NEXT: .cfi_offset %rbx, -24
; x86_64-NEXT: .cfi_offset %r14, -16
; x86_64-NEXT: movq %rsi, %r14
; x86_64-NEXT: movq %rdi, %rbx
; x86_64-NEXT: callq test
; x86_64-NEXT: fxch %st(1)
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: fstpt (%r14)
; x86_64-NEXT: addq $8, %rsp
; x86_64-NEXT: .cfi_def_cfa_offset 24
; x86_64-NEXT: popq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: popq %r14
; x86_64-NEXT: .cfi_def_cfa_offset 8
; x86_64-NEXT: retq
%a = call %0 @test() %a = call %0 @test()
%b = extractvalue %0 %a, 1 %b = extractvalue %0 %a, 1
store x86_fp80 %b, x86_fp80* %P1 store x86_fp80 %b, x86_fp80* %P1
%c = extractvalue %0 %a, 0 %c = extractvalue %0 %a, 0
store x86_fp80 %c, x86_fp80* %P2 store x86_fp80 %c, x86_fp80* %P2
ret void ret void
} }
; Uses ST(0), ST(1) is dead but must be popped. ; Uses ST(0), ST(1) is dead but must be popped.
define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) { define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-LABEL: call3:
; i686: # %bb.0:
; i686-NEXT: pushl %esi
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: .cfi_offset %esi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; i686-NEXT: calll test
; i686-NEXT: fstp %st(1)
; i686-NEXT: fstpt (%esi)
; i686-NEXT: popl %esi
; i686-NEXT: .cfi_def_cfa_offset 4
; i686-NEXT: retl
;
; x86_64-LABEL: call3:
; x86_64: # %bb.0:
; x86_64-NEXT: pushq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: .cfi_offset %rbx, -16
; x86_64-NEXT: movq %rdi, %rbx
; x86_64-NEXT: callq test
; x86_64-NEXT: fstp %st(1)
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: popq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 8
; x86_64-NEXT: retq
%a = call %0 @test() %a = call %0 @test()
%b = extractvalue %0 %a, 0 %b = extractvalue %0 %a, 0
store x86_fp80 %b, x86_fp80* %P1 store x86_fp80 %b, x86_fp80* %P1
ret void ret void
} }
; Uses ST(1), ST(0) is dead and must be popped. ; Uses ST(1), ST(0) is dead and must be popped.
define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) { define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) {
; i686-LABEL: call4:
; i686: # %bb.0:
; i686-NEXT: pushl %esi
; i686-NEXT: .cfi_def_cfa_offset 8
; i686-NEXT: .cfi_offset %esi, -8
; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; i686-NEXT: calll test
; i686-NEXT: fstp %st(0)
; i686-NEXT: fstpt (%esi)
; i686-NEXT: popl %esi
; i686-NEXT: .cfi_def_cfa_offset 4
; i686-NEXT: retl
;
; x86_64-LABEL: call4:
; x86_64: # %bb.0:
; x86_64-NEXT: pushq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 16
; x86_64-NEXT: .cfi_offset %rbx, -16
; x86_64-NEXT: movq %rsi, %rbx
; x86_64-NEXT: callq test
; x86_64-NEXT: fstp %st(0)
; x86_64-NEXT: fstpt (%rbx)
; x86_64-NEXT: popq %rbx
; x86_64-NEXT: .cfi_def_cfa_offset 8
; x86_64-NEXT: retq
%a = call %0 @test() %a = call %0 @test()
%c = extractvalue %0 %a, 1 %c = extractvalue %0 %a, 1
store x86_fp80 %c, x86_fp80* %P2 store x86_fp80 %c, x86_fp80* %P2
ret void ret void
} }

llvm/test/CodeGen/X86/fp-stack-direct-ret.ll

; RUN: llc < %s -mtriple=i686-- | not grep fstp ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | not grep movsd ; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,GENERIC
; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s --check-prefixes=ALL,YONAH
declare double @foo() declare double @foo()
define double @bar() { define double @bar() {
; ALL-LABEL: bar:
; ALL: # %bb.0: # %entry
; ALL-NEXT: jmp foo # TAILCALL
entry: entry:
%tmp5 = tail call double @foo() %tmp5 = tail call double @foo()
ret double %tmp5 ret double %tmp5
} }

llvm/test/CodeGen/X86/fp-stack-ret-conv.ll

; RUN: llc < %s -mcpu=yonah | grep cvtss2sd ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=yonah | grep fstps ; RUN: llc < %s -mcpu=yonah | FileCheck %s
; RUN: llc < %s -mcpu=yonah | not grep cvtsd2ss
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
define void @test(double *%b) { define void @test(double *%b) {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: calll _foo
; CHECK-NEXT: fstps {{[0-9]+}}(%esp)
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: cvtss2sd %xmm0, %xmm0
; CHECK-NEXT: movsd %xmm0, (%esi)
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%tmp13 = tail call double @foo() %tmp13 = tail call double @foo()
%tmp1314 = fptrunc double %tmp13 to float ; <float> [#uses=1] %tmp1314 = fptrunc double %tmp13 to float ; <float> [#uses=1]
%tmp3940 = fpext float %tmp1314 to double ; <double> [#uses=1] %tmp3940 = fpext float %tmp1314 to double ; <double> [#uses=1]
store volatile double %tmp3940, double* %b store volatile double %tmp3940, double* %b
ret void ret void
} }
declare double @foo() declare double @foo()

llvm/test/CodeGen/X86/fp-stack-ret-store.ll

; RUN: llc < %s -mcpu=yonah | not grep movss ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=yonah | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
; This should store directly into P from the FP stack. It should not ; This should store directly into P from the FP stack. It should not
; go through a stack slot to get there. ; go through a stack slot to get there.
define void @bar(double* %P) { define void @bar(double* %P) {
; CHECK-LABEL: bar:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: calll _foo
; CHECK-NEXT: fstpl (%esi)
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%tmp = tail call double (...) @foo( ) ; <double> [#uses=1] %tmp = tail call double (...) @foo( ) ; <double> [#uses=1]
store double %tmp, double* %P, align 8 store double %tmp, double* %P, align 8
ret void ret void
} }
declare double @foo(...) declare double @foo(...)
define void @bar2(float* %P) { define void @bar2(float* %P) {
; CHECK-LABEL: bar2:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: calll _foo2
; CHECK-NEXT: fstps (%esi)
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%tmp = tail call double (...) @foo2( ) ; <double> [#uses=1] %tmp = tail call double (...) @foo2( ) ; <double> [#uses=1]
%tmp1 = fptrunc double %tmp to float ; <float> [#uses=1] %tmp1 = fptrunc double %tmp to float ; <float> [#uses=1]
store float %tmp1, float* %P, align 4 store float %tmp1, float* %P, align 4
ret void ret void
} }
declare double @foo2(...) declare double @foo2(...)

llvm/test/CodeGen/X86/fp-stack-retcopy.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; This should not copy the result of foo into an xmm register. ; This should not copy the result of foo into an xmm register.
; RUN: llc < %s -mcpu=yonah -mtriple=i686-apple-darwin9 | not grep xmm ; RUN: llc < %s -mcpu=yonah -mtriple=i686-apple-darwin9 | FileCheck %s
; rdar://5689903 ; rdar://5689903
declare double @foo() declare double @foo()
define double @carg({ double, double }* byval %z) nounwind { define double @carg({ double, double }* byval %z) nounwind {
; CHECK-LABEL: carg:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: jmp _foo ## TAILCALL
entry: entry:
%tmp5 = tail call double @foo() nounwind ; <double> [#uses=1] %tmp5 = tail call double @foo() nounwind ; <double> [#uses=1]
ret double %tmp5 ret double %tmp5
} }

llvm/test/CodeGen/X86/fp-stack-set-st1.ll

; RUN: llc < %s -mtriple=i686-- | grep fxch | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fldl {{\.LCPI.*}}
; CHECK-NEXT: fldl {{\.LCPI.*}}
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: #APP
; CHECK-NEXT: fmul %st(1), %st
; CHECK-NEXT: fst %st(1)
; CHECK-NEXT: frndint
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fsub %st(1), %st
; CHECK-NEXT: f2xm1
; CHECK-EMPTY:
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: fstp %st(0)
; CHECK-NEXT: fstp %st(0)
entry: entry:
%asmtmp = tail call { double, double } asm sideeffect "fmul\09%st(1),%st\0A\09fst\09%st(1)\0A\09frndint\0A\09fxch %st(1)\0A\09fsub\09%st(1),%st\0A\09f2xm1\0A\09", "={st},={st(1)},0,1,~{dirflag},~{fpsr},~{flags}"(double 0x4030FEFBD582097D, double 4.620000e+01) nounwind ; <{ double, double }> [#uses=0] %asmtmp = tail call { double, double } asm sideeffect "fmul\09%st(1),%st\0A\09fst\09%st(1)\0A\09frndint\0A\09fxch %st(1)\0A\09fsub\09%st(1),%st\0A\09f2xm1\0A\09", "={st},={st(1)},0,1,~{dirflag},~{fpsr},~{flags}"(double 0x4030FEFBD582097D, double 4.620000e+01) nounwind ; <{ double, double }> [#uses=0]
unreachable unreachable
} }

llvm/test/CodeGen/X86/fp2sint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;; LowerFP_TO_SINT should not create a stack object if it's not needed. ;; LowerFP_TO_SINT should not create a stack object if it's not needed.
; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | not grep add ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
define i32 @main(i32 %argc, i8** %argv) { define i32 @main(i32 %argc, i8** %argv) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %cond_false.i.i.i
; CHECK-NEXT: cvttsd2si 0, %eax
; CHECK-NEXT: movl %eax, 0
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
cond_false.i.i.i: ; preds = %bb.i5 cond_false.i.i.i: ; preds = %bb.i5
%tmp35.i = load double, double* null, align 8 ; <double> [#uses=1] %tmp35.i = load double, double* null, align 8 ; <double> [#uses=1]
%tmp3536.i = fptosi double %tmp35.i to i32 ; <i32> [#uses=1] %tmp3536.i = fptosi double %tmp35.i to i32 ; <i32> [#uses=1]
%tmp3536140.i = zext i32 %tmp3536.i to i64 ; <i64> [#uses=1] %tmp3536140.i = zext i32 %tmp3536.i to i64 ; <i64> [#uses=1]
%tmp39.i = load double, double* null, align 4 ; <double> [#uses=1] %tmp39.i = load double, double* null, align 4 ; <double> [#uses=1]
%tmp3940.i = fptosi double %tmp39.i to i32 ; <i32> [#uses=1] %tmp3940.i = fptosi double %tmp39.i to i32 ; <i32> [#uses=1]
%tmp3940137.i = zext i32 %tmp3940.i to i64 ; <i64> [#uses=1] %tmp3940137.i = zext i32 %tmp3940.i to i64 ; <i64> [#uses=1]
%tmp3940137138.i = shl i64 %tmp3940137.i, 32 ; <i64> [#uses=1] %tmp3940137138.i = shl i64 %tmp3940137.i, 32 ; <i64> [#uses=1]
%tmp3940137138.ins.i = or i64 %tmp3940137138.i, %tmp3536140.i ; <i64> [#uses=1] %tmp3940137138.ins.i = or i64 %tmp3940137138.i, %tmp3536140.i ; <i64> [#uses=1]
%tmp95.i.i = trunc i64 %tmp3940137138.ins.i to i32 ; <i32> [#uses=1] %tmp95.i.i = trunc i64 %tmp3940137138.ins.i to i32 ; <i32> [#uses=1]
store i32 %tmp95.i.i, i32* null, align 4 store i32 %tmp95.i.i, i32* null, align 4
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/fp_load_fold.ll

; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | \ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep -i ST | not grep "fadd\|fsub\|fdiv\|fmul" ; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | FileCheck %s
; Test that the load of the memory location is folded into the operation. ; Test that the load of the memory location is folded into the operation.
define double @test_add(double %X, double* %P) { define double @test_add(double %X, double* %P) {
; CHECK-LABEL: test_add:
; CHECK: # %bb.0:
; CHECK-NEXT: mov eax, dword ptr [esp + 12]
; CHECK-NEXT: fld qword ptr [esp + 4]
; CHECK-NEXT: fadd qword ptr [eax]
; CHECK-NEXT: ret
%Y = load double, double* %P ; <double> [#uses=1] %Y = load double, double* %P ; <double> [#uses=1]
%R = fadd double %X, %Y ; <double> [#uses=1] %R = fadd double %X, %Y ; <double> [#uses=1]
ret double %R ret double %R
} }
define double @test_mul(double %X, double* %P) { define double @test_mul(double %X, double* %P) {
; CHECK-LABEL: test_mul:
; CHECK: # %bb.0:
; CHECK-NEXT: mov eax, dword ptr [esp + 12]
; CHECK-NEXT: fld qword ptr [esp + 4]
; CHECK-NEXT: fmul qword ptr [eax]
; CHECK-NEXT: ret
%Y = load double, double* %P ; <double> [#uses=1] %Y = load double, double* %P ; <double> [#uses=1]
%R = fmul double %X, %Y ; <double> [#uses=1] %R = fmul double %X, %Y ; <double> [#uses=1]
ret double %R ret double %R
} }
define double @test_sub(double %X, double* %P) { define double @test_sub(double %X, double* %P) {
; CHECK-LABEL: test_sub:
; CHECK: # %bb.0:
; CHECK-NEXT: mov eax, dword ptr [esp + 12]
; CHECK-NEXT: fld qword ptr [esp + 4]
; CHECK-NEXT: fsub qword ptr [eax]
; CHECK-NEXT: ret
%Y = load double, double* %P ; <double> [#uses=1] %Y = load double, double* %P ; <double> [#uses=1]
%R = fsub double %X, %Y ; <double> [#uses=1] %R = fsub double %X, %Y ; <double> [#uses=1]
ret double %R ret double %R
} }
define double @test_subr(double %X, double* %P) { define double @test_subr(double %X, double* %P) {
; CHECK-LABEL: test_subr:
; CHECK: # %bb.0:
; CHECK-NEXT: mov eax, dword ptr [esp + 12]
; CHECK-NEXT: fld qword ptr [eax]
; CHECK-NEXT: fsub qword ptr [esp + 4]
; CHECK-NEXT: ret
%Y = load double, double* %P ; <double> [#uses=1] %Y = load double, double* %P ; <double> [#uses=1]
%R = fsub double %Y, %X ; <double> [#uses=1] %R = fsub double %Y, %X ; <double> [#uses=1]
ret double %R ret double %R
} }
define double @test_div(double %X, double* %P) { define double @test_div(double %X, double* %P) {
; CHECK-LABEL: test_div:
; CHECK: # %bb.0:
; CHECK-NEXT: mov eax, dword ptr [esp + 12]
; CHECK-NEXT: fld qword ptr [esp + 4]
; CHECK-NEXT: fdiv qword ptr [eax]
; CHECK-NEXT: ret
%Y = load double, double* %P ; <double> [#uses=1] %Y = load double, double* %P ; <double> [#uses=1]
%R = fdiv double %X, %Y ; <double> [#uses=1] %R = fdiv double %X, %Y ; <double> [#uses=1]
ret double %R ret double %R
} }
define double @test_divr(double %X, double* %P) { define double @test_divr(double %X, double* %P) {
; CHECK-LABEL: test_divr:
; CHECK: # %bb.0:
; CHECK-NEXT: mov eax, dword ptr [esp + 12]
; CHECK-NEXT: fld qword ptr [eax]
; CHECK-NEXT: fdiv qword ptr [esp + 4]
; CHECK-NEXT: ret
%Y = load double, double* %P ; <double> [#uses=1] %Y = load double, double* %P ; <double> [#uses=1]
%R = fdiv double %Y, %X ; <double> [#uses=1] %R = fdiv double %Y, %X ; <double> [#uses=1]
ret double %R ret double %R
} }

llvm/test/CodeGen/X86/fsxor-alignment.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -enable-unsafe-fp-math | \ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep -v sp | grep xorps | count 2 ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -enable-unsafe-fp-math | FileCheck %s
; Don't fold the incoming stack arguments into the xorps instructions used ; Don't fold the incoming stack arguments into the xorps instructions used
; to do floating-point negations, because the arguments aren't vectors ; to do floating-point negations, because the arguments aren't vectors
; and aren't vector-aligned. ; and aren't vector-aligned.
define void @foo(float* %p, float* %q, float %s, float %y) { define void @foo(float* %p, float* %q, float %s, float %y) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
; CHECK-NEXT: xorps %xmm1, %xmm0
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: xorps %xmm1, %xmm2
; CHECK-NEXT: movss %xmm0, (%ecx)
; CHECK-NEXT: movss %xmm2, (%eax)
; CHECK-NEXT: retl
%ss = fsub float -0.0, %s %ss = fsub float -0.0, %s
%yy = fsub float -0.0, %y %yy = fsub float -0.0, %y
store float %ss, float* %p store float %ss, float* %p
store float %yy, float* %q store float %yy, float* %q
ret void ret void
} }

llvm/test/CodeGen/X86/hidden-vis-2.ll

; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | not grep GOT ; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s --check-prefix=i386-darwin9
; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s --check-prefix=x86_64-darwin9
@x = weak hidden global i32 0 ; <i32*> [#uses=1] @x = weak hidden global i32 0 ; <i32*> [#uses=1]
define i32 @t() nounwind readonly { define i32 @t() nounwind readonly {
; i386-darwin9-LABEL: t:
; i386-darwin9: ## %bb.0: ## %entry
; i386-darwin9-NEXT: movl _x, %eax
; i386-darwin9-NEXT: retl
;
; x86_64-darwin9-LABEL: t:
; x86_64-darwin9: ## %bb.0: ## %entry
; x86_64-darwin9-NEXT: movl {{.*}}(%rip), %eax
; x86_64-darwin9-NEXT: retq
entry: entry:
%0 = load i32, i32* @x, align 4 ; <i32> [#uses=1] %0 = load i32, i32* @x, align 4 ; <i32> [#uses=1]
ret i32 %0 ret i32 %0
} }

llvm/test/CodeGen/X86/i128-and-beyond.ll

; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1 | count 14 ; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s
; These static initializers are too big to hand off to assemblers ; These static initializers are too big to hand off to assemblers
; as monolithic blobs. ; as monolithic blobs.
; CHECK: -1
; CHECK-NEXT: -1
; CHECK: -1
; CHECK-NEXT: -1
; CHECK-NEXT: -1
; CHECK-NEXT: -1
; CHECK: -1
; CHECK-NEXT: -1
; CHECK-NEXT: -1
; CHECK-NEXT: -1
; CHECK-NEXT: -1
; CHECK-NEXT: -1
; CHECK-NEXT: -1
@x = global i128 -1 @x = global i128 -1
@y = global i256 -1 @y = global i256 -1
@z = global i512 -1 @z = global i512 -1

llvm/test/CodeGen/X86/i128-immediate.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movq | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define i128 @__addvti3() { define i128 @__addvti3() {
; CHECK-LABEL: __addvti3:
; CHECK: # %bb.0:
; CHECK-NEXT: movq $-1, %rax
; CHECK-NEXT: movq $-1, %rdx
; CHECK-NEXT: retq
ret i128 -1 ret i128 -1
} }

llvm/test/CodeGen/X86/illegal-vector-args-return.ll

; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "mulpd %xmm3, %xmm1" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "mulpd %xmm2, %xmm0" ; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | FileCheck %s
; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "addps %xmm3, %xmm1"
; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "addps %xmm2, %xmm0"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
define <4 x double> @foo(<4 x double> %x, <4 x double> %z) { define <4 x double> @foo(<4 x double> %x, <4 x double> %z) {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0:
; CHECK-NEXT: mulpd %xmm2, %xmm0
; CHECK-NEXT: mulpd %xmm3, %xmm1
; CHECK-NEXT: retl
%y = fmul <4 x double> %x, %z %y = fmul <4 x double> %x, %z
ret <4 x double> %y ret <4 x double> %y
} }
define <8 x float> @bar(<8 x float> %x, <8 x float> %z) { define <8 x float> @bar(<8 x float> %x, <8 x float> %z) {
; CHECK-LABEL: bar:
; CHECK: ## %bb.0:
; CHECK-NEXT: addps %xmm2, %xmm0
; CHECK-NEXT: addps %xmm3, %xmm1
; CHECK-NEXT: retl
%y = fadd <8 x float> %x, %z %y = fadd <8 x float> %x, %z
ret <8 x float> %y ret <8 x float> %y
} }

llvm/test/CodeGen/X86/inline-asm-modifier-n.ll

; RUN: llc < %s -mtriple=i686-- -no-integrated-as | grep " 37" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -no-integrated-as | FileCheck %s
; rdar://7008959 ; rdar://7008959
define void @bork() nounwind { define void @bork() nounwind {
; CHECK-LABEL: bork:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
; CHECK-NEXT: BORK 37
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: retl
entry: entry:
tail call void asm sideeffect "BORK ${0:n}", "i,~{dirflag},~{fpsr},~{flags}"(i32 -37) nounwind tail call void asm sideeffect "BORK ${0:n}", "i,~{dirflag},~{fpsr},~{flags}"(i32 -37) nounwind
ret void ret void
} }

llvm/test/CodeGen/X86/inline-asm-mrv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -no-integrated-as | FileCheck %s
; PR2094 ; PR2094
; RUN: llc < %s -no-integrated-as | grep movslq
; RUN: llc < %s -no-integrated-as | grep addps
; RUN: llc < %s -no-integrated-as | grep paddd
; RUN: llc < %s -no-integrated-as | not grep movq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8" target triple = "x86_64-apple-darwin8"
define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind { define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind {
; CHECK-LABEL: test1:
; CHECK: ## %bb.0:
; CHECK-NEXT: movslq %ecx, %rax
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: %eax %rcx %rdx %rax %r8d %rdx %rsi
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: set %eax
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: retq
%tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1] %tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1]
%mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6", %mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
"=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind "=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
%tmp6 = extractvalue {i32, i8*, i8*} %mrv, 0 %tmp6 = extractvalue {i32, i8*, i8*} %mrv, 0
%tmp7 = call i32 asm sideeffect "set $0", %tmp7 = call i32 asm sideeffect "set $0",
"=r,~{dirflag},~{fpsr},~{flags}"( ) nounwind "=r,~{dirflag},~{fpsr},~{flags}"( ) nounwind
ret i32 %tmp7 ret i32 %tmp7
} }
define <4 x float> @test2() nounwind { define <4 x float> @test2() nounwind {
; CHECK-LABEL: test2:
; CHECK: ## %bb.0:
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: set %xmm0, %xmm1
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: addps %xmm1, %xmm0
; CHECK-NEXT: retq
%mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"() %mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"()
%a = extractvalue {<4 x float>, <4 x float>} %mrv, 0 %a = extractvalue {<4 x float>, <4 x float>} %mrv, 0
%b = extractvalue {<4 x float>, <4 x float>} %mrv, 1 %b = extractvalue {<4 x float>, <4 x float>} %mrv, 1
%c = fadd <4 x float> %a, %b %c = fadd <4 x float> %a, %b
ret <4 x float> %c ret <4 x float> %c
} }
define <4 x i32> @test3() nounwind { define <4 x i32> @test3() nounwind {
; CHECK-LABEL: test3:
; CHECK: ## %bb.0:
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: set %xmm0, %xmm1
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: paddd %xmm1, %xmm0
; CHECK-NEXT: retq
%mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"() %mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"()
%a = extractvalue {<4 x i32>, <4 x i32>} %mrv, 0 %a = extractvalue {<4 x i32>, <4 x i32>} %mrv, 0
%b = extractvalue {<4 x i32>, <4 x i32>} %mrv, 1 %b = extractvalue {<4 x i32>, <4 x i32>} %mrv, 1
%c = add <4 x i32> %a, %b %c = add <4 x i32> %a, %b
ret <4 x i32> %c ret <4 x i32> %c
} }

llvm/test/CodeGen/X86/inline-asm-pic.ll

; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep lea ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep call ; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | FileCheck %s
@main_q = internal global i8* null ; <i8**> [#uses=1] @main_q = internal global i8* null ; <i8**> [#uses=1]
define void @func2() nounwind { define void @func2() nounwind {
; CHECK-LABEL: func2:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: calll L0$pb
; CHECK-NEXT: L0$pb:
; CHECK-NEXT: popl %eax
; CHECK-NEXT: leal _main_q-L0$pb(%eax), %eax
; CHECK-NEXT: ## InlineAsm Start
; CHECK-NEXT: movl %eax, %gs:152
; CHECK-NEXT: ## InlineAsm End
; CHECK-NEXT: retl
entry: entry:
tail call void asm "mov $1,%gs:$0", "=*m,ri,~{dirflag},~{fpsr},~{flags}"(i8** inttoptr (i32 152 to i8**), i8* bitcast (i8** @main_q to i8*)) nounwind tail call void asm "mov $1,%gs:$0", "=*m,ri,~{dirflag},~{fpsr},~{flags}"(i8** inttoptr (i32 152 to i8**), i8* bitcast (i8** @main_q to i8*)) nounwind
ret void ret void
} }

llvm/test/CodeGen/X86/ins_subreg_coalesce-2.ll

; RUN: llc < %s -mtriple=x86_64-- | not grep movw ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define i16 @test5(i16 %f12) nounwind { define i16 @test5(i16 %f12) nounwind {
; CHECK-LABEL: test5:
; CHECK: # %bb.0:
; CHECK-NEXT: shrl $6, %edi
; CHECK-NEXT: movsbl %dil, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%f11 = shl i16 %f12, 2 ; <i16> [#uses=1] %f11 = shl i16 %f12, 2 ; <i16> [#uses=1]
%tmp7.25 = ashr i16 %f11, 8 ; <i16> [#uses=1] %tmp7.25 = ashr i16 %f11, 8 ; <i16> [#uses=1]
ret i16 %tmp7.25 ret i16 %tmp7.25
} }

llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll

; RUN: llc < %s -mtriple=x86_64-- | grep mov | count 3 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
%struct.COMPOSITE = type { i8, i16, i16 } %struct.COMPOSITE = type { i8, i16, i16 }
%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
%struct.FILE_POS = type { i8, i8, i16, i32 } %struct.FILE_POS = type { i8, i8, i16, i32 }
%struct.FIRST_UNION = type { %struct.FILE_POS } %struct.FIRST_UNION = type { %struct.FILE_POS }
%struct.FONT_INFO = type { %struct.metrics*, i8*, i16*, %struct.COMPOSITE*, i32, %struct.rec*, %struct.rec*, i16, i16, i16*, i8*, i8*, i16* } %struct.FONT_INFO = type { %struct.metrics*, i8*, i16*, %struct.COMPOSITE*, i32, %struct.rec*, %struct.rec*, i16, i16, i16*, i8*, i8*, i16* }
%struct.FOURTH_UNION = type { %struct.STYLE } %struct.FOURTH_UNION = type { %struct.STYLE }
%struct.GAP = type { i8, i8, i16 } %struct.GAP = type { i8, i8, i16 }
%struct.LIST = type { %struct.rec*, %struct.rec* } %struct.LIST = type { %struct.rec*, %struct.rec* }
%struct.SECOND_UNION = type { { i16, i8, i8 } } %struct.SECOND_UNION = type { { i16, i8, i8 } }
%struct.STYLE = type { { %struct.GAP }, { %struct.GAP }, i16, i16, i32 } %struct.STYLE = type { { %struct.GAP }, { %struct.GAP }, i16, i16, i32 }
%struct.THIRD_UNION = type { %struct.FILE*, [8 x i8] } %struct.THIRD_UNION = type { %struct.FILE*, [8 x i8] }
%struct.__sFILEX = type opaque %struct.__sFILEX = type opaque
%struct.__sbuf = type { i8*, i32 } %struct.__sbuf = type { i8*, i32 }
%struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 } %struct.head_type = type { [2 x %struct.LIST], %struct.FIRST_UNION, %struct.SECOND_UNION, %struct.THIRD_UNION, %struct.FOURTH_UNION, %struct.rec*, { %struct.rec* }, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, %struct.rec*, i32 }
%struct.metrics = type { i16, i16, i16, i16, i16 } %struct.metrics = type { i16, i16, i16, i16, i16 }
%struct.rec = type { %struct.head_type } %struct.rec = type { %struct.head_type }
define void @FontChange(i1 %foo) nounwind { define void @FontChange(i1 %foo) nounwind {
; CHECK-LABEL: FontChange:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: je .LBB0_9
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb366
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb428
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: je .LBB0_9
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_3: # %bb650
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpb $0, 0
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.4: # %bb662
; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: andl $57344, %ecx # imm = 0xE000
; CHECK-NEXT: cmpl $8192, %ecx # imm = 0x2000
; CHECK-NEXT: jne .LBB0_9
; CHECK-NEXT: # %bb.5: # %bb4884
; CHECK-NEXT: andl $7168, %eax # imm = 0x1C00
; CHECK-NEXT: cmpl $1024, %eax # imm = 0x400
; CHECK-NEXT: jne .LBB0_9
; CHECK-NEXT: # %bb.6: # %bb4932
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB0_9
; CHECK-NEXT: # %bb.7: # %bb4940
; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: cmpl $160, %eax
; CHECK-NEXT: je .LBB0_9
; CHECK-NEXT: # %bb.8: # %bb4940
; CHECK-NEXT: cmpl $159, %eax
; CHECK-NEXT: .LBB0_9: # %bb4897
; CHECK-NEXT: retq
entry: entry:
br i1 %foo, label %bb298, label %bb49 br i1 %foo, label %bb298, label %bb49
bb49: ; preds = %entry bb49: ; preds = %entry
ret void ret void
bb298: ; preds = %entry bb298: ; preds = %entry
br i1 %foo, label %bb304, label %bb366 br i1 %foo, label %bb304, label %bb366
bb304: ; preds = %bb298 bb304: ; preds = %bb298
br i1 %foo, label %bb330, label %bb428 br i1 %foo, label %bb330, label %bb428
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/isel-sink2.ll

; RUN: llc < %s -mtriple=i686-- > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "movb.7(%...)" %t ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; RUN: not grep leal %t
define i8 @test(i32 *%P) nounwind { define i8 @test(i32 *%P) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: cmpb $0, 4(%eax)
; CHECK-NEXT: je .LBB0_1
; CHECK-NEXT: # %bb.2: # %F
; CHECK-NEXT: movb 7(%eax), %al
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %TB
; CHECK-NEXT: movb $4, %al
; CHECK-NEXT: retl
%Q = getelementptr i32, i32* %P, i32 1 %Q = getelementptr i32, i32* %P, i32 1
%R = bitcast i32* %Q to i8* %R = bitcast i32* %Q to i8*
%S = load i8, i8* %R %S = load i8, i8* %R
%T = icmp eq i8 %S, 0 %T = icmp eq i8 %S, 0
br i1 %T, label %TB, label %F br i1 %T, label %TB, label %F
TB: TB:
ret i8 4 ret i8 4
F: F:
%U = getelementptr i8, i8* %R, i32 3 %U = getelementptr i8, i8* %R, i32 3
%V = load i8, i8* %U %V = load i8, i8* %U
ret i8 %V ret i8 %V
} }

llvm/test/CodeGen/X86/isnan.ll

; RUN: llc < %s -mtriple=i686-- | not grep call ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
declare i1 @llvm.isunordered.f64(double) declare i1 @llvm.isunordered.f64(double)
define i1 @test_isnan(double %X) { define i1 @test_isnan(double %X) {
; CHECK-LABEL: test_isnan:
; CHECK: # %bb.0:
; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: fucomp %st(0)
; CHECK-NEXT: fnstsw %ax
; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
; CHECK-NEXT: sahf
; CHECK-NEXT: setp %al
; CHECK-NEXT: retl
%R = fcmp uno double %X, %X ; <i1> [#uses=1] %R = fcmp uno double %X, %X ; <i1> [#uses=1]
ret i1 %R ret i1 %R
} }

llvm/test/CodeGen/X86/isnan2.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | not grep pxor ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s
; This should not need to materialize 0.0 to evaluate the condition. ; This should not need to materialize 0.0 to evaluate the condition.
define i32 @test(double %X) nounwind { define i32 @test(double %X) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: ucomisd %xmm0, %xmm0
; CHECK-NEXT: setp %al
; CHECK-NEXT: retl
entry: entry:
%tmp6 = fcmp uno double %X, 0.000000e+00 ; <i1> [#uses=1] %tmp6 = fcmp uno double %X, 0.000000e+00 ; <i1> [#uses=1]
%tmp67 = zext i1 %tmp6 to i32 ; <i32> [#uses=1] %tmp67 = zext i1 %tmp6 to i32 ; <i32> [#uses=1]
ret i32 %tmp67 ret i32 %tmp67
} }

llvm/test/CodeGen/X86/ispositive.ll

; RUN: llc < %s -mtriple=i686-- | grep "shrl.*31" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i32 @test1(i32 %X) { define i32 @test1(i32 %X) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: retl
entry: entry:
icmp slt i32 %X, 0 ; <i1>:0 [#uses=1] icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
zext i1 %0 to i32 ; <i32>:1 [#uses=1] zext i1 %0 to i32 ; <i32>:1 [#uses=1]
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/X86/large-constants.ll

; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=corei7 | grep movabsq | count 3 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=corei7 | FileCheck %s
define i64 @constant_hoisting(i64 %o0, i64 %o1, i64 %o2, i64 %o3, i64 %o4, i64 %o5) { define i64 @constant_hoisting(i64 %o0, i64 %o1, i64 %o2, i64 %o3, i64 %o4, i64 %o5) {
; CHECK-LABEL: constant_hoisting:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movabsq $-281474976710654, %rax ## imm = 0xFFFF000000000002
; CHECK-NEXT: testq %rax, %rdi
; CHECK-NEXT: jne LBB0_7
; CHECK-NEXT: ## %bb.1: ## %bb1
; CHECK-NEXT: testq %rax, %rsi
; CHECK-NEXT: jne LBB0_7
; CHECK-NEXT: ## %bb.2: ## %bb2
; CHECK-NEXT: testq %rax, %rdx
; CHECK-NEXT: jne LBB0_7
; CHECK-NEXT: ## %bb.3: ## %bb3
; CHECK-NEXT: testq %rax, %rcx
; CHECK-NEXT: jne LBB0_7
; CHECK-NEXT: ## %bb.4: ## %bb4
; CHECK-NEXT: leaq 1(%rax), %rcx
; CHECK-NEXT: testq %rcx, %r8
; CHECK-NEXT: jne LBB0_7
; CHECK-NEXT: ## %bb.5: ## %bb5
; CHECK-NEXT: addq $2, %rax
; CHECK-NEXT: andq %rax, %r9
; CHECK-NEXT: je LBB0_6
; CHECK-NEXT: LBB0_7: ## %fail
; CHECK-NEXT: movq $-1, %rax
; CHECK-NEXT: retq
; CHECK-NEXT: LBB0_6: ## %bb6
; CHECK-NEXT: movq %r9, %rax
; CHECK-NEXT: retq
entry: entry:
%l0 = and i64 %o0, -281474976710654 %l0 = and i64 %o0, -281474976710654
%c0 = icmp ne i64 %l0, 0 %c0 = icmp ne i64 %l0, 0
br i1 %c0, label %fail, label %bb1 br i1 %c0, label %fail, label %bb1
bb1: bb1:
%l1 = and i64 %o1, -281474976710654 %l1 = and i64 %o1, -281474976710654
%c1 = icmp ne i64 %l1, 0 %c1 = icmp ne i64 %l1, 0
Show All 22 Lines
bb6: bb6:
ret i64 %l5 ret i64 %l5
fail: fail:
ret i64 -1 ret i64 -1
} }
define void @constant_expressions() { define void @constant_expressions() {
; CHECK-LABEL: constant_expressions:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movabsq $51250129900, %rax ## imm = 0xBEEBEEBEC
; CHECK-NEXT: movq (%rax), %rcx
; CHECK-NEXT: movq 16(%rax), %rdx
; CHECK-NEXT: addq 8(%rax), %rcx
; CHECK-NEXT: addq 24(%rax), %rdx
; CHECK-NEXT: addq %rcx, %rdx
; CHECK-NEXT: movq %rdx, (%rax)
; CHECK-NEXT: retq
entry: entry:
%0 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 0) to i64*) %0 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 0) to i64*)
%1 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 8) to i64*) %1 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 8) to i64*)
%2 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 16) to i64*) %2 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 16) to i64*)
%3 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 24) to i64*) %3 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 24) to i64*)
%4 = add i64 %0, %1 %4 = add i64 %0, %1
%5 = add i64 %2, %3 %5 = add i64 %2, %3
%6 = add i64 %4, %5 %6 = add i64 %4, %5
store i64 %6, i64* inttoptr (i64 add (i64 51250129900, i64 0) to i64*) store i64 %6, i64* inttoptr (i64 add (i64 51250129900, i64 0) to i64*)
ret void ret void
} }
define void @constant_expressions2() { define void @constant_expressions2() {
; CHECK-LABEL: constant_expressions2:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movabsq $51250129900, %rax ## imm = 0xBEEBEEBEC
; CHECK-NEXT: movq (%rax), %rcx
; CHECK-NEXT: movq 16(%rax), %rdx
; CHECK-NEXT: addq 8(%rax), %rcx
; CHECK-NEXT: addq 24(%rax), %rdx
; CHECK-NEXT: addq %rcx, %rdx
; CHECK-NEXT: movq %rdx, (%rax)
; CHECK-NEXT: retq
entry: entry:
%0 = load i64, i64* inttoptr (i64 51250129900 to i64*) %0 = load i64, i64* inttoptr (i64 51250129900 to i64*)
%1 = load i64, i64* inttoptr (i64 51250129908 to i64*) %1 = load i64, i64* inttoptr (i64 51250129908 to i64*)
%2 = load i64, i64* inttoptr (i64 51250129916 to i64*) %2 = load i64, i64* inttoptr (i64 51250129916 to i64*)
%3 = load i64, i64* inttoptr (i64 51250129924 to i64*) %3 = load i64, i64* inttoptr (i64 51250129924 to i64*)
%4 = add i64 %0, %1 %4 = add i64 %0, %1
%5 = add i64 %2, %3 %5 = add i64 %2, %3
%6 = add i64 %4, %5 %6 = add i64 %4, %5
store i64 %6, i64* inttoptr (i64 51250129900 to i64*) store i64 %6, i64* inttoptr (i64 51250129900 to i64*)
ret void ret void
} }

llvm/test/CodeGen/X86/lea-recursion.ll

; RUN: llc < %s -mtriple=x86_64-- | grep lea | count 13 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; This testcase was written to demonstrate an instruction-selection problem, ; This testcase was written to demonstrate an instruction-selection problem,
; however it also happens to expose a limitation in the DAGCombiner's ; however it also happens to expose a limitation in the DAGCombiner's
; expression reassociation which causes it to miss opportunities for ; expression reassociation which causes it to miss opportunities for
; constant folding due to the intermediate adds having multiple uses. ; constant folding due to the intermediate adds having multiple uses.
; The Reassociate pass has similar limitations. If these limitations are ; The Reassociate pass has similar limitations. If these limitations are
; fixed, the test commands above will need to be updated to expect fewer ; fixed, the test commands above will need to be updated to expect fewer
; lea instructions. ; lea instructions.
@g0 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=8] @g0 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=8]
@g1 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=7] @g1 = weak global [1000 x i32] zeroinitializer, align 32 ; <[1000 x i32]*> [#uses=7]
define void @foo() { define void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
; CHECK-NEXT: movl {{.*}}(%rip), %ecx
; CHECK-NEXT: leal (%rax,%rcx), %edx
; CHECK-NEXT: leal 1(%rax,%rcx), %eax
; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rdx), %ecx
; CHECK-NEXT: leal 2(%rax,%rdx), %eax
; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rcx), %edx
; CHECK-NEXT: leal 2(%rax,%rcx), %eax
; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rdx), %ecx
; CHECK-NEXT: leal 2(%rax,%rdx), %eax
; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rcx), %edx
; CHECK-NEXT: leal 2(%rax,%rcx), %eax
; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
; CHECK-NEXT: leal 1(%rax,%rdx), %ecx
; CHECK-NEXT: leal 2(%rax,%rdx), %eax
; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
; CHECK-NEXT: movl g1+{{.*}}(%rip), %eax
; CHECK-NEXT: leal 2(%rax,%rcx), %eax
; CHECK-NEXT: movl %eax, g0+{{.*}}(%rip)
; CHECK-NEXT: retq
entry: entry:
%tmp4 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 0) ; <i32> [#uses=1] %tmp4 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 0) ; <i32> [#uses=1]
%tmp8 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 0) ; <i32> [#uses=1] %tmp8 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 0) ; <i32> [#uses=1]
%tmp9 = add i32 %tmp4, 1 ; <i32> [#uses=1] %tmp9 = add i32 %tmp4, 1 ; <i32> [#uses=1]
%tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=2] %tmp10 = add i32 %tmp9, %tmp8 ; <i32> [#uses=2]
store i32 %tmp10, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 1) store i32 %tmp10, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 1)
%tmp8.1 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 1) ; <i32> [#uses=1] %tmp8.1 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 1) ; <i32> [#uses=1]
%tmp9.1 = add i32 %tmp10, 1 ; <i32> [#uses=1] %tmp9.1 = add i32 %tmp10, 1 ; <i32> [#uses=1]
Show All 24 Lines

llvm/test/CodeGen/X86/limited-prec.ll

; RUN: llc < %s -limit-float-precision=6 -mtriple=i686-- | \ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep exp | not grep log | not grep pow ; RUN: llc < %s -limit-float-precision=6 -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,precision6
; RUN: llc < %s -limit-float-precision=12 -mtriple=i686-- | \ ; RUN: llc < %s -limit-float-precision=12 -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,precision12
; RUN: not grep exp | not grep log | not grep pow ; RUN: llc < %s -limit-float-precision=18 -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,precision18
; RUN: llc < %s -limit-float-precision=18 -mtriple=i686-- | \
; RUN: not grep exp | not grep log | not grep pow
define float @f1(float %x) nounwind noinline { define float @f1(float %x) nounwind noinline {
; precision6-LABEL: f1:
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $20, %esp
; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fnstcw (%esp)
; precision6-NEXT: movzwl (%esp), %eax
; precision6-NEXT: orl $3072, %eax # imm = 0xC00
; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw {{[0-9]+}}(%esp)
; precision6-NEXT: fistl {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw (%esp)
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: addl $20, %esp
; precision6-NEXT: retl
;
; precision12-LABEL: f1:
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00
; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw {{[0-9]+}}(%esp)
; precision12-NEXT: fistl {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw (%esp)
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: addl $20, %esp
; precision12-NEXT: retl
;
; precision18-LABEL: f1:
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00
; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw {{[0-9]+}}(%esp)
; precision18-NEXT: fistl {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw (%esp)
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: fstps {{[0-9]+}}(%esp)
; precision18-NEXT: shll $23, %eax
; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: addl $20, %esp
; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.exp.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.exp.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.exp.f32(float) nounwind readonly declare float @llvm.exp.f32(float) nounwind readonly
define float @f2(float %x) nounwind noinline { define float @f2(float %x) nounwind noinline {
; precision6-LABEL: f2:
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $20, %esp
; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: fnstcw (%esp)
; precision6-NEXT: movzwl (%esp), %eax
; precision6-NEXT: orl $3072, %eax # imm = 0xC00
; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw {{[0-9]+}}(%esp)
; precision6-NEXT: fistl {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw (%esp)
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: addl $20, %esp
; precision6-NEXT: retl
;
; precision12-LABEL: f2:
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00
; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw {{[0-9]+}}(%esp)
; precision12-NEXT: fistl {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw (%esp)
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: addl $20, %esp
; precision12-NEXT: retl
;
; precision18-LABEL: f2:
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00
; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw {{[0-9]+}}(%esp)
; precision18-NEXT: fistl {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw (%esp)
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: fstps {{[0-9]+}}(%esp)
; precision18-NEXT: shll $23, %eax
; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: addl $20, %esp
; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.exp2.f32(float) nounwind readonly declare float @llvm.exp2.f32(float) nounwind readonly
define float @f3(float %x) nounwind noinline { define float @f3(float %x) nounwind noinline {
; precision6-LABEL: f3:
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $20, %esp
; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fnstcw (%esp)
; precision6-NEXT: movzwl (%esp), %eax
; precision6-NEXT: orl $3072, %eax # imm = 0xC00
; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw {{[0-9]+}}(%esp)
; precision6-NEXT: fistl {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw (%esp)
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: addl $20, %esp
; precision6-NEXT: retl
;
; precision12-LABEL: f3:
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00
; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw {{[0-9]+}}(%esp)
; precision12-NEXT: fistl {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw (%esp)
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: addl $20, %esp
; precision12-NEXT: retl
;
; precision18-LABEL: f3:
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00
; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw {{[0-9]+}}(%esp)
; precision18-NEXT: fistl {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw (%esp)
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: fstps {{[0-9]+}}(%esp)
; precision18-NEXT: shll $23, %eax
; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: addl $20, %esp
; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.pow.f32(float 1.000000e+01, float %x) ; <float> [#uses=1] %0 = call float @llvm.pow.f32(float 1.000000e+01, float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.pow.f32(float, float) nounwind readonly declare float @llvm.pow.f32(float, float) nounwind readonly
define float @f4(float %x) nounwind noinline { define float @f4(float %x) nounwind noinline {
; precision6-LABEL: f4:
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $8, %esp
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, %ecx
; precision6-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision6-NEXT: movl %ecx, (%esp)
; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision6-NEXT: shrl $23, %eax
; precision6-NEXT: addl $-127, %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fildl {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: faddp %st, %st(1)
; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl
;
; precision12-LABEL: f4:
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $8, %esp
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, %ecx
; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision12-NEXT: movl %ecx, (%esp)
; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision12-NEXT: shrl $23, %eax
; precision12-NEXT: addl $-127, %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fildl {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: faddp %st, %st(1)
; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl
;
; precision18-LABEL: f4:
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $8, %esp
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, %ecx
; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision18-NEXT: movl %ecx, (%esp)
; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision18-NEXT: shrl $23, %eax
; precision18-NEXT: addl $-127, %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fildl {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.log.f32(float) nounwind readonly declare float @llvm.log.f32(float) nounwind readonly
define float @f5(float %x) nounwind noinline { define float @f5(float %x) nounwind noinline {
; precision6-LABEL: f5:
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $8, %esp
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, %ecx
; precision6-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision6-NEXT: movl %ecx, (%esp)
; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision6-NEXT: shrl $23, %eax
; precision6-NEXT: addl $-127, %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl
;
; precision12-LABEL: f5:
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $8, %esp
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, %ecx
; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision12-NEXT: movl %ecx, (%esp)
; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision12-NEXT: shrl $23, %eax
; precision12-NEXT: addl $-127, %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl
;
; precision18-LABEL: f5:
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $8, %esp
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, %ecx
; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision18-NEXT: movl %ecx, (%esp)
; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision18-NEXT: shrl $23, %eax
; precision18-NEXT: addl $-127, %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.log2.f32(float) nounwind readonly declare float @llvm.log2.f32(float) nounwind readonly
define float @f6(float %x) nounwind noinline { define float @f6(float %x) nounwind noinline {
; precision6-LABEL: f6:
; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $8, %esp
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, %ecx
; precision6-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision6-NEXT: movl %ecx, (%esp)
; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision6-NEXT: shrl $23, %eax
; precision6-NEXT: addl $-127, %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}}
; precision6-NEXT: fildl {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}}
; precision6-NEXT: faddp %st, %st(1)
; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl
;
; precision12-LABEL: f6:
; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $8, %esp
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, %ecx
; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision12-NEXT: movl %ecx, (%esp)
; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision12-NEXT: shrl $23, %eax
; precision12-NEXT: addl $-127, %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}}
; precision12-NEXT: fildl {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}}
; precision12-NEXT: faddp %st, %st(1)
; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl
;
; precision18-LABEL: f6:
; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $8, %esp
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, %ecx
; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision18-NEXT: movl %ecx, (%esp)
; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision18-NEXT: shrl $23, %eax
; precision18-NEXT: addl $-127, %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fadds {{\.LCPI.*}}
; precision18-NEXT: fildl {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}}
; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.log10.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.log10.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.log10.f32(float) nounwind readonly declare float @llvm.log10.f32(float) nounwind readonly

llvm/test/CodeGen/X86/loop-strength-reduce5.ll

; RUN: llc < %s -mtriple=i686-- | grep inc | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
@X = weak global i16 0 ; <i16*> [#uses=1] @X = weak global i16 0 ; <i16*> [#uses=1]
@Y = weak global i16 0 ; <i16*> [#uses=1] @Y = weak global i16 0 ; <i16*> [#uses=1]
define void @foo(i32 %N) nounwind { define void @foo(i32 %N) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jle .LBB0_3
; CHECK-NEXT: # %bb.1: # %bb.preheader
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movw %dx, X
; CHECK-NEXT: movw %cx, Y
; CHECK-NEXT: incl %edx
; CHECK-NEXT: addl $4, %ecx
; CHECK-NEXT: cmpl %edx, %eax
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: .LBB0_3: # %return
; CHECK-NEXT: retl
entry: entry:
%tmp1019 = icmp sgt i32 %N, 0 ; <i1> [#uses=1] %tmp1019 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
br i1 %tmp1019, label %bb, label %return br i1 %tmp1019, label %bb, label %return
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
%i.014.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] %i.014.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
%tmp1 = trunc i32 %i.014.0 to i16 ; <i16> [#uses=2] %tmp1 = trunc i32 %i.014.0 to i16 ; <i16> [#uses=2]
store volatile i16 %tmp1, i16* @X, align 2 store volatile i16 %tmp1, i16* @X, align 2
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llvm/test/CodeGen/X86/loop-strength-reduce6.ll

; RUN: llc < %s -mtriple=x86_64-- | not grep inc ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define fastcc i32 @decodeMP3(i32 %isize, i32* %done) nounwind { define fastcc i32 @decodeMP3(i32 %isize, i32* %done) nounwind {
; CHECK-LABEL: decodeMP3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
entry: entry:
br label %cond_true189 br label %cond_true189
cond_true189: ; preds = %entry cond_true189: ; preds = %entry
ret i32 0 ret i32 0
cond_next191: ; preds = %entry cond_next191: ; preds = %entry
br label %cond_false.i9 br label %cond_false.i9
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/loop-strength-reduce7.ll

; RUN: llc < %s | not grep imul ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
target triple = "i386-apple-darwin9.6" target triple = "i386-apple-darwin9.6"
%struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] } %struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] }
%struct.III_scalefac_t = type { [22 x i32], [13 x [3 x i32]] } %struct.III_scalefac_t = type { [22 x i32], [13 x [3 x i32]] }
%struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, [4 x i32] } %struct.gr_info = type { i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, [4 x i32] }
%struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 } %struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
define fastcc void @outer_loop(%struct.lame_global_flags* nocapture %gfp, double* nocapture %xr, i32 %targ_bits, double* nocapture %best_noise, %struct.III_psy_xmin* nocapture %l3_xmin, i32* nocapture %l3_enc, %struct.III_scalefac_t* nocapture %scalefac, %struct.gr_info* nocapture %cod_info, i32 %ch) nounwind { define fastcc void @outer_loop(%struct.lame_global_flags* nocapture %gfp, double* nocapture %xr, i32 %targ_bits, double* nocapture %best_noise, %struct.III_psy_xmin* nocapture %l3_xmin, i32* nocapture %l3_enc, %struct.III_scalefac_t* nocapture %scalefac, %struct.gr_info* nocapture %cod_info, i32 %ch) nounwind {
; CHECK-LABEL: outer_loop:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl $88, %eax
; CHECK-NEXT: movl $168, %ecx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_2: ## %bb28.i37
; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB0_3 Depth 2
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_3: ## %bb29.i38
; CHECK-NEXT: ## Parent Loop BB0_2 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: incl %edx
; CHECK-NEXT: addl $12, %esi
; CHECK-NEXT: cmpl $11, %edx
; CHECK-NEXT: jbe LBB0_3
; CHECK-NEXT: ## %bb.1: ## %bb28.i37.loopexit
; CHECK-NEXT: ## in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: addl $4, %eax
; CHECK-NEXT: addl $168, %ecx
; CHECK-NEXT: jmp LBB0_2
entry: entry:
br label %bb4 br label %bb4
bb4: ; preds = %bb4, %entry bb4: ; preds = %bb4, %entry
br i1 true, label %bb5, label %bb4 br i1 true, label %bb5, label %bb4
bb5: ; preds = %bb4 bb5: ; preds = %bb4
br i1 true, label %bb28.i37, label %bb.i4 br i1 true, label %bb28.i37, label %bb.i4
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llvm/test/CodeGen/X86/lsr-negative-stride.ll

; RUN: llc < %s -mtriple=i686-- > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep neg %t ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; RUN: not grep sub.*esp %t
; RUN: not grep esi %t
; RUN: not grep push %t
; This corresponds to: ; This corresponds to:
;int t(int a, int b) { ;int t(int a, int b) {
; while (a != b) { ; while (a != b) {
; if (a > b) ; if (a > b)
; a -= b; ; a -= b;
; else ; else
; b -= a; ; b -= a;
; } ; }
; return a; ; return a;
;} ;}
define i32 @t(i32 %a, i32 %b) nounwind { define i32 @t(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: cmpl %ecx, %edx
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: retl
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %bb.outer
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_3 Depth 2
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_3: # %bb
; CHECK-NEXT: # Parent Loop BB0_2 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: jle .LBB0_5
; CHECK-NEXT: # %bb.4: # %cond_true
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=2
; CHECK-NEXT: cmpl %eax, %ecx
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: jmp .LBB0_6
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_5: # %cond_false
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: subl %edx, %ecx
; CHECK-NEXT: cmpl %edx, %ecx
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: .LBB0_6: # %bb17
; CHECK-NEXT: retl
entry: entry:
%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1] %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp1434, label %bb17, label %bb.outer br i1 %tmp1434, label %bb17, label %bb.outer
bb.outer: ; preds = %cond_false, %entry bb.outer: ; preds = %cond_false, %entry
%b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5] %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] ; <i32> [#uses=5]
%a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1] %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] ; <i32> [#uses=1]
br label %bb br label %bb
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llvm/test/CodeGen/X86/lsr-sort.ll

; RUN: llc < %s -mtriple=x86_64-- > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep inc %t | count 1 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; RUN: not grep incw %t
@X = common global i16 0 ; <i16*> [#uses=1] @X = common global i16 0 ; <i16*> [#uses=1]
define i32 @foo(i32 %N) nounwind { define i32 @foo(i32 %N) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: jle .LBB0_2
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movw %ax, {{.*}}(%rip)
; CHECK-NEXT: incl %eax
; CHECK-NEXT: cmpl %eax, %edi
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: .LBB0_2: # %return
; CHECK-NEXT: retq
entry: entry:
%0 = icmp sgt i32 %N, 0 ; <i1> [#uses=1] %0 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
br i1 %0, label %bb, label %return br i1 %0, label %bb, label %return
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
%i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] %i.03 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2]
%1 = trunc i32 %i.03 to i16 ; <i16> [#uses=1] %1 = trunc i32 %i.03 to i16 ; <i16> [#uses=1]
store volatile i16 %1, i16* @X, align 2 store volatile i16 %1, i16* @X, align 2
%indvar.next = add i32 %i.03, 1 ; <i32> [#uses=2] %indvar.next = add i32 %i.03, 1 ; <i32> [#uses=2]
%exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1] %exitcond = icmp eq i32 %indvar.next, %N ; <i1> [#uses=1]
br i1 %exitcond, label %return, label %bb br i1 %exitcond, label %return, label %bb
return: ; preds = %bb, %entry return: ; preds = %bb, %entry
%h = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] %h = phi i32 [ 0, %entry ], [ %indvar.next, %bb ]
ret i32 %h ret i32 %h
} }

llvm/test/CodeGen/X86/maskmovdqu.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse2,-avx | grep -i edi ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | grep -i rdi ; RUN: llc < %s -mtriple=i686-- -mattr=+sse2,-avx | FileCheck %s --check-prefixes=ALL,i686_SSE2
; RUN: llc < %s -mtriple=i686-- -mattr=+avx | grep -i edi ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | FileCheck %s --check-prefixes=ALL,x86_64_SSE2
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | grep -i rdi ; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=ALL,i686_AVX
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=ALL,x86_64_AVX
; rdar://6573467 ; rdar://6573467
define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind { define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind {
; i686_SSE2-LABEL: test:
; i686_SSE2: # %bb.0: # %entry
; i686_SSE2-NEXT: pushl %edi
; i686_SSE2-NEXT: movl {{[0-9]+}}(%esp), %edi
; i686_SSE2-NEXT: maskmovdqu %xmm1, %xmm0
; i686_SSE2-NEXT: popl %edi
; i686_SSE2-NEXT: retl
;
; x86_64_SSE2-LABEL: test:
; x86_64_SSE2: # %bb.0: # %entry
; x86_64_SSE2-NEXT: movq %rsi, %rdi
; x86_64_SSE2-NEXT: maskmovdqu %xmm1, %xmm0
; x86_64_SSE2-NEXT: retq
;
; i686_AVX-LABEL: test:
; i686_AVX: # %bb.0: # %entry
; i686_AVX-NEXT: pushl %edi
; i686_AVX-NEXT: movl {{[0-9]+}}(%esp), %edi
; i686_AVX-NEXT: vmaskmovdqu %xmm1, %xmm0
; i686_AVX-NEXT: popl %edi
; i686_AVX-NEXT: retl
;
; x86_64_AVX-LABEL: test:
; x86_64_AVX: # %bb.0: # %entry
; x86_64_AVX-NEXT: movq %rsi, %rdi
; x86_64_AVX-NEXT: vmaskmovdqu %xmm1, %xmm0
; x86_64_AVX-NEXT: retq
entry: entry:
tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c ) tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c )
ret void ret void
} }
declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind declare void @llvm.x86.sse2.maskmov.dqu(<16 x i8>, <16 x i8>, i8*) nounwind

llvm/test/CodeGen/X86/movfs.ll

; RUN: llc < %s -mtriple=i686-- | grep fs ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i32 @foo() nounwind readonly { define i32 @foo() nounwind readonly {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %fs:196, %eax
; CHECK-NEXT: movl (%eax), %eax
; CHECK-NEXT: retl
entry: entry:
%tmp = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1] %tmp = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1]
%tmp1 = load i32, i32* %tmp ; <i32> [#uses=1] %tmp1 = load i32, i32* %tmp ; <i32> [#uses=1]
ret i32 %tmp1 ret i32 %tmp1
} }

llvm/test/CodeGen/X86/mul-remat.ll

; RUN: llc < %s -mtriple=i686-- | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; PR1874 ; PR1874
define i32 @test(i32 %a, i32 %b) { define i32 @test(i32 %a, i32 %b) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: imull {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: retl
entry: entry:
%tmp3 = mul i32 %b, %a %tmp3 = mul i32 %b, %a
ret i32 %tmp3 ret i32 %tmp3
} }

llvm/test/CodeGen/X86/mul-shift-reassoc.ll

; RUN: llc < %s -mtriple=i686-- | grep lea ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | not grep add ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i32 @test(i32 %X, i32 %Y) { define i32 @test(i32 %X, i32 %Y) {
; Push the shl through the mul to allow an LEA to be formed, instead ; Push the shl through the mul to allow an LEA to be formed, instead
; of using a shift and add separately. ; of using a shift and add separately.
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: imull %eax, %ecx
; CHECK-NEXT: leal (%eax,%ecx,2), %eax
; CHECK-NEXT: retl
%tmp.2 = shl i32 %X, 1 ; <i32> [#uses=1] %tmp.2 = shl i32 %X, 1 ; <i32> [#uses=1]
%tmp.3 = mul i32 %tmp.2, %Y ; <i32> [#uses=1] %tmp.3 = mul i32 %tmp.2, %Y ; <i32> [#uses=1]
%tmp.5 = add i32 %tmp.3, %Y ; <i32> [#uses=1] %tmp.5 = add i32 %tmp.3, %Y ; <i32> [#uses=1]
ret i32 %tmp.5 ret i32 %tmp.5
} }

llvm/test/CodeGen/X86/neg-shl-add.ll

; RUN: llc -mtriple=x86_64-- < %s | not grep negq ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
; These sequences don't need neg instructions; they can be done with ; These sequences don't need neg instructions; they can be done with
; a single shift and sub each. ; a single shift and sub each.
define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind { define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
; CHECK-NEXT: shlq %cl, %rsi
; CHECK-NEXT: subq %rsi, %rax
; CHECK-NEXT: retq
%a = sub i64 0, %y %a = sub i64 0, %y
%b = shl i64 %a, %n %b = shl i64 %a, %n
%c = add i64 %b, %x %c = add i64 %b, %x
ret i64 %c ret i64 %c
} }
define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind { define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind {
; CHECK-LABEL: boo:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: # kill: def $cl killed $cl killed $rcx
; CHECK-NEXT: shlq %cl, %rsi
; CHECK-NEXT: subq %rsi, %rax
; CHECK-NEXT: retq
%a = sub i64 0, %y %a = sub i64 0, %y
%b = shl i64 %a, %n %b = shl i64 %a, %n
%c = add i64 %x, %b %c = add i64 %x, %b
ret i64 %c ret i64 %c
} }

llvm/test/CodeGen/X86/neg_fp.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 -o %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep xorps %t | count 1 ; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s
; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization ; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization
; -0 - (A - B) to (B - A) because A==B, -0 != 0 ; -0 - (A - B) to (B - A) because A==B, -0 != 0
define float @negfp(float %a, float %b) { define float @negfp(float %a, float %b) {
; CHECK-LABEL: negfp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: subss {{[0-9]+}}(%esp), %xmm0
; CHECK-NEXT: xorps {{\.LCPI.*}}, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp)
; CHECK-NEXT: popl %eax
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry: entry:
%sub = fsub float %a, %b ; <float> [#uses=1] %sub = fsub float %a, %b ; <float> [#uses=1]
%neg = fsub float -0.000000e+00, %sub ; <float> [#uses=1] %neg = fsub float -0.000000e+00, %sub ; <float> [#uses=1]
ret float %neg ret float %neg
} }

llvm/test/CodeGen/X86/negate-add-zero.ll

; RUN: llc < %s -enable-unsafe-fp-math | not grep xor ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -enable-unsafe-fp-math | FileCheck %s
; PR3374 ; PR3374
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin7" target triple = "i386-apple-darwin7"
%struct.AtomList = type { %"struct.CDSListRep<IVMAtom*>"* } %struct.AtomList = type { %"struct.CDSListRep<IVMAtom*>"* }
%struct.AtomTree = type { %struct.IVM*, %"struct.CDSList<CDSList<HingeNode*> >" } %struct.AtomTree = type { %struct.IVM*, %"struct.CDSList<CDSList<HingeNode*> >" }
%"struct.CDS::DefaultAlloc" = type <{ i8 }> %"struct.CDS::DefaultAlloc" = type <{ i8 }>
%"struct.CDS::SingularError" = type { %"struct.CDS::exception" } %"struct.CDS::SingularError" = type { %"struct.CDS::exception" }
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declare void @_ZN13HingeNodeSpecILi6EE9calcPropsEv(%"struct.HingeNodeSpec<6>"*) declare void @_ZN13HingeNodeSpecILi6EE9calcPropsEv(%"struct.HingeNodeSpec<6>"*)
declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%struct.Mat6* noalias sret, %struct.Mat6*) declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13TransposeTypeERKS3_(%struct.Mat6* noalias sret, %struct.Mat6*)
declare void @_ZN21HNodeTranslateRotate311toCartesianEv(%struct.HNodeTranslateRotate3*) declare void @_ZN21HNodeTranslateRotate311toCartesianEv(%struct.HNodeTranslateRotate3*)
define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3* %this, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"* %velv) { define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3* %this, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"* %velv) {
; CHECK-LABEL: _ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: fldl 0
; CHECK-NEXT: fldl 3184(%ecx)
; CHECK-NEXT: fld %st(1)
; CHECK-NEXT: fmull 3176(%ecx)
; CHECK-NEXT: fldz
; CHECK-NEXT: fld %st(1)
; CHECK-NEXT: fadd %st(1), %st
; CHECK-NEXT: fld %st(3)
; CHECK-NEXT: fmul %st(5), %st
; CHECK-NEXT: fadd %st(2), %st
; CHECK-NEXT: fxch %st(5)
; CHECK-NEXT: fmul %st, %st(0)
; CHECK-NEXT: fadd %st, %st(5)
; CHECK-NEXT: fsubr %st, %st(5)
; CHECK-NEXT: fxch %st(4)
; CHECK-NEXT: fmull -8
; CHECK-NEXT: fxch %st(5)
; CHECK-NEXT: fstl 8
; CHECK-NEXT: fxch %st(2)
; CHECK-NEXT: fsubp %st, %st(5)
; CHECK-NEXT: fxch %st(4)
; CHECK-NEXT: fsubp %st, %st(2)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fadd %st(2), %st
; CHECK-NEXT: faddp %st, %st(2)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fstl 16
; CHECK-NEXT: fxch %st(2)
; CHECK-NEXT: fadd %st, %st(0)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fadd %st, %st(0)
; CHECK-NEXT: fxch %st(2)
; CHECK-NEXT: fadd %st, %st(0)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fstpl 2056(%ecx)
; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fstpl 2064(%ecx)
; CHECK-NEXT: fstpl 2072(%ecx)
; CHECK-NEXT: movl %eax, 0
; CHECK-NEXT: movl $4, 4
; CHECK-NEXT: movl $3, 8
; CHECK-NEXT: ud2
%1 = getelementptr double, double* null, i32 -1 ; <double*> [#uses=1] %1 = getelementptr double, double* null, i32 -1 ; <double*> [#uses=1]
%2 = load double, double* %1, align 8 ; <double> [#uses=1] %2 = load double, double* %1, align 8 ; <double> [#uses=1]
%3 = load double, double* null, align 8 ; <double> [#uses=2] %3 = load double, double* null, align 8 ; <double> [#uses=2]
%4 = load double, double* null, align 8 ; <double> [#uses=2] %4 = load double, double* null, align 8 ; <double> [#uses=2]
%5 = load double, double* null, align 8 ; <double> [#uses=3] %5 = load double, double* null, align 8 ; <double> [#uses=3]
%6 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0 ; <double*> [#uses=0] %6 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 0 ; <double*> [#uses=0]
%7 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 1 ; <double*> [#uses=0] %7 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 1 ; <double*> [#uses=0]
%8 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 2 ; <double*> [#uses=0] %8 = getelementptr %struct.HNodeTranslateRotate3, %struct.HNodeTranslateRotate3* %this, i32 0, i32 2, i32 0, i32 0, i32 0, i32 2 ; <double*> [#uses=0]
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llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll

; RUN: llc < %s -mtriple=x86_64-- | grep cvtsi2sd ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; LSR previously eliminated the sitofp by introducing an induction ; LSR previously eliminated the sitofp by introducing an induction
; variable which stepped by a bogus ((double)UINT32_C(-1)). It's theoretically ; variable which stepped by a bogus ((double)UINT32_C(-1)). It's theoretically
; possible to eliminate the sitofp using a proper -1.0 step though; this ; possible to eliminate the sitofp using a proper -1.0 step though; this
; test should be changed if that is done. ; test should be changed if that is done.
define void @foo(i32 %N) nounwind { define void @foo(i32 %N) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: jns .LBB0_3
; CHECK-NEXT: # %bb.1: # %bb.preheader
; CHECK-NEXT: movl %edi, %ebx
; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_2: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: cvtsi2sd %ebp, %xmm0
; CHECK-NEXT: callq bar
; CHECK-NEXT: decl %ebp
; CHECK-NEXT: cmpl %ebp, %ebx
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: .LBB0_3: # %return
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
entry: entry:
%0 = icmp slt i32 %N, 0 ; <i1> [#uses=1] %0 = icmp slt i32 %N, 0 ; <i1> [#uses=1]
br i1 %0, label %bb, label %return br i1 %0, label %bb, label %return
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
%i.03 = phi i32 [ 0, %entry ], [ %2, %bb ] ; <i32> [#uses=2] %i.03 = phi i32 [ 0, %entry ], [ %2, %bb ] ; <i32> [#uses=2]
%1 = sitofp i32 %i.03 to double ; <double> [#uses=1] %1 = sitofp i32 %i.03 to double ; <double> [#uses=1]
tail call void @bar(double %1) nounwind tail call void @bar(double %1) nounwind
Show All 9 Lines

llvm/test/CodeGen/X86/nobt.ll

; RUN: llc < %s -mtriple=i686-- | not grep btl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; This tests some cases where BT must not be generated. See also bt.ll. ; This tests some cases where BT must not be generated. See also bt.ll.
; Fixes 20040709-[12].c in gcc testsuite. ; Fixes 20040709-[12].c in gcc testsuite.
define void @test2(i32 %x, i32 %n) nounwind { define void @test2(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo
; CHECK-NEXT: .LBB0_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
%tmp4 = icmp eq i32 %tmp3, %tmp2 ; <i1> [#uses=1] %tmp4 = icmp eq i32 %tmp3, %tmp2 ; <i1> [#uses=1]
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: ; preds = %entry bb: ; preds = %entry
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }
define void @test3(i32 %x, i32 %n) nounwind { define void @test3(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB1_2
; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo
; CHECK-NEXT: .LBB1_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
%tmp4 = icmp eq i32 %tmp2, %tmp3 ; <i1> [#uses=1] %tmp4 = icmp eq i32 %tmp2, %tmp3 ; <i1> [#uses=1]
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: ; preds = %entry bb: ; preds = %entry
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }
define void @test4(i32 %x, i32 %n) nounwind { define void @test4(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB2_2
; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo
; CHECK-NEXT: .LBB2_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
%tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1] %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: ; preds = %entry bb: ; preds = %entry
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }
define void @test5(i32 %x, i32 %n) nounwind { define void @test5(i32 %x, i32 %n) nounwind {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB3_2
; CHECK-NEXT: # %bb.1: # %bb
; CHECK-NEXT: calll foo
; CHECK-NEXT: .LBB3_2: # %UnifiedReturnBlock
; CHECK-NEXT: retl
entry: entry:
%tmp1 = and i32 %x, 1 %tmp1 = and i32 %x, 1
%tmp2 = urem i32 %tmp1, 15 %tmp2 = urem i32 %tmp1, 15
%tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1] %tmp3 = and i32 %tmp2, 1 ; <i32> [#uses=1]
%tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1] %tmp4 = icmp ne i32 %tmp2, %tmp3 ; <i1> [#uses=1]
br i1 %tmp4, label %bb, label %UnifiedReturnBlock br i1 %tmp4, label %bb, label %UnifiedReturnBlock
bb: ; preds = %entry bb: ; preds = %entry
call void @foo() call void @foo()
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }
declare void @foo() declare void @foo()

llvm/test/CodeGen/X86/optimize-max-0.ll

; RUN: llc < %s | not grep cmov ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; LSR should be able to eliminate the max computations by ; LSR should be able to eliminate the max computations by
; making the loops use slt/ult comparisons instead of ne comparisons. ; making the loops use slt/ult comparisons instead of ne comparisons.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9" target triple = "i386-apple-darwin9"
define void @foo(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind { define void @foo(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: imull %edi, %eax
; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: je LBB0_19
; CHECK-NEXT: ## %bb.1: ## %bb10.preheader
; CHECK-NEXT: movl %eax, %ebp
; CHECK-NEXT: sarl $31, %ebp
; CHECK-NEXT: shrl $30, %ebp
; CHECK-NEXT: addl %eax, %ebp
; CHECK-NEXT: sarl $2, %ebp
; CHECK-NEXT: testl %ebx, %ebx
; CHECK-NEXT: jle LBB0_12
; CHECK-NEXT: ## %bb.2: ## %bb.nph9
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: jle LBB0_12
; CHECK-NEXT: ## %bb.3: ## %bb.nph9.split
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: incl %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_4: ## %bb6
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movzbl (%eax,%esi,2), %ebx
; CHECK-NEXT: movb %bl, (%edx,%esi)
; CHECK-NEXT: incl %esi
; CHECK-NEXT: cmpl %edi, %esi
; CHECK-NEXT: jl LBB0_4
; CHECK-NEXT: ## %bb.5: ## %bb9
; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: incl %ecx
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: addl %edi, %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: cmpl %ebx, %ecx
; CHECK-NEXT: je LBB0_12
; CHECK-NEXT: ## %bb.6: ## %bb7.preheader
; CHECK-NEXT: ## in Loop: Header=BB0_4 Depth=1
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: jmp LBB0_4
; CHECK-NEXT: LBB0_12: ## %bb18.loopexit
; CHECK-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: addl %ebp, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: cmpl $1, %ebx
; CHECK-NEXT: jle LBB0_13
; CHECK-NEXT: ## %bb.7: ## %bb.nph5
; CHECK-NEXT: cmpl $2, {{[0-9]+}}(%esp)
; CHECK-NEXT: jl LBB0_13
; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: sarl %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $31, %ecx
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: sarl %ecx
; CHECK-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: leal 2(%esi), %esi
; CHECK-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi ## 4-byte Reload
; CHECK-NEXT: addl %esi, %ecx
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: xorl %ebp, %ebp
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_9: ## %bb13
; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB0_10 Depth 2
; CHECK-NEXT: movl %ebp, %esi
; CHECK-NEXT: shrl $31, %esi
; CHECK-NEXT: addl %ebp, %esi
; CHECK-NEXT: andl $-2, %esi
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: subl %esi, %edi
; CHECK-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: addl %ebx, %edi
; CHECK-NEXT: imull {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Folded Reload
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_10: ## %bb14
; CHECK-NEXT: ## Parent Loop BB0_9 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: movzbl -2(%edi,%esi,4), %ebx
; CHECK-NEXT: movb %bl, (%ecx,%esi)
; CHECK-NEXT: movzbl (%edi,%esi,4), %ebx
; CHECK-NEXT: movb %bl, (%eax,%esi)
; CHECK-NEXT: incl %esi
; CHECK-NEXT: cmpl %edx, %esi
; CHECK-NEXT: jl LBB0_10
; CHECK-NEXT: ## %bb.11: ## %bb17
; CHECK-NEXT: ## in Loop: Header=BB0_9 Depth=1
; CHECK-NEXT: incl %ebp
; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx ## 4-byte Reload
; CHECK-NEXT: addl $2, %ebx
; CHECK-NEXT: addl %edx, %ecx
; CHECK-NEXT: cmpl {{[-0-9]+}}(%e{{[sb]}}p), %ebp ## 4-byte Folded Reload
; CHECK-NEXT: jl LBB0_9
; CHECK-NEXT: LBB0_13: ## %bb20
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: cmpl $1, %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: je LBB0_19
; CHECK-NEXT: ## %bb.14: ## %bb20
; CHECK-NEXT: cmpl $3, %edx
; CHECK-NEXT: jne LBB0_24
; CHECK-NEXT: ## %bb.15: ## %bb22
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi ## 4-byte Reload
; CHECK-NEXT: addl %esi, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: testl %ebx, %ebx
; CHECK-NEXT: jle LBB0_18
; CHECK-NEXT: ## %bb.16: ## %bb.nph
; CHECK-NEXT: leal 15(%ebx), %eax
; CHECK-NEXT: andl $-16, %eax
; CHECK-NEXT: imull {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: addl %eax, %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: addl $15, %eax
; CHECK-NEXT: andl $-16, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: addl %esi, %esi
; CHECK-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %esi ## 4-byte Folded Reload
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_17: ## %bb23
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: calll _memcpy
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: addl %edi, %esi
; CHECK-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ebp ## 4-byte Folded Reload
; CHECK-NEXT: decl %ebx
; CHECK-NEXT: jne LBB0_17
; CHECK-NEXT: LBB0_18: ## %bb26
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi ## 4-byte Reload
; CHECK-NEXT: addl %ecx, %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: addl %esi, %edx
; CHECK-NEXT: jmp LBB0_23
; CHECK-NEXT: LBB0_19: ## %bb29
; CHECK-NEXT: testl %ebx, %ebx
; CHECK-NEXT: jle LBB0_22
; CHECK-NEXT: ## %bb.20: ## %bb.nph11
; CHECK-NEXT: movl %edi, %esi
; CHECK-NEXT: leal 15(%edi), %eax
; CHECK-NEXT: andl $-16, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_21: ## %bb30
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: calll _memcpy
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: addl %esi, %edi
; CHECK-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ebp ## 4-byte Folded Reload
; CHECK-NEXT: decl %ebx
; CHECK-NEXT: jne LBB0_21
; CHECK-NEXT: LBB0_22: ## %bb33
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: LBB0_23: ## %bb33
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: sarl %eax
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $128
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: calll _memset
; CHECK-NEXT: addl $44, %esp
; CHECK-NEXT: LBB0_25: ## %return
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_24: ## %return
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: jmp LBB0_25
entry: entry:
%0 = mul i32 %x, %w %0 = mul i32 %x, %w
%1 = mul i32 %x, %w %1 = mul i32 %x, %w
%2 = sdiv i32 %1, 4 %2 = sdiv i32 %1, 4
%.sum2 = add i32 %2, %0 %.sum2 = add i32 %2, %0
%cond = icmp eq i32 %d, 1 %cond = icmp eq i32 %d, 1
br i1 %cond, label %bb29, label %bb10.preheader br i1 %cond, label %bb29, label %bb10.preheader
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Linesbb33: ; preds = %bb31.bb33_crit_edge, %bb29
tail call void @llvm.memset.p0i8.i32(i8* %61, i8 -128, i32 %63, i1 false) tail call void @llvm.memset.p0i8.i32(i8* %61, i8 -128, i32 %63, i1 false)
ret void ret void
return: ; preds = %bb20 return: ; preds = %bb20
ret void ret void
} }
define void @bar(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind { define void @bar(i8* %r, i32 %s, i32 %w, i32 %x, i8* %j, i32 %d) nounwind {
; CHECK-LABEL: bar:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $28, %esp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movl %ebp, %eax
; CHECK-NEXT: imull %ecx, %eax
; CHECK-NEXT: cmpl $1, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: je LBB1_19
; CHECK-NEXT: ## %bb.1: ## %bb10.preheader
; CHECK-NEXT: shrl $2, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: testl %ebp, %ebp
; CHECK-NEXT: je LBB1_12
; CHECK-NEXT: ## %bb.2: ## %bb.nph9
; CHECK-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; CHECK-NEXT: je LBB1_12
; CHECK-NEXT: ## %bb.3: ## %bb.nph9.split
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: incl %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_6: ## %bb7.preheader
; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB1_4 Depth 2
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_4: ## %bb6
; CHECK-NEXT: ## Parent Loop BB1_6 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: movzbl (%eax,%esi,2), %ebx
; CHECK-NEXT: movb %bl, (%edx,%esi)
; CHECK-NEXT: incl %esi
; CHECK-NEXT: cmpl %edi, %esi
; CHECK-NEXT: jb LBB1_4
; CHECK-NEXT: ## %bb.5: ## %bb9
; CHECK-NEXT: ## in Loop: Header=BB1_6 Depth=1
; CHECK-NEXT: incl %ecx
; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: addl %edi, %edx
; CHECK-NEXT: cmpl %ebp, %ecx
; CHECK-NEXT: jne LBB1_6
; CHECK-NEXT: LBB1_12: ## %bb18.loopexit
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: cmpl $1, %ebp
; CHECK-NEXT: jbe LBB1_13
; CHECK-NEXT: ## %bb.7: ## %bb.nph5
; CHECK-NEXT: cmpl $2, {{[0-9]+}}(%esp)
; CHECK-NEXT: jb LBB1_13
; CHECK-NEXT: ## %bb.8: ## %bb.nph5.split
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: shrl %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: leal 2(%edx), %edx
; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Reload
; CHECK-NEXT: addl %edx, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_9: ## %bb13
; CHECK-NEXT: ## =>This Loop Header: Depth=1
; CHECK-NEXT: ## Child Loop BB1_10 Depth 2
; CHECK-NEXT: movl %edi, %ebx
; CHECK-NEXT: andl $1, %ebx
; CHECK-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: addl %edx, %ebx
; CHECK-NEXT: imull {{[0-9]+}}(%esp), %ebx
; CHECK-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ebx ## 4-byte Folded Reload
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_10: ## %bb14
; CHECK-NEXT: ## Parent Loop BB1_9 Depth=1
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
; CHECK-NEXT: movzbl -2(%ebx,%esi,4), %edx
; CHECK-NEXT: movb %dl, (%eax,%esi)
; CHECK-NEXT: movzbl (%ebx,%esi,4), %edx
; CHECK-NEXT: movb %dl, (%ecx,%esi)
; CHECK-NEXT: incl %esi
; CHECK-NEXT: cmpl %ebp, %esi
; CHECK-NEXT: jb LBB1_10
; CHECK-NEXT: ## %bb.11: ## %bb17
; CHECK-NEXT: ## in Loop: Header=BB1_9 Depth=1
; CHECK-NEXT: incl %edi
; CHECK-NEXT: addl %ebp, %ecx
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Reload
; CHECK-NEXT: addl $2, %edx
; CHECK-NEXT: addl %ebp, %eax
; CHECK-NEXT: cmpl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Folded Reload
; CHECK-NEXT: jb LBB1_9
; CHECK-NEXT: LBB1_13: ## %bb20
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: cmpl $1, %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: je LBB1_19
; CHECK-NEXT: ## %bb.14: ## %bb20
; CHECK-NEXT: cmpl $3, %edx
; CHECK-NEXT: jne LBB1_24
; CHECK-NEXT: ## %bb.15: ## %bb22
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: addl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill
; CHECK-NEXT: testl %ebp, %ebp
; CHECK-NEXT: je LBB1_18
; CHECK-NEXT: ## %bb.16: ## %bb.nph
; CHECK-NEXT: movl %ebp, %esi
; CHECK-NEXT: leal 15(%ebp), %eax
; CHECK-NEXT: andl $-16, %eax
; CHECK-NEXT: imull {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: leal 15(%ecx), %ebx
; CHECK-NEXT: andl $-16, %ebx
; CHECK-NEXT: addl %eax, %edi
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: leal (%edx,%eax), %ebp
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_17: ## %bb23
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: calll _memcpy
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: addl %ecx, %ebp
; CHECK-NEXT: addl %ebx, %edi
; CHECK-NEXT: decl %esi
; CHECK-NEXT: jne LBB1_17
; CHECK-NEXT: LBB1_18: ## %bb26
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: shrl %ecx
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: pushl $128
; CHECK-NEXT: pushl %edx
; CHECK-NEXT: jmp LBB1_23
; CHECK-NEXT: LBB1_19: ## %bb29
; CHECK-NEXT: testl %ebp, %ebp
; CHECK-NEXT: je LBB1_22
; CHECK-NEXT: ## %bb.20: ## %bb.nph11
; CHECK-NEXT: movl %ebp, %esi
; CHECK-NEXT: leal 15(%ecx), %ebx
; CHECK-NEXT: andl $-16, %ebx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB1_21: ## %bb30
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: calll _memcpy
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: addl %ecx, %ebp
; CHECK-NEXT: addl %ebx, %edi
; CHECK-NEXT: decl %esi
; CHECK-NEXT: jne LBB1_21
; CHECK-NEXT: LBB1_22: ## %bb33
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax ## 4-byte Reload
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: subl $4, %esp
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $128
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: LBB1_23: ## %bb33
; CHECK-NEXT: calll _memset
; CHECK-NEXT: addl $44, %esp
; CHECK-NEXT: LBB1_25: ## %return
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
; CHECK-NEXT: LBB1_24: ## %return
; CHECK-NEXT: addl $28, %esp
; CHECK-NEXT: jmp LBB1_25
entry: entry:
%0 = mul i32 %x, %w %0 = mul i32 %x, %w
%1 = mul i32 %x, %w %1 = mul i32 %x, %w
%2 = udiv i32 %1, 4 %2 = udiv i32 %1, 4
%.sum2 = add i32 %2, %0 %.sum2 = add i32 %2, %0
%cond = icmp eq i32 %d, 1 %cond = icmp eq i32 %d, 1
br i1 %cond, label %bb29, label %bb10.preheader br i1 %cond, label %bb29, label %bb10.preheader
▲ Show 20 Lines • Show All 219 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/overlap-shift.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | FileCheck %s
;; X's live range extends beyond the shift, so the register allocator ;; X's live range extends beyond the shift, so the register allocator
;; cannot coalesce it with Y. Because of this, a copy needs to be ;; cannot coalesce it with Y. Because of this, a copy needs to be
;; emitted before the shift to save the register value before it is ;; emitted before the shift to save the register value before it is
;; clobbered. However, this copy is not needed if the register ;; clobbered. However, this copy is not needed if the register
;; allocator turns the shift into an LEA. This also occurs for ADD. ;; allocator turns the shift into an LEA. This also occurs for ADD.
; Check that the shift gets turned into an LEA. ; Check that the shift gets turned into an LEA.
; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | \
; RUN: not grep "mov E.X, E.X"
@G = external global i32 ; <i32*> [#uses=1] @G = external global i32 ; <i32*> [#uses=1]
define i32 @test1(i32 %X) { define i32 @test1(i32 %X) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: mov eax, dword ptr [esp + 4]
; CHECK-NEXT: lea ecx, [4*eax]
; CHECK-NEXT: mov dword ptr [G], ecx
; CHECK-NEXT: ret
%Z = shl i32 %X, 2 ; <i32> [#uses=1] %Z = shl i32 %X, 2 ; <i32> [#uses=1]
store volatile i32 %Z, i32* @G store volatile i32 %Z, i32* @G
ret i32 %X ret i32 %X
} }

llvm/test/CodeGen/X86/packed_struct.ll

; RUN: llc < %s > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep foos+5 %t ; RUN: llc < %s | FileCheck %s
; RUN: grep foos+1 %t
; RUN: grep foos+9 %t
; RUN: grep bara+19 %t
; RUN: grep bara+4 %t
; make sure we compute the correct offset for a packed structure ; make sure we compute the correct offset for a packed structure
;Note: codegen for this could change rendering the above checks wrong ;Note: codegen for this could change rendering the above checks wrong
target datalayout = "e-p:32:32" target datalayout = "e-p:32:32"
target triple = "i686-pc-linux-gnu" target triple = "i686-pc-linux-gnu"
%struct.anon = type <{ i8, i32, i32, i32 }> %struct.anon = type <{ i8, i32, i32, i32 }>
@foos = external global %struct.anon ; <%struct.anon*> [#uses=3] @foos = external global %struct.anon ; <%struct.anon*> [#uses=3]
@bara = weak global [4 x <{ i32, i8 }>] zeroinitializer ; <[4 x <{ i32, i8 }>]*> [#uses=2] @bara = weak global [4 x <{ i32, i8 }>] zeroinitializer ; <[4 x <{ i32, i8 }>]*> [#uses=2]
define i32 @foo() nounwind { define i32 @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl foos+5, %eax
; CHECK-NEXT: addl foos+1, %eax
; CHECK-NEXT: addl foos+9, %eax
; CHECK-NEXT: retl
entry: entry:
%tmp = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 1) ; <i32> [#uses=1] %tmp = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 1) ; <i32> [#uses=1]
%tmp3 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 2) ; <i32> [#uses=1] %tmp3 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 2) ; <i32> [#uses=1]
%tmp6 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 3) ; <i32> [#uses=1] %tmp6 = load i32, i32* getelementptr (%struct.anon, %struct.anon* @foos, i32 0, i32 3) ; <i32> [#uses=1]
%tmp4 = add i32 %tmp3, %tmp ; <i32> [#uses=1] %tmp4 = add i32 %tmp3, %tmp ; <i32> [#uses=1]
%tmp7 = add i32 %tmp4, %tmp6 ; <i32> [#uses=1] %tmp7 = add i32 %tmp4, %tmp6 ; <i32> [#uses=1]
ret i32 %tmp7 ret i32 %tmp7
} }
define i8 @bar() nounwind { define i8 @bar() nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb bara+19, %al
; CHECK-NEXT: addb bara+4, %al
; CHECK-NEXT: retl
entry: entry:
%tmp = load i8, i8* getelementptr ([4 x <{ i32, i8 }>], [4 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 1) ; <i8> [#uses=1] %tmp = load i8, i8* getelementptr ([4 x <{ i32, i8 }>], [4 x <{ i32, i8 }>]* @bara, i32 0, i32 0, i32 1) ; <i8> [#uses=1]
%tmp4 = load i8, i8* getelementptr ([4 x <{ i32, i8 }>], [4 x <{ i32, i8 }>]* @bara, i32 0, i32 3, i32 1) ; <i8> [#uses=1] %tmp4 = load i8, i8* getelementptr ([4 x <{ i32, i8 }>], [4 x <{ i32, i8 }>]* @bara, i32 0, i32 3, i32 1) ; <i8> [#uses=1]
%tmp5 = add i8 %tmp4, %tmp ; <i8> [#uses=1] %tmp5 = add i8 %tmp4, %tmp ; <i8> [#uses=1]
ret i8 %tmp5 ret i8 %tmp5
} }

llvm/test/CodeGen/X86/peep-test-0.ll

; RUN: llc < %s -mtriple=x86_64-- > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep cmp %t ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; RUN: not grep test %t
define void @loop(i64 %n, double* nocapture %d) nounwind { define void @loop(i64 %n, double* nocapture %d) nounwind {
; CHECK-LABEL: loop:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: shlq $4, %rax
; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: mulsd %xmm0, %xmm1
; CHECK-NEXT: movsd %xmm1, (%rax)
; CHECK-NEXT: addq $8, %rax
; CHECK-NEXT: incq %rdi
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %return
; CHECK-NEXT: retq
entry: entry:
br label %bb br label %bb
bb: bb:
%indvar = phi i64 [ %n, %entry ], [ %indvar.next, %bb ] %indvar = phi i64 [ %n, %entry ], [ %indvar.next, %bb ]
%i.03 = add i64 %indvar, %n %i.03 = add i64 %indvar, %n
%0 = getelementptr double, double* %d, i64 %i.03 %0 = getelementptr double, double* %d, i64 %i.03
%1 = load double, double* %0, align 8 %1 = load double, double* %0, align 8
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llvm/test/CodeGen/X86/peep-test-1.ll

; RUN: llc < %s -mtriple=i686-- > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep dec %t | count 1 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; RUN: not grep test %t
; RUN: not grep cmp %t
define void @foo(i32 %n, double* nocapture %p) nounwind { define void @foo(i32 %n, double* nocapture %p) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: fldl (%eax,%ecx,8)
; CHECK-NEXT: fmull {{\.LCPI.*}}
; CHECK-NEXT: fstpl (%eax,%ecx,8)
; CHECK-NEXT: decl %ecx
; CHECK-NEXT: js .LBB0_1
; CHECK-NEXT: # %bb.2: # %return
; CHECK-NEXT: retl
br label %bb br label %bb
bb: bb:
%indvar = phi i32 [ 0, %0 ], [ %indvar.next, %bb ] %indvar = phi i32 [ 0, %0 ], [ %indvar.next, %bb ]
%i.03 = sub i32 %n, %indvar %i.03 = sub i32 %n, %indvar
%1 = getelementptr double, double* %p, i32 %i.03 %1 = getelementptr double, double* %p, i32 %i.03
%2 = load double, double* %1, align 4 %2 = load double, double* %1, align 4
%3 = fmul double %2, 2.930000e+00 %3 = fmul double %2, 2.930000e+00
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llvm/test/CodeGen/X86/pic-load-remat.ll

; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | FileCheck %s
define void @f() nounwind { define void @f() nounwind {
; CHECK-LABEL: f:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: calll L0$pb
; CHECK-NEXT: L0$pb:
; CHECK-NEXT: popl %eax
; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1]
; CHECK-NEXT: psllw LCPI0_1-L0$pb(%eax), %xmm1
; CHECK-NEXT: pavgw LCPI0_2-L0$pb(%eax), %xmm0
; CHECK-NEXT: paddsw %xmm0, %xmm0
; CHECK-NEXT: paddw %xmm1, %xmm0
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_1: ## %bb
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movdqa %xmm0, 0
; CHECK-NEXT: jmp LBB0_1
entry: entry:
br label %bb br label %bb
bb: ; preds = %bb, %entry bb: ; preds = %bb, %entry
%tmp4403 = tail call <8 x i16> @llvm.ssub.sat.v8i16( <8 x i16> zeroinitializer, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=2] %tmp4403 = tail call <8 x i16> @llvm.ssub.sat.v8i16( <8 x i16> zeroinitializer, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=2]
%tmp4443 = tail call <8 x i16> @llvm.sadd.sat.v8i16( <8 x i16> zeroinitializer, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1] %tmp4443 = tail call <8 x i16> @llvm.sadd.sat.v8i16( <8 x i16> zeroinitializer, <8 x i16> zeroinitializer ) nounwind readnone ; <<8 x i16>> [#uses=1]
%tmp4609 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 3, i32 5, i32 6, i32 9 > to <8 x i16>) ) ; <<8 x i16>> [#uses=1] %tmp4609 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> zeroinitializer, <8 x i16> bitcast (<4 x i32> < i32 3, i32 5, i32 6, i32 9 > to <8 x i16>) ) ; <<8 x i16>> [#uses=1]
%tmp4651 = add <8 x i16> %tmp4609, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <<8 x i16>> [#uses=1] %tmp4651 = add <8 x i16> %tmp4609, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1 > ; <<8 x i16>> [#uses=1]
Show All 21 Linesbb: ; preds = %bb, %entry
store <2 x i64> %tmp4829, <2 x i64>* null, align 16 store <2 x i64> %tmp4829, <2 x i64>* null, align 16
store <2 x i64> %tmp4958, <2 x i64>* null, align 16 store <2 x i64> %tmp4958, <2 x i64>* null, align 16
store <2 x i64> %tmp4968, <2 x i64>* null, align 16 store <2 x i64> %tmp4968, <2 x i64>* null, align 16
store <2 x i64> %tmp4950, <2 x i64>* null, align 16 store <2 x i64> %tmp4950, <2 x i64>* null, align 16
store <2 x i64> %tmp4708, <2 x i64>* null, align 16 store <2 x i64> %tmp4708, <2 x i64>* null, align 16
br label %bb br label %bb
} }
declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) nounwind readnone

llvm/test/CodeGen/X86/postalloc-coalescing.ll

; RUN: llc < %s -mtriple=i686-- | grep mov | count 3 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define fastcc i32 @_Z18yy_get_next_bufferv() nounwind { define fastcc i32 @_Z18yy_get_next_bufferv() nounwind {
; CHECK-LABEL: _Z18yy_get_next_bufferv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb116
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movb %al, 0
; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: .LBB0_3: # %bb158
; CHECK-NEXT: movb %al, 0
; CHECK-NEXT: cmpl $-1, %eax
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
entry: entry:
br label %bb131 br label %bb131
bb116: ; preds = %bb131 bb116: ; preds = %bb131
%tmp125126 = trunc i32 %c.1 to i8 ; <i8> [#uses=1] %tmp125126 = trunc i32 %c.1 to i8 ; <i8> [#uses=1]
store i8 %tmp125126, i8* null, align 1 store i8 %tmp125126, i8* null, align 1
br label %bb131 br label %bb131
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llvm/test/CodeGen/X86/pr1489.ll

; RUN: llc < %s -frame-pointer=all -O0 -mcpu=i486 | grep 1082126238 | count 3 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -frame-pointer=all -O0 -mcpu=i486 | grep -- -1236950581 | count 1 ; RUN: llc < %s -frame-pointer=all -O0 -mcpu=i486 | FileCheck %s
;; magic constants are 3.999f and half of 3.999 ;; magic constants are 3.999f and half of 3.999
; ModuleID = '1489.c' ; ModuleID = '1489.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
@.str = internal constant [13 x i8] c"%d %d %d %d\0A\00" ; <[13 x i8]*> [#uses=1] @.str = internal constant [13 x i8] c"%d %d %d %d\0A\00" ; <[13 x i8]*> [#uses=1]
define i32 @quux() nounwind { define i32 @quux() nounwind {
; CHECK-LABEL: quux:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: movl $1082126238, (%eax) ## imm = 0x407FEF9E
; CHECK-NEXT: calll _lrintf
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: setl %cl
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1] %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1] %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
%tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1] %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
ret i32 %tmp23 ret i32 %tmp23
} }
declare i32 @lrintf(float) declare i32 @lrintf(float)
define i32 @foo() nounwind { define i32 @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: movl $1074789875, 4(%eax) ## imm = 0x400FFDF3
; CHECK-NEXT: movl $-1236950581, (%eax) ## imm = 0xB645A1CB
; CHECK-NEXT: calll _lrint
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: setl %cl
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%tmp1 = tail call i32 @lrint( double 3.999000e+00 ) ; <i32> [#uses=1] %tmp1 = tail call i32 @lrint( double 3.999000e+00 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1] %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
%tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1] %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
ret i32 %tmp23 ret i32 %tmp23
} }
declare i32 @lrint(double) declare i32 @lrint(double)
define i32 @bar() nounwind { define i32 @bar() nounwind {
; CHECK-LABEL: bar:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: movl $1082126238, (%eax) ## imm = 0x407FEF9E
; CHECK-NEXT: calll _lrintf
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: setl %cl
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1] %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1] %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
%tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1] %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
ret i32 %tmp23 ret i32 %tmp23
} }
define i32 @baz() nounwind { define i32 @baz() nounwind {
; CHECK-LABEL: baz:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: movl $1082126238, (%eax) ## imm = 0x407FEF9E
; CHECK-NEXT: calll _lrintf
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: setl %cl
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1] %tmp1 = tail call i32 @lrintf( float 0x400FFDF3C0000000 ) ; <i32> [#uses=1]
%tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1] %tmp2 = icmp slt i32 %tmp1, 1 ; <i1> [#uses=1]
%tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1] %tmp23 = zext i1 %tmp2 to i32 ; <i32> [#uses=1]
ret i32 %tmp23 ret i32 %tmp23
} }
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $48, %esp
; CHECK-NEXT: calll _baz
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: calll _bar
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: calll _foo
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: calll _quux
; CHECK-NEXT: movl %esp, %ecx
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx ## 4-byte Reload
; CHECK-NEXT: movl %edx, 16(%ecx)
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi ## 4-byte Reload
; CHECK-NEXT: movl %esi, 12(%ecx)
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Reload
; CHECK-NEXT: movl %edi, 8(%ecx)
; CHECK-NEXT: movl %eax, 4(%ecx)
; CHECK-NEXT: movl $_.str, (%ecx)
; CHECK-NEXT: calll _printf
; CHECK-NEXT: ## implicit-def: $ecx
; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Spill
; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: addl $48, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
%tmp = tail call i32 @baz( ) ; <i32> [#uses=1] %tmp = tail call i32 @baz( ) ; <i32> [#uses=1]
%tmp1 = tail call i32 @bar( ) ; <i32> [#uses=1] %tmp1 = tail call i32 @bar( ) ; <i32> [#uses=1]
%tmp2 = tail call i32 @foo( ) ; <i32> [#uses=1] %tmp2 = tail call i32 @foo( ) ; <i32> [#uses=1]
%tmp3 = tail call i32 @quux( ) ; <i32> [#uses=1] %tmp3 = tail call i32 @quux( ) ; <i32> [#uses=1]
%tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %tmp3, i32 %tmp2, i32 %tmp1, i32 %tmp ) ; <i32> [#uses=0] %tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %tmp3, i32 %tmp2, i32 %tmp1, i32 %tmp ) ; <i32> [#uses=0]
ret i32 undef ret i32 undef
} }
declare i32 @printf(i8*, ...) declare i32 @printf(i8*, ...)

llvm/test/CodeGen/X86/pr1505.ll

; RUN: llc < %s -mcpu=i486 | not grep fldl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=i486 | FileCheck %s
; PR1505 ; PR1505
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
@G = weak global float 0.000000e+00 ; <float*> [#uses=1] @G = weak global float 0.000000e+00 ; <float*> [#uses=1]
define void @t1(float %F) { define void @t1(float %F) {
; CHECK-LABEL: t1:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: movl L_G$non_lazy_ptr, %eax
; CHECK-NEXT: fstps (%eax)
; CHECK-NEXT: retl
entry: entry:
store float %F, float* @G store float %F, float* @G
ret void ret void
} }

llvm/test/CodeGen/X86/pr2326.ll

; RUN: llc < %s -mtriple=i686-- | grep sete ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; PR2326 ; PR2326
define i32 @func_59(i32 %p_60) nounwind { define i32 @func_59(i32 %p_60) nounwind {
; CHECK-LABEL: func_59:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movl 0, %eax
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl (%esp), %eax
; CHECK-NEXT: sete %cl
; CHECK-NEXT: pushl $0
; CHECK-NEXT: pushl %ecx
; CHECK-NEXT: calll func_15
entry: entry:
%l_108 = alloca i32 ; <i32*> [#uses=2] %l_108 = alloca i32 ; <i32*> [#uses=2]
%tmp15 = load i32, i32* null, align 4 ; <i32> [#uses=1] %tmp15 = load i32, i32* null, align 4 ; <i32> [#uses=1]
%tmp16 = load i32, i32* %l_108, align 4 ; <i32> [#uses=1] %tmp16 = load i32, i32* %l_108, align 4 ; <i32> [#uses=1]
%tmp17 = icmp eq i32 %tmp15, %tmp16 ; <i1> [#uses=1] %tmp17 = icmp eq i32 %tmp15, %tmp16 ; <i1> [#uses=1]
%tmp1718 = zext i1 %tmp17 to i8 ; <i8> [#uses=1] %tmp1718 = zext i1 %tmp17 to i8 ; <i8> [#uses=1]
%tmp19 = load i32, i32* null, align 4 ; <i32> [#uses=1] %tmp19 = load i32, i32* null, align 4 ; <i32> [#uses=1]
%tmp20 = load i32, i32* %l_108, align 4 ; <i32> [#uses=1] %tmp20 = load i32, i32* %l_108, align 4 ; <i32> [#uses=1]
Show All 12 Lines

llvm/test/CodeGen/X86/pr3366.ll

; RUN: llc < %s -mtriple=i686-- -disable-cgp-branch-opts | grep movzbl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -disable-cgp-branch-opts | FileCheck %s
; PR3366 ; PR3366
define void @_ada_c34002a() nounwind { define void @_ada_c34002a() nounwind {
; CHECK-LABEL: _ada_c34002a:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $90, %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: idivb 0
; CHECK-NEXT: cmpb $3, %al
; CHECK-NEXT: # %bb.1: # %bb457
entry: entry:
%0 = load i8, i8* null, align 1 %0 = load i8, i8* null, align 1
%1 = sdiv i8 90, %0 %1 = sdiv i8 90, %0
%2 = icmp ne i8 %1, 3 %2 = icmp ne i8 %1, 3
%3 = zext i1 %2 to i8 %3 = zext i1 %2 to i8
%toBool449 = icmp ne i8 %3, 0 %toBool449 = icmp ne i8 %3, 0
%4 = or i1 false, %toBool449 %4 = or i1 false, %toBool449
%5 = zext i1 %4 to i8 %5 = zext i1 %4 to i8
Show All 9 Lines

llvm/test/CodeGen/X86/pr3457.ll

; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | not grep fstpt ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
; PR3457 ; PR3457
; rdar://6548010 ; rdar://6548010
define void @foo(double* nocapture %P) nounwind { define void @foo(double* nocapture %P) nounwind {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: subl $24, %esp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: calll _test
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, (%esp) ## 8-byte Spill
; CHECK-NEXT: calll _test
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%esp), %xmm1 ## 8-byte Reload
; CHECK-NEXT: ## xmm1 = mem[0],zero
; CHECK-NEXT: mulsd %xmm1, %xmm1
; CHECK-NEXT: mulsd %xmm0, %xmm0
; CHECK-NEXT: addsd %xmm1, %xmm0
; CHECK-NEXT: movsd %xmm0, (%esi)
; CHECK-NEXT: addl $24, %esp
; CHECK-NEXT: popl %esi
; CHECK-NEXT: retl
entry: entry:
%0 = tail call double (...) @test() nounwind ; <double> [#uses=2] %0 = tail call double (...) @test() nounwind ; <double> [#uses=2]
%1 = tail call double (...) @test() nounwind ; <double> [#uses=2] %1 = tail call double (...) @test() nounwind ; <double> [#uses=2]
%2 = fmul double %0, %0 ; <double> [#uses=1] %2 = fmul double %0, %0 ; <double> [#uses=1]
%3 = fmul double %1, %1 ; <double> [#uses=1] %3 = fmul double %1, %1 ; <double> [#uses=1]
%4 = fadd double %2, %3 ; <double> [#uses=1] %4 = fadd double %2, %3 ; <double> [#uses=1]
store double %4, double* %P, align 8 store double %4, double* %P, align 8
ret void ret void
} }
declare double @test(...) declare double @test(...)

llvm/test/CodeGen/X86/remat-constant.ll

; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static | grep xmm | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static | FileCheck %s
declare void @bar() nounwind declare void @bar() nounwind
@a = external constant float @a = external constant float
declare void @qux(float %f) nounwind declare void @qux(float %f) nounwind
define void @foo() nounwind { define void @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: callq bar
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: callq qux
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: callq qux
; CHECK-NEXT: popq %rax
; CHECK-NEXT: retq
%f = load float, float* @a %f = load float, float* @a
call void @bar() call void @bar()
call void @qux(float %f) call void @qux(float %f)
call void @qux(float %f) call void @qux(float %f)
ret void ret void
} }

llvm/test/CodeGen/X86/ret-addr.ll

; RUN: llc < %s -frame-pointer=all -mtriple=i686-- | not grep xor ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -frame-pointer=all -mtriple=x86_64-- | not grep xor ; RUN: llc < %s -frame-pointer=all -mtriple=i686-- | FileCheck %s --check-prefix=i686
; RUN: llc < %s -frame-pointer=all -mtriple=x86_64-- | FileCheck %s --check-prefix=x86_64
define i8* @h() nounwind readnone optsize { define i8* @h() nounwind readnone optsize {
; i686-LABEL: h:
; i686: # %bb.0: # %entry
; i686-NEXT: pushl %ebp
; i686-NEXT: movl %esp, %ebp
; i686-NEXT: movl (%ebp), %eax
; i686-NEXT: movl (%eax), %eax
; i686-NEXT: movl 4(%eax), %eax
; i686-NEXT: popl %ebp
; i686-NEXT: retl
;
; x86_64-LABEL: h:
; x86_64: # %bb.0: # %entry
; x86_64-NEXT: pushq %rbp
; x86_64-NEXT: movq %rsp, %rbp
; x86_64-NEXT: movq (%rbp), %rax
; x86_64-NEXT: movq (%rax), %rax
; x86_64-NEXT: movq 8(%rax), %rax
; x86_64-NEXT: popq %rbp
; x86_64-NEXT: retq
entry: entry:
%0 = tail call i8* @llvm.returnaddress(i32 2) ; <i8*> [#uses=1] %0 = tail call i8* @llvm.returnaddress(i32 2) ; <i8*> [#uses=1]
ret i8* %0 ret i8* %0
} }
declare i8* @llvm.returnaddress(i32) nounwind readnone declare i8* @llvm.returnaddress(i32) nounwind readnone
define i8* @g() nounwind readnone optsize { define i8* @g() nounwind readnone optsize {
; i686-LABEL: g:
; i686: # %bb.0: # %entry
; i686-NEXT: pushl %ebp
; i686-NEXT: movl %esp, %ebp
; i686-NEXT: movl (%ebp), %eax
; i686-NEXT: movl 4(%eax), %eax
; i686-NEXT: popl %ebp
; i686-NEXT: retl
;
; x86_64-LABEL: g:
; x86_64: # %bb.0: # %entry
; x86_64-NEXT: pushq %rbp
; x86_64-NEXT: movq %rsp, %rbp
; x86_64-NEXT: movq (%rbp), %rax
; x86_64-NEXT: movq 8(%rax), %rax
; x86_64-NEXT: popq %rbp
; x86_64-NEXT: retq
entry: entry:
%0 = tail call i8* @llvm.returnaddress(i32 1) ; <i8*> [#uses=1] %0 = tail call i8* @llvm.returnaddress(i32 1) ; <i8*> [#uses=1]
ret i8* %0 ret i8* %0
} }
define i8* @f() nounwind readnone optsize { define i8* @f() nounwind readnone optsize {
; i686-LABEL: f:
; i686: # %bb.0: # %entry
; i686-NEXT: pushl %ebp
; i686-NEXT: movl %esp, %ebp
; i686-NEXT: movl 4(%ebp), %eax
; i686-NEXT: popl %ebp
; i686-NEXT: retl
;
; x86_64-LABEL: f:
; x86_64: # %bb.0: # %entry
; x86_64-NEXT: pushq %rbp
; x86_64-NEXT: movq %rsp, %rbp
; x86_64-NEXT: movq 8(%rbp), %rax
; x86_64-NEXT: popq %rbp
; x86_64-NEXT: retq
entry: entry:
%0 = tail call i8* @llvm.returnaddress(i32 0) ; <i8*> [#uses=1] %0 = tail call i8* @llvm.returnaddress(i32 0) ; <i8*> [#uses=1]
ret i8* %0 ret i8* %0
} }

llvm/test/CodeGen/X86/ret-i64-0.ll

; RUN: llc < %s -mtriple=i686-- | grep xor | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i64 @foo() nounwind { define i64 @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: retl
ret i64 0 ret i64 0
} }

llvm/test/CodeGen/X86/scalar-extract.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+mmx -o %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep movq %t ; RUN: llc < %s -mtriple=i686-- -mattr=+mmx | FileCheck %s
; Check that widening doesn't introduce a mmx register in this case when ; Check that widening doesn't introduce a mmx register in this case when
; a simple load/store would suffice. ; a simple load/store would suffice.
define void @foo(<2 x i16>* %A, <2 x i16>* %B) { define void @foo(<2 x i16>* %A, <2 x i16>* %B) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl (%ecx), %ecx
; CHECK-NEXT: movl %ecx, (%eax)
; CHECK-NEXT: retl
entry: entry:
%tmp1 = load <2 x i16>, <2 x i16>* %A ; <<2 x i16>> [#uses=1] %tmp1 = load <2 x i16>, <2 x i16>* %A ; <<2 x i16>> [#uses=1]
store <2 x i16> %tmp1, <2 x i16>* %B store <2 x i16> %tmp1, <2 x i16>* %B
ret void ret void
} }

llvm/test/CodeGen/X86/setuge.ll

; RUN: llc < %s -mtriple=i686-- | not grep set ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
declare i1 @llvm.isunordered.f32(float, float) declare i1 @llvm.isunordered.f32(float, float)
define float @cmp(float %A, float %B, float %C, float %D) nounwind { define float @cmp(float %A, float %B, float %C, float %D) nounwind {
; CHECK-LABEL: cmp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: fucompp
; CHECK-NEXT: fnstsw %ax
; CHECK-NEXT: # kill: def $ah killed $ah killed $ax
; CHECK-NEXT: sahf
; CHECK-NEXT: jbe .LBB0_1
; CHECK-NEXT: # %bb.2: # %entry
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: flds (%eax)
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: flds (%eax)
; CHECK-NEXT: retl
entry: entry:
%tmp.1 = fcmp uno float %A, %B ; <i1> [#uses=1] %tmp.1 = fcmp uno float %A, %B ; <i1> [#uses=1]
%tmp.2 = fcmp oge float %A, %B ; <i1> [#uses=1] %tmp.2 = fcmp oge float %A, %B ; <i1> [#uses=1]
%tmp.3 = or i1 %tmp.1, %tmp.2 ; <i1> [#uses=1] %tmp.3 = or i1 %tmp.1, %tmp.2 ; <i1> [#uses=1]
%tmp.4 = select i1 %tmp.3, float %C, float %D ; <float> [#uses=1] %tmp.4 = select i1 %tmp.3, float %C, float %D ; <float> [#uses=1]
ret float %tmp.4 ret float %tmp.4
} }

llvm/test/CodeGen/X86/shift-coalesce.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | \ ; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | FileCheck %s
; RUN: grep "shld.*cl"
; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | \
; RUN: not grep "mov cl, bl"
; PR687 ; PR687
define i64 @foo(i64 %x, i64* %X) { define i64 @foo(i64 %x, i64* %X) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: push esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset esi, -8
; CHECK-NEXT: mov esi, dword ptr [esp + 8]
; CHECK-NEXT: mov edx, dword ptr [esp + 12]
; CHECK-NEXT: mov eax, dword ptr [esp + 16]
; CHECK-NEXT: mov cl, byte ptr [eax]
; CHECK-NEXT: mov eax, esi
; CHECK-NEXT: shl eax, cl
; CHECK-NEXT: shld edx, esi, cl
; CHECK-NEXT: test cl, 32
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mov edx, eax
; CHECK-NEXT: xor eax, eax
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: pop esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: ret
%tmp.1 = load i64, i64* %X ; <i64> [#uses=1] %tmp.1 = load i64, i64* %X ; <i64> [#uses=1]
%tmp.3 = trunc i64 %tmp.1 to i8 ; <i8> [#uses=1] %tmp.3 = trunc i64 %tmp.1 to i8 ; <i8> [#uses=1]
%shift.upgrd.1 = zext i8 %tmp.3 to i64 ; <i64> [#uses=1] %shift.upgrd.1 = zext i8 %tmp.3 to i64 ; <i64> [#uses=1]
%tmp.4 = shl i64 %x, %shift.upgrd.1 ; <i64> [#uses=1] %tmp.4 = shl i64 %x, %shift.upgrd.1 ; <i64> [#uses=1]
ret i64 %tmp.4 ret i64 %tmp.4
} }

llvm/test/CodeGen/X86/shift-i128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,i686
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=CHECK,X64 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=ALL,x86_64
; ;
; Scalars ; Scalars
; ;
define void @test_lshr_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind { define void @test_lshr_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind {
; X86-LABEL: test_lshr_i128: ; i686-LABEL: test_lshr_i128:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: pushl %ebp ; i686-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; i686-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; i686-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; i686-NEXT: pushl %esi
; X86-NEXT: subl $20, %esp ; i686-NEXT: subl $20, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; i686-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ebp, %esi ; i686-NEXT: movl %ebp, %esi
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: shrdl %cl, %edi, %esi ; i686-NEXT: shrdl %cl, %edi, %esi
; X86-NEXT: shrl %cl, %edx ; i686-NEXT: shrl %cl, %edx
; X86-NEXT: shrl %cl, %edi ; i686-NEXT: shrl %cl, %edi
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: jne .LBB0_1 ; i686-NEXT: jne .LBB0_1
; X86-NEXT: # %bb.2: # %entry ; i686-NEXT: # %bb.2: # %entry
; X86-NEXT: movl %edx, (%esp) # 4-byte Spill ; i686-NEXT: movl %edx, (%esp) # 4-byte Spill
; X86-NEXT: jmp .LBB0_3 ; i686-NEXT: jmp .LBB0_3
; X86-NEXT: .LBB0_1: ; i686-NEXT: .LBB0_1:
; X86-NEXT: movl %edi, %esi ; i686-NEXT: movl %edi, %esi
; X86-NEXT: movl $0, (%esp) # 4-byte Folded Spill ; i686-NEXT: movl $0, (%esp) # 4-byte Folded Spill
; X86-NEXT: xorl %edi, %edi ; i686-NEXT: xorl %edi, %edi
; X86-NEXT: .LBB0_3: # %entry ; i686-NEXT: .LBB0_3: # %entry
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %eax, %edx ; i686-NEXT: movl %eax, %edx
; X86-NEXT: subb $64, %dl ; i686-NEXT: subb $64, %dl
; X86-NEXT: jb .LBB0_5 ; i686-NEXT: jb .LBB0_5
; X86-NEXT: # %bb.4: # %entry ; i686-NEXT: # %bb.4: # %entry
; X86-NEXT: xorl %edi, %edi ; i686-NEXT: xorl %edi, %edi
; X86-NEXT: .LBB0_5: # %entry ; i686-NEXT: .LBB0_5: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: negb %dl ; i686-NEXT: negb %dl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: shldl %cl, %ebp, %edi ; i686-NEXT: shldl %cl, %ebp, %edi
; X86-NEXT: movl %ebp, %esi ; i686-NEXT: movl %ebp, %esi
; X86-NEXT: shll %cl, %esi ; i686-NEXT: shll %cl, %esi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl %esi, %ebx ; i686-NEXT: movl %esi, %ebx
; X86-NEXT: jne .LBB0_7 ; i686-NEXT: jne .LBB0_7
; X86-NEXT: # %bb.6: # %entry ; i686-NEXT: # %bb.6: # %entry
; X86-NEXT: movl %edi, %ebx ; i686-NEXT: movl %edi, %ebx
; X86-NEXT: .LBB0_7: # %entry ; i686-NEXT: .LBB0_7: # %entry
; X86-NEXT: movb %al, %ah ; i686-NEXT: movb %al, %ah
; X86-NEXT: addb $-64, %ah ; i686-NEXT: addb $-64, %ah
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movb %ah, %cl ; i686-NEXT: movb %ah, %cl
; X86-NEXT: shrl %cl, %edi ; i686-NEXT: shrl %cl, %edi
; X86-NEXT: testb $32, %ah ; i686-NEXT: testb $32, %ah
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB0_9 ; i686-NEXT: jne .LBB0_9
; X86-NEXT: # %bb.8: # %entry ; i686-NEXT: # %bb.8: # %entry
; X86-NEXT: movl %edi, %ecx ; i686-NEXT: movl %edi, %ecx
; X86-NEXT: .LBB0_9: # %entry ; i686-NEXT: .LBB0_9: # %entry
; X86-NEXT: cmpb $64, %al ; i686-NEXT: cmpb $64, %al
; X86-NEXT: jb .LBB0_10 ; i686-NEXT: jb .LBB0_10
; X86-NEXT: # %bb.11: # %entry ; i686-NEXT: # %bb.11: # %entry
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB0_12 ; i686-NEXT: jmp .LBB0_12
; X86-NEXT: .LBB0_10: ; i686-NEXT: .LBB0_10:
; X86-NEXT: movl (%esp), %ecx # 4-byte Reload ; i686-NEXT: movl (%esp), %ecx # 4-byte Reload
; X86-NEXT: orl %ebx, %ecx ; i686-NEXT: orl %ebx, %ecx
; X86-NEXT: .LBB0_12: # %entry ; i686-NEXT: .LBB0_12: # %entry
; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill ; i686-NEXT: movl %ecx, (%esp) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: jne .LBB0_14 ; i686-NEXT: jne .LBB0_14
; X86-NEXT: # %bb.13: # %entry ; i686-NEXT: # %bb.13: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB0_14: # %entry ; i686-NEXT: .LBB0_14: # %entry
; X86-NEXT: movl %ebx, %edx ; i686-NEXT: movl %ebx, %edx
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shrdl %cl, %esi, %edx ; i686-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: jne .LBB0_16 ; i686-NEXT: jne .LBB0_16
; X86-NEXT: # %bb.15: # %entry ; i686-NEXT: # %bb.15: # %entry
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB0_16: # %entry ; i686-NEXT: .LBB0_16: # %entry
; X86-NEXT: movb %ah, %cl ; i686-NEXT: movb %ah, %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: shrdl %cl, %edx, %ebp ; i686-NEXT: shrdl %cl, %edx, %ebp
; X86-NEXT: testb $32, %ah ; i686-NEXT: testb $32, %ah
; X86-NEXT: jne .LBB0_18 ; i686-NEXT: jne .LBB0_18
; X86-NEXT: # %bb.17: # %entry ; i686-NEXT: # %bb.17: # %entry
; X86-NEXT: movl %ebp, %edi ; i686-NEXT: movl %ebp, %edi
; X86-NEXT: .LBB0_18: # %entry ; i686-NEXT: .LBB0_18: # %entry
; X86-NEXT: cmpb $64, %al ; i686-NEXT: cmpb $64, %al
; X86-NEXT: jae .LBB0_20 ; i686-NEXT: jae .LBB0_20
; X86-NEXT: # %bb.19: ; i686-NEXT: # %bb.19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: .LBB0_20: # %entry ; i686-NEXT: .LBB0_20: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: je .LBB0_22 ; i686-NEXT: je .LBB0_22
; X86-NEXT: # %bb.21: # %entry ; i686-NEXT: # %bb.21: # %entry
; X86-NEXT: movl %edi, %ebx ; i686-NEXT: movl %edi, %ebx
; X86-NEXT: movl (%esp), %esi # 4-byte Reload ; i686-NEXT: movl (%esp), %esi # 4-byte Reload
; X86-NEXT: .LBB0_22: # %entry ; i686-NEXT: .LBB0_22: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, 12(%ecx) ; i686-NEXT: movl %eax, 12(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, 8(%ecx) ; i686-NEXT: movl %eax, 8(%ecx)
; X86-NEXT: movl %esi, 4(%ecx) ; i686-NEXT: movl %esi, 4(%ecx)
; X86-NEXT: movl %ebx, (%ecx) ; i686-NEXT: movl %ebx, (%ecx)
; X86-NEXT: addl $20, %esp ; i686-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; i686-NEXT: popl %esi
; X86-NEXT: popl %edi ; i686-NEXT: popl %edi
; X86-NEXT: popl %ebx ; i686-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; i686-NEXT: popl %ebp
; X86-NEXT: retl ; i686-NEXT: retl
; ;
; X64-LABEL: test_lshr_i128: ; x86_64-LABEL: test_lshr_i128:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: movq %rdx, %rcx ; x86_64-NEXT: movq %rdx, %rcx
; X64-NEXT: shrdq %cl, %rsi, %rdi ; x86_64-NEXT: shrdq %cl, %rsi, %rdi
; X64-NEXT: shrq %cl, %rsi ; x86_64-NEXT: shrq %cl, %rsi
; X64-NEXT: xorl %eax, %eax ; x86_64-NEXT: xorl %eax, %eax
; X64-NEXT: testb $64, %cl ; x86_64-NEXT: testb $64, %cl
; X64-NEXT: cmovneq %rsi, %rdi ; x86_64-NEXT: cmovneq %rsi, %rdi
; X64-NEXT: cmoveq %rsi, %rax ; x86_64-NEXT: cmoveq %rsi, %rax
; X64-NEXT: movq %rax, 8(%r8) ; x86_64-NEXT: movq %rax, 8(%r8)
; X64-NEXT: movq %rdi, (%r8) ; x86_64-NEXT: movq %rdi, (%r8)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = lshr i128 %x, %a %0 = lshr i128 %x, %a
store i128 %0, i128* %r, align 16 store i128 %0, i128* %r, align 16
ret void ret void
} }
define void @test_ashr_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind { define void @test_ashr_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind {
; X86-LABEL: test_ashr_i128: ; i686-LABEL: test_ashr_i128:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: pushl %ebp ; i686-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; i686-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; i686-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; i686-NEXT: pushl %esi
; X86-NEXT: subl $24, %esp ; i686-NEXT: subl $24, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; i686-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ebp, %esi ; i686-NEXT: movl %ebp, %esi
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: shrdl %cl, %ebx, %esi ; i686-NEXT: shrdl %cl, %ebx, %esi
; X86-NEXT: shrl %cl, %edx ; i686-NEXT: shrl %cl, %edx
; X86-NEXT: movl %ebx, %edi ; i686-NEXT: movl %ebx, %edi
; X86-NEXT: sarl %cl, %edi ; i686-NEXT: sarl %cl, %edi
; X86-NEXT: sarl $31, %ebx ; i686-NEXT: sarl $31, %ebx
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB1_1 ; i686-NEXT: jne .LBB1_1
; X86-NEXT: # %bb.2: # %entry ; i686-NEXT: # %bb.2: # %entry
; X86-NEXT: movl %edx, (%esp) # 4-byte Spill ; i686-NEXT: movl %edx, (%esp) # 4-byte Spill
; X86-NEXT: jmp .LBB1_3 ; i686-NEXT: jmp .LBB1_3
; X86-NEXT: .LBB1_1: ; i686-NEXT: .LBB1_1:
; X86-NEXT: movl %edi, %esi ; i686-NEXT: movl %edi, %esi
; X86-NEXT: movl $0, (%esp) # 4-byte Folded Spill ; i686-NEXT: movl $0, (%esp) # 4-byte Folded Spill
; X86-NEXT: movl %ebx, %edi ; i686-NEXT: movl %ebx, %edi
; X86-NEXT: .LBB1_3: # %entry ; i686-NEXT: .LBB1_3: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %eax, %edx ; i686-NEXT: movl %eax, %edx
; X86-NEXT: subb $64, %dl ; i686-NEXT: subb $64, %dl
; X86-NEXT: jb .LBB1_5 ; i686-NEXT: jb .LBB1_5
; X86-NEXT: # %bb.4: # %entry ; i686-NEXT: # %bb.4: # %entry
; X86-NEXT: movl %ebx, %edi ; i686-NEXT: movl %ebx, %edi
; X86-NEXT: .LBB1_5: # %entry ; i686-NEXT: .LBB1_5: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: negb %dl ; i686-NEXT: negb %dl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: shldl %cl, %ebp, %edi ; i686-NEXT: shldl %cl, %ebp, %edi
; X86-NEXT: movl %ebp, %esi ; i686-NEXT: movl %ebp, %esi
; X86-NEXT: shll %cl, %esi ; i686-NEXT: shll %cl, %esi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl %esi, %ecx ; i686-NEXT: movl %esi, %ecx
; X86-NEXT: jne .LBB1_7 ; i686-NEXT: jne .LBB1_7
; X86-NEXT: # %bb.6: # %entry ; i686-NEXT: # %bb.6: # %entry
; X86-NEXT: movl %edi, %ecx ; i686-NEXT: movl %edi, %ecx
; X86-NEXT: .LBB1_7: # %entry ; i686-NEXT: .LBB1_7: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movb %al, %ah ; i686-NEXT: movb %al, %ah
; X86-NEXT: addb $-64, %ah ; i686-NEXT: addb $-64, %ah
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movb %ah, %cl ; i686-NEXT: movb %ah, %cl
; X86-NEXT: sarl %cl, %edi ; i686-NEXT: sarl %cl, %edi
; X86-NEXT: testb $32, %ah ; i686-NEXT: testb $32, %ah
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: jne .LBB1_9 ; i686-NEXT: jne .LBB1_9
; X86-NEXT: # %bb.8: # %entry ; i686-NEXT: # %bb.8: # %entry
; X86-NEXT: movl %edi, %ecx ; i686-NEXT: movl %edi, %ecx
; X86-NEXT: .LBB1_9: # %entry ; i686-NEXT: .LBB1_9: # %entry
; X86-NEXT: cmpb $64, %al ; i686-NEXT: cmpb $64, %al
; X86-NEXT: jb .LBB1_10 ; i686-NEXT: jb .LBB1_10
; X86-NEXT: # %bb.11: # %entry ; i686-NEXT: # %bb.11: # %entry
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jmp .LBB1_12 ; i686-NEXT: jmp .LBB1_12
; X86-NEXT: .LBB1_10: ; i686-NEXT: .LBB1_10:
; X86-NEXT: movl (%esp), %ecx # 4-byte Reload ; i686-NEXT: movl (%esp), %ecx # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: .LBB1_12: # %entry ; i686-NEXT: .LBB1_12: # %entry
; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill ; i686-NEXT: movl %ecx, (%esp) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: jne .LBB1_14 ; i686-NEXT: jne .LBB1_14
; X86-NEXT: # %bb.13: # %entry ; i686-NEXT: # %bb.13: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB1_14: # %entry ; i686-NEXT: .LBB1_14: # %entry
; X86-NEXT: movl %ebx, %edx ; i686-NEXT: movl %ebx, %edx
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shrdl %cl, %esi, %edx ; i686-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: jne .LBB1_16 ; i686-NEXT: jne .LBB1_16
; X86-NEXT: # %bb.15: # %entry ; i686-NEXT: # %bb.15: # %entry
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB1_16: # %entry ; i686-NEXT: .LBB1_16: # %entry
; X86-NEXT: movb %ah, %cl ; i686-NEXT: movb %ah, %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: shrdl %cl, %edx, %ebp ; i686-NEXT: shrdl %cl, %edx, %ebp
; X86-NEXT: testb $32, %ah ; i686-NEXT: testb $32, %ah
; X86-NEXT: jne .LBB1_18 ; i686-NEXT: jne .LBB1_18
; X86-NEXT: # %bb.17: # %entry ; i686-NEXT: # %bb.17: # %entry
; X86-NEXT: movl %ebp, %edi ; i686-NEXT: movl %ebp, %edi
; X86-NEXT: .LBB1_18: # %entry ; i686-NEXT: .LBB1_18: # %entry
; X86-NEXT: cmpb $64, %al ; i686-NEXT: cmpb $64, %al
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jae .LBB1_20 ; i686-NEXT: jae .LBB1_20
; X86-NEXT: # %bb.19: ; i686-NEXT: # %bb.19:
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, %edi ; i686-NEXT: movl %ecx, %edi
; X86-NEXT: .LBB1_20: # %entry ; i686-NEXT: .LBB1_20: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: je .LBB1_22 ; i686-NEXT: je .LBB1_22
; X86-NEXT: # %bb.21: # %entry ; i686-NEXT: # %bb.21: # %entry
; X86-NEXT: movl %edi, %ebx ; i686-NEXT: movl %edi, %ebx
; X86-NEXT: movl (%esp), %esi # 4-byte Reload ; i686-NEXT: movl (%esp), %esi # 4-byte Reload
; X86-NEXT: .LBB1_22: # %entry ; i686-NEXT: .LBB1_22: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, 12(%ecx) ; i686-NEXT: movl %eax, 12(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, 8(%ecx) ; i686-NEXT: movl %eax, 8(%ecx)
; X86-NEXT: movl %esi, 4(%ecx) ; i686-NEXT: movl %esi, 4(%ecx)
; X86-NEXT: movl %ebx, (%ecx) ; i686-NEXT: movl %ebx, (%ecx)
; X86-NEXT: addl $24, %esp ; i686-NEXT: addl $24, %esp
; X86-NEXT: popl %esi ; i686-NEXT: popl %esi
; X86-NEXT: popl %edi ; i686-NEXT: popl %edi
; X86-NEXT: popl %ebx ; i686-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; i686-NEXT: popl %ebp
; X86-NEXT: retl ; i686-NEXT: retl
; ;
; X64-LABEL: test_ashr_i128: ; x86_64-LABEL: test_ashr_i128:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: movq %rdx, %rcx ; x86_64-NEXT: movq %rdx, %rcx
; X64-NEXT: shrdq %cl, %rsi, %rdi ; x86_64-NEXT: shrdq %cl, %rsi, %rdi
; X64-NEXT: movq %rsi, %rax ; x86_64-NEXT: movq %rsi, %rax
; X64-NEXT: sarq %cl, %rax ; x86_64-NEXT: sarq %cl, %rax
; X64-NEXT: sarq $63, %rsi ; x86_64-NEXT: sarq $63, %rsi
; X64-NEXT: testb $64, %cl ; x86_64-NEXT: testb $64, %cl
; X64-NEXT: cmovneq %rax, %rdi ; x86_64-NEXT: cmovneq %rax, %rdi
; X64-NEXT: cmoveq %rax, %rsi ; x86_64-NEXT: cmoveq %rax, %rsi
; X64-NEXT: movq %rsi, 8(%r8) ; x86_64-NEXT: movq %rsi, 8(%r8)
; X64-NEXT: movq %rdi, (%r8) ; x86_64-NEXT: movq %rdi, (%r8)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = ashr i128 %x, %a %0 = ashr i128 %x, %a
store i128 %0, i128* %r, align 16 store i128 %0, i128* %r, align 16
ret void ret void
} }
define void @test_shl_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind { define void @test_shl_i128(i128 %x, i128 %a, i128* nocapture %r) nounwind {
; X86-LABEL: test_shl_i128: ; i686-LABEL: test_shl_i128:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: pushl %ebp ; i686-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; i686-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; i686-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; i686-NEXT: pushl %esi
; X86-NEXT: subl $20, %esp ; i686-NEXT: subl $20, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; i686-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: shll %cl, %ebx ; i686-NEXT: shll %cl, %ebx
; X86-NEXT: movl %ebp, %esi ; i686-NEXT: movl %ebp, %esi
; X86-NEXT: shll %cl, %esi ; i686-NEXT: shll %cl, %esi
; X86-NEXT: movl %edi, %edx ; i686-NEXT: movl %edi, %edx
; X86-NEXT: shldl %cl, %ebp, %edx ; i686-NEXT: shldl %cl, %ebp, %edx
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: jne .LBB2_1 ; i686-NEXT: jne .LBB2_1
; X86-NEXT: # %bb.2: # %entry ; i686-NEXT: # %bb.2: # %entry
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, (%esp) # 4-byte Spill ; i686-NEXT: movl %ebx, (%esp) # 4-byte Spill
; X86-NEXT: jmp .LBB2_3 ; i686-NEXT: jmp .LBB2_3
; X86-NEXT: .LBB2_1: ; i686-NEXT: .LBB2_1:
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, (%esp) # 4-byte Folded Spill ; i686-NEXT: movl $0, (%esp) # 4-byte Folded Spill
; X86-NEXT: xorl %esi, %esi ; i686-NEXT: xorl %esi, %esi
; X86-NEXT: .LBB2_3: # %entry ; i686-NEXT: .LBB2_3: # %entry
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %eax, %edx ; i686-NEXT: movl %eax, %edx
; X86-NEXT: subb $64, %dl ; i686-NEXT: subb $64, %dl
; X86-NEXT: jb .LBB2_5 ; i686-NEXT: jb .LBB2_5
; X86-NEXT: # %bb.4: # %entry ; i686-NEXT: # %bb.4: # %entry
; X86-NEXT: xorl %esi, %esi ; i686-NEXT: xorl %esi, %esi
; X86-NEXT: .LBB2_5: # %entry ; i686-NEXT: .LBB2_5: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: negb %dl ; i686-NEXT: negb %dl
; X86-NEXT: movl %edi, %esi ; i686-NEXT: movl %edi, %esi
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: shrl %cl, %esi ; i686-NEXT: shrl %cl, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: shrdl %cl, %edi, %ebx ; i686-NEXT: shrdl %cl, %edi, %ebx
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl %esi, %ebp ; i686-NEXT: movl %esi, %ebp
; X86-NEXT: jne .LBB2_7 ; i686-NEXT: jne .LBB2_7
; X86-NEXT: # %bb.6: # %entry ; i686-NEXT: # %bb.6: # %entry
; X86-NEXT: movl %ebx, %ebp ; i686-NEXT: movl %ebx, %ebp
; X86-NEXT: .LBB2_7: # %entry ; i686-NEXT: .LBB2_7: # %entry
; X86-NEXT: movb %al, %ah ; i686-NEXT: movb %al, %ah
; X86-NEXT: addb $-64, %ah ; i686-NEXT: addb $-64, %ah
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movb %ah, %cl ; i686-NEXT: movb %ah, %cl
; X86-NEXT: shll %cl, %ebx ; i686-NEXT: shll %cl, %ebx
; X86-NEXT: testb $32, %ah ; i686-NEXT: testb $32, %ah
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB2_9 ; i686-NEXT: jne .LBB2_9
; X86-NEXT: # %bb.8: # %entry ; i686-NEXT: # %bb.8: # %entry
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: .LBB2_9: # %entry ; i686-NEXT: .LBB2_9: # %entry
; X86-NEXT: cmpb $64, %al ; i686-NEXT: cmpb $64, %al
; X86-NEXT: jb .LBB2_10 ; i686-NEXT: jb .LBB2_10
; X86-NEXT: # %bb.11: # %entry ; i686-NEXT: # %bb.11: # %entry
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: jmp .LBB2_12 ; i686-NEXT: jmp .LBB2_12
; X86-NEXT: .LBB2_10: ; i686-NEXT: .LBB2_10:
; X86-NEXT: movl (%esp), %ecx # 4-byte Reload ; i686-NEXT: movl (%esp), %ecx # 4-byte Reload
; X86-NEXT: orl %ebp, %ecx ; i686-NEXT: orl %ebp, %ecx
; X86-NEXT: .LBB2_12: # %entry ; i686-NEXT: .LBB2_12: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill ; i686-NEXT: movl %ecx, (%esp) # 4-byte Spill
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: jne .LBB2_14 ; i686-NEXT: jne .LBB2_14
; X86-NEXT: # %bb.13: # %entry ; i686-NEXT: # %bb.13: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB2_14: # %entry ; i686-NEXT: .LBB2_14: # %entry
; X86-NEXT: movl %edx, %esi ; i686-NEXT: movl %edx, %esi
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: shldl %cl, %ebp, %esi ; i686-NEXT: shldl %cl, %ebp, %esi
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: jne .LBB2_16 ; i686-NEXT: jne .LBB2_16
; X86-NEXT: # %bb.15: # %entry ; i686-NEXT: # %bb.15: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB2_16: # %entry ; i686-NEXT: .LBB2_16: # %entry
; X86-NEXT: movb %ah, %cl ; i686-NEXT: movb %ah, %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shldl %cl, %esi, %edi ; i686-NEXT: shldl %cl, %esi, %edi
; X86-NEXT: testb $32, %ah ; i686-NEXT: testb $32, %ah
; X86-NEXT: jne .LBB2_18 ; i686-NEXT: jne .LBB2_18
; X86-NEXT: # %bb.17: # %entry ; i686-NEXT: # %bb.17: # %entry
; X86-NEXT: movl %edi, %ebx ; i686-NEXT: movl %edi, %ebx
; X86-NEXT: .LBB2_18: # %entry ; i686-NEXT: .LBB2_18: # %entry
; X86-NEXT: cmpb $64, %al ; i686-NEXT: cmpb $64, %al
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: jae .LBB2_20 ; i686-NEXT: jae .LBB2_20
; X86-NEXT: # %bb.19: ; i686-NEXT: # %bb.19:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload
; X86-NEXT: .LBB2_20: # %entry ; i686-NEXT: .LBB2_20: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: je .LBB2_22 ; i686-NEXT: je .LBB2_22
; X86-NEXT: # %bb.21: # %entry ; i686-NEXT: # %bb.21: # %entry
; X86-NEXT: movl %ebx, %edx ; i686-NEXT: movl %ebx, %edx
; X86-NEXT: movl (%esp), %ebp # 4-byte Reload ; i686-NEXT: movl (%esp), %ebp # 4-byte Reload
; X86-NEXT: .LBB2_22: # %entry ; i686-NEXT: .LBB2_22: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, 4(%ecx) ; i686-NEXT: movl %eax, 4(%ecx)
; X86-NEXT: movl %esi, (%ecx) ; i686-NEXT: movl %esi, (%ecx)
; X86-NEXT: movl %edx, 12(%ecx) ; i686-NEXT: movl %edx, 12(%ecx)
; X86-NEXT: movl %ebp, 8(%ecx) ; i686-NEXT: movl %ebp, 8(%ecx)
; X86-NEXT: addl $20, %esp ; i686-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; i686-NEXT: popl %esi
; X86-NEXT: popl %edi ; i686-NEXT: popl %edi
; X86-NEXT: popl %ebx ; i686-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; i686-NEXT: popl %ebp
; X86-NEXT: retl ; i686-NEXT: retl
; ;
; X64-LABEL: test_shl_i128: ; x86_64-LABEL: test_shl_i128:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: movq %rdx, %rcx ; x86_64-NEXT: movq %rdx, %rcx
; X64-NEXT: shldq %cl, %rdi, %rsi ; x86_64-NEXT: shldq %cl, %rdi, %rsi
; X64-NEXT: shlq %cl, %rdi ; x86_64-NEXT: shlq %cl, %rdi
; X64-NEXT: xorl %eax, %eax ; x86_64-NEXT: xorl %eax, %eax
; X64-NEXT: testb $64, %cl ; x86_64-NEXT: testb $64, %cl
; X64-NEXT: cmovneq %rdi, %rsi ; x86_64-NEXT: cmovneq %rdi, %rsi
; X64-NEXT: cmoveq %rdi, %rax ; x86_64-NEXT: cmoveq %rdi, %rax
; X64-NEXT: movq %rsi, 8(%r8) ; x86_64-NEXT: movq %rsi, 8(%r8)
; X64-NEXT: movq %rax, (%r8) ; x86_64-NEXT: movq %rax, (%r8)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = shl i128 %x, %a %0 = shl i128 %x, %a
store i128 %0, i128* %r, align 16 store i128 %0, i128* %r, align 16
ret void ret void
} }
define void @test_lshr_i128_outofrange(i128 %x, i128* nocapture %r) nounwind { define void @test_lshr_i128_outofrange(i128 %x, i128* nocapture %r) nounwind {
; CHECK-LABEL: test_lshr_i128_outofrange: ; ALL-LABEL: test_lshr_i128_outofrange:
; CHECK: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; CHECK-NEXT: ret{{[l|q]}} ; ALL-NEXT: ret{{[l|q]}}
entry: entry:
%0 = lshr i128 %x, -1 %0 = lshr i128 %x, -1
store i128 %0, i128* %r, align 16 store i128 %0, i128* %r, align 16
ret void ret void
} }
define void @test_ashr_i128_outofrange(i128 %x, i128* nocapture %r) nounwind { define void @test_ashr_i128_outofrange(i128 %x, i128* nocapture %r) nounwind {
; CHECK-LABEL: test_ashr_i128_outofrange: ; ALL-LABEL: test_ashr_i128_outofrange:
; CHECK: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; CHECK-NEXT: ret{{[l|q]}} ; ALL-NEXT: ret{{[l|q]}}
entry: entry:
%0 = ashr i128 %x, -1 %0 = ashr i128 %x, -1
store i128 %0, i128* %r, align 16 store i128 %0, i128* %r, align 16
ret void ret void
} }
define void @test_shl_i128_outofrange(i128 %x, i128* nocapture %r) nounwind { define void @test_shl_i128_outofrange(i128 %x, i128* nocapture %r) nounwind {
; CHECK-LABEL: test_shl_i128_outofrange: ; ALL-LABEL: test_shl_i128_outofrange:
; CHECK: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; CHECK-NEXT: ret{{[l|q]}} ; ALL-NEXT: ret{{[l|q]}}
entry: entry:
%0 = shl i128 %x, -1 %0 = shl i128 %x, -1
store i128 %0, i128* %r, align 16 store i128 %0, i128* %r, align 16
ret void ret void
} }
; ;
; Vectors ; Vectors
; ;
define void @test_lshr_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind { define void @test_lshr_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind {
; X86-LABEL: test_lshr_v2i128: ; i686-LABEL: test_lshr_v2i128:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: pushl %ebp ; i686-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; i686-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; i686-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; i686-NEXT: pushl %esi
; X86-NEXT: subl $68, %esp ; i686-NEXT: subl $68, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %ebx, %edi ; i686-NEXT: movl %ebx, %edi
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: shrl %cl, %edi ; i686-NEXT: shrl %cl, %edi
; X86-NEXT: movl %esi, %ebp ; i686-NEXT: movl %esi, %ebp
; X86-NEXT: shrl %cl, %ebp ; i686-NEXT: shrl %cl, %ebp
; X86-NEXT: shrdl %cl, %esi, %edx ; i686-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: jne .LBB6_1 ; i686-NEXT: jne .LBB6_1
; X86-NEXT: # %bb.2: # %entry ; i686-NEXT: # %bb.2: # %entry
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jmp .LBB6_3 ; i686-NEXT: jmp .LBB6_3
; X86-NEXT: .LBB6_1: ; i686-NEXT: .LBB6_1:
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .LBB6_3: # %entry ; i686-NEXT: .LBB6_3: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: shrdl %cl, %ebx, %esi ; i686-NEXT: shrdl %cl, %ebx, %esi
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: jne .LBB6_5 ; i686-NEXT: jne .LBB6_5
; X86-NEXT: # %bb.4: # %entry ; i686-NEXT: # %bb.4: # %entry
; X86-NEXT: movl %esi, %edi ; i686-NEXT: movl %esi, %edi
; X86-NEXT: .LBB6_5: # %entry ; i686-NEXT: .LBB6_5: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: shrl %cl, %ebx ; i686-NEXT: shrl %cl, %ebx
; X86-NEXT: shrl %cl, %ebp ; i686-NEXT: shrl %cl, %ebp
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: subl $64, %ecx ; i686-NEXT: subl $64, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; i686-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB6_7 ; i686-NEXT: jne .LBB6_7
; X86-NEXT: # %bb.6: # %entry ; i686-NEXT: # %bb.6: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: .LBB6_7: # %entry ; i686-NEXT: .LBB6_7: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: shrdl %cl, %ebp, %esi ; i686-NEXT: shrdl %cl, %ebp, %esi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: jne .LBB6_9 ; i686-NEXT: jne .LBB6_9
; X86-NEXT: # %bb.8: # %entry ; i686-NEXT: # %bb.8: # %entry
; X86-NEXT: movl %esi, %ebx ; i686-NEXT: movl %esi, %ebx
; X86-NEXT: .LBB6_9: # %entry ; i686-NEXT: .LBB6_9: # %entry
; X86-NEXT: movl %edi, %esi ; i686-NEXT: movl %edi, %esi
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: shrl %cl, %ebp ; i686-NEXT: shrl %cl, %ebp
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB6_11 ; i686-NEXT: jne .LBB6_11
; X86-NEXT: # %bb.10: # %entry ; i686-NEXT: # %bb.10: # %entry
; X86-NEXT: movl %ebp, %ecx ; i686-NEXT: movl %ebp, %ecx
; X86-NEXT: .LBB6_11: # %entry ; i686-NEXT: .LBB6_11: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movb $64, %cl ; i686-NEXT: movb $64, %cl
; X86-NEXT: subb %dl, %cl ; i686-NEXT: subb %dl, %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: shldl %cl, %ebx, %edi ; i686-NEXT: shldl %cl, %ebx, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, %edi ; i686-NEXT: movl %ebx, %edi
; X86-NEXT: shll %cl, %edi ; i686-NEXT: shll %cl, %edi
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movb $64, %bl ; i686-NEXT: movb $64, %bl
; X86-NEXT: jne .LBB6_12 ; i686-NEXT: jne .LBB6_12
; X86-NEXT: # %bb.13: # %entry ; i686-NEXT: # %bb.13: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jmp .LBB6_14 ; i686-NEXT: jmp .LBB6_14
; X86-NEXT: .LBB6_12: ; i686-NEXT: .LBB6_12:
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .LBB6_14: # %entry ; i686-NEXT: .LBB6_14: # %entry
; X86-NEXT: movl %esi, %edi ; i686-NEXT: movl %esi, %edi
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: shrdl %cl, %ebp, %esi ; i686-NEXT: shrdl %cl, %ebp, %esi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: jne .LBB6_16 ; i686-NEXT: jne .LBB6_16
; X86-NEXT: # %bb.15: # %entry ; i686-NEXT: # %bb.15: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB6_16: # %entry ; i686-NEXT: .LBB6_16: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: subb %al, %bl ; i686-NEXT: subb %al, %bl
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: shll %cl, %ebp ; i686-NEXT: shll %cl, %ebp
; X86-NEXT: testb $32, %bl ; i686-NEXT: testb $32, %bl
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB6_18 ; i686-NEXT: jne .LBB6_18
; X86-NEXT: # %bb.17: # %entry ; i686-NEXT: # %bb.17: # %entry
; X86-NEXT: movl %ebp, %ecx ; i686-NEXT: movl %ebp, %ecx
; X86-NEXT: .LBB6_18: # %entry ; i686-NEXT: .LBB6_18: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: subl $64, %ecx ; i686-NEXT: subl $64, %ecx
; X86-NEXT: sbbl $0, %esi ; i686-NEXT: sbbl $0, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: sbbl $0, %esi ; i686-NEXT: sbbl $0, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: sbbl $0, %esi ; i686-NEXT: sbbl $0, %esi
; X86-NEXT: setae %bh ; i686-NEXT: setae %bh
; X86-NEXT: jb .LBB6_20 ; i686-NEXT: jb .LBB6_20
; X86-NEXT: # %bb.19: # %entry ; i686-NEXT: # %bb.19: # %entry
; X86-NEXT: xorl %edi, %edi ; i686-NEXT: xorl %edi, %edi
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .LBB6_20: # %entry ; i686-NEXT: .LBB6_20: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shrdl %cl, %esi, %edi ; i686-NEXT: shrdl %cl, %esi, %edi
; X86-NEXT: shrl %cl, %esi ; i686-NEXT: shrl %cl, %esi
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB6_22 ; i686-NEXT: jne .LBB6_22
; X86-NEXT: # %bb.21: # %entry ; i686-NEXT: # %bb.21: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB6_22: # %entry ; i686-NEXT: .LBB6_22: # %entry
; X86-NEXT: testb %bh, %bh ; i686-NEXT: testb %bh, %bh
; X86-NEXT: jne .LBB6_24 ; i686-NEXT: jne .LBB6_24
; X86-NEXT: # %bb.23: ; i686-NEXT: # %bb.23:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB6_24: # %entry ; i686-NEXT: .LBB6_24: # %entry
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB6_26 ; i686-NEXT: jne .LBB6_26
; X86-NEXT: # %bb.25: # %entry ; i686-NEXT: # %bb.25: # %entry
; X86-NEXT: movl %esi, %ecx ; i686-NEXT: movl %esi, %ecx
; X86-NEXT: .LBB6_26: # %entry ; i686-NEXT: .LBB6_26: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: shldl %cl, %edi, %esi ; i686-NEXT: shldl %cl, %edi, %esi
; X86-NEXT: testb $32, %bl ; i686-NEXT: testb $32, %bl
; X86-NEXT: jne .LBB6_28 ; i686-NEXT: jne .LBB6_28
; X86-NEXT: # %bb.27: # %entry ; i686-NEXT: # %bb.27: # %entry
; X86-NEXT: movl %esi, %ebp ; i686-NEXT: movl %esi, %ebp
; X86-NEXT: .LBB6_28: # %entry ; i686-NEXT: .LBB6_28: # %entry
; X86-NEXT: testb %bh, %bh ; i686-NEXT: testb %bh, %bh
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: jne .LBB6_30 ; i686-NEXT: jne .LBB6_30
; X86-NEXT: # %bb.29: ; i686-NEXT: # %bb.29:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: orl %ebp, %ecx ; i686-NEXT: orl %ebp, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB6_30: # %entry ; i686-NEXT: .LBB6_30: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: jne .LBB6_32 ; i686-NEXT: jne .LBB6_32
; X86-NEXT: # %bb.31: # %entry ; i686-NEXT: # %bb.31: # %entry
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .LBB6_32: # %entry ; i686-NEXT: .LBB6_32: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: shrdl %cl, %ebp, %edi ; i686-NEXT: shrdl %cl, %ebp, %edi
; X86-NEXT: movl %edi, %ebp ; i686-NEXT: movl %edi, %ebp
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: je .LBB6_33 ; i686-NEXT: je .LBB6_33
; X86-NEXT: # %bb.34: # %entry ; i686-NEXT: # %bb.34: # %entry
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: jne .LBB6_35 ; i686-NEXT: jne .LBB6_35
; X86-NEXT: .LBB6_36: # %entry ; i686-NEXT: .LBB6_36: # %entry
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: je .LBB6_38 ; i686-NEXT: je .LBB6_38
; X86-NEXT: .LBB6_37: ; i686-NEXT: .LBB6_37:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB6_38: # %entry ; i686-NEXT: .LBB6_38: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: orl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: orl {{[0-9]+}}(%esp), %edx ; i686-NEXT: orl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl %ecx, %edx ; i686-NEXT: orl %ecx, %edx
; X86-NEXT: je .LBB6_40 ; i686-NEXT: je .LBB6_40
; X86-NEXT: # %bb.39: # %entry ; i686-NEXT: # %bb.39: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: .LBB6_40: # %entry ; i686-NEXT: .LBB6_40: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl {{[0-9]+}}(%esp), %edx ; i686-NEXT: orl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl {{[0-9]+}}(%esp), %eax ; i686-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl %edx, %eax ; i686-NEXT: orl %edx, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: je .LBB6_42 ; i686-NEXT: je .LBB6_42
; X86-NEXT: # %bb.41: # %entry ; i686-NEXT: # %bb.41: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: .LBB6_42: # %entry ; i686-NEXT: .LBB6_42: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 28(%ecx) ; i686-NEXT: movl %edx, 28(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 24(%ecx) ; i686-NEXT: movl %edx, 24(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 12(%ecx) ; i686-NEXT: movl %edx, 12(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 8(%ecx) ; i686-NEXT: movl %edx, 8(%ecx)
; X86-NEXT: movl %esi, 20(%ecx) ; i686-NEXT: movl %esi, 20(%ecx)
; X86-NEXT: movl %eax, 16(%ecx) ; i686-NEXT: movl %eax, 16(%ecx)
; X86-NEXT: movl %ebx, 4(%ecx) ; i686-NEXT: movl %ebx, 4(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, (%ecx) ; i686-NEXT: movl %eax, (%ecx)
; X86-NEXT: addl $68, %esp ; i686-NEXT: addl $68, %esp
; X86-NEXT: popl %esi ; i686-NEXT: popl %esi
; X86-NEXT: popl %edi ; i686-NEXT: popl %edi
; X86-NEXT: popl %ebx ; i686-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; i686-NEXT: popl %ebp
; X86-NEXT: retl ; i686-NEXT: retl
; X86-NEXT: .LBB6_33: # %entry ; i686-NEXT: .LBB6_33: # %entry
; X86-NEXT: movl %ebp, %edi ; i686-NEXT: movl %ebp, %edi
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: je .LBB6_36 ; i686-NEXT: je .LBB6_36
; X86-NEXT: .LBB6_35: ; i686-NEXT: .LBB6_35:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, %edi ; i686-NEXT: movl %ecx, %edi
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: jne .LBB6_37 ; i686-NEXT: jne .LBB6_37
; X86-NEXT: jmp .LBB6_38 ; i686-NEXT: jmp .LBB6_38
; ;
; X64-LABEL: test_lshr_v2i128: ; x86_64-LABEL: test_lshr_v2i128:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: movq %rcx, %rax ; x86_64-NEXT: movq %rcx, %rax
; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 ; x86_64-NEXT: movq {{[0-9]+}}(%rsp), %r10
; X64-NEXT: movb {{[0-9]+}}(%rsp), %r9b ; x86_64-NEXT: movb {{[0-9]+}}(%rsp), %r9b
; X64-NEXT: movl %r9d, %ecx ; x86_64-NEXT: movl %r9d, %ecx
; X64-NEXT: shrdq %cl, %rax, %rdx ; x86_64-NEXT: shrdq %cl, %rax, %rdx
; X64-NEXT: movl %r8d, %ecx ; x86_64-NEXT: movl %r8d, %ecx
; X64-NEXT: shrdq %cl, %rsi, %rdi ; x86_64-NEXT: shrdq %cl, %rsi, %rdi
; X64-NEXT: shrq %cl, %rsi ; x86_64-NEXT: shrq %cl, %rsi
; X64-NEXT: xorl %r11d, %r11d ; x86_64-NEXT: xorl %r11d, %r11d
; X64-NEXT: testb $64, %r8b ; x86_64-NEXT: testb $64, %r8b
; X64-NEXT: cmovneq %rsi, %rdi ; x86_64-NEXT: cmovneq %rsi, %rdi
; X64-NEXT: cmovneq %r11, %rsi ; x86_64-NEXT: cmovneq %r11, %rsi
; X64-NEXT: movl %r9d, %ecx ; x86_64-NEXT: movl %r9d, %ecx
; X64-NEXT: shrq %cl, %rax ; x86_64-NEXT: shrq %cl, %rax
; X64-NEXT: testb $64, %r9b ; x86_64-NEXT: testb $64, %r9b
; X64-NEXT: cmovneq %rax, %rdx ; x86_64-NEXT: cmovneq %rax, %rdx
; X64-NEXT: cmovneq %r11, %rax ; x86_64-NEXT: cmovneq %r11, %rax
; X64-NEXT: movq %rax, 24(%r10) ; x86_64-NEXT: movq %rax, 24(%r10)
; X64-NEXT: movq %rdx, 16(%r10) ; x86_64-NEXT: movq %rdx, 16(%r10)
; X64-NEXT: movq %rsi, 8(%r10) ; x86_64-NEXT: movq %rsi, 8(%r10)
; X64-NEXT: movq %rdi, (%r10) ; x86_64-NEXT: movq %rdi, (%r10)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = lshr <2 x i128> %x, %a %0 = lshr <2 x i128> %x, %a
store <2 x i128> %0, <2 x i128>* %r, align 16 store <2 x i128> %0, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_ashr_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind { define void @test_ashr_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind {
; X86-LABEL: test_ashr_v2i128: ; i686-LABEL: test_ashr_v2i128:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: pushl %ebp ; i686-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; i686-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; i686-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; i686-NEXT: pushl %esi
; X86-NEXT: subl $80, %esp ; i686-NEXT: subl $80, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %ebp, %ebx ; i686-NEXT: movl %ebp, %ebx
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: sarl %cl, %ebx ; i686-NEXT: sarl %cl, %ebx
; X86-NEXT: movl %esi, %edi ; i686-NEXT: movl %esi, %edi
; X86-NEXT: shrl %cl, %edi ; i686-NEXT: shrl %cl, %edi
; X86-NEXT: shrdl %cl, %esi, %edx ; i686-NEXT: shrdl %cl, %esi, %edx
; X86-NEXT: sarl $31, %ebp ; i686-NEXT: sarl $31, %ebp
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jne .LBB7_1 ; i686-NEXT: jne .LBB7_1
; X86-NEXT: # %bb.2: # %entry ; i686-NEXT: # %bb.2: # %entry
; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jmp .LBB7_3 ; i686-NEXT: jmp .LBB7_3
; X86-NEXT: .LBB7_1: ; i686-NEXT: .LBB7_1:
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_3: # %entry ; i686-NEXT: .LBB7_3: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: shrdl %cl, %edx, %edi ; i686-NEXT: shrdl %cl, %edx, %edi
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: jne .LBB7_5 ; i686-NEXT: jne .LBB7_5
; X86-NEXT: # %bb.4: # %entry ; i686-NEXT: # %bb.4: # %entry
; X86-NEXT: movl %edi, %ebx ; i686-NEXT: movl %edi, %ebx
; X86-NEXT: .LBB7_5: # %entry ; i686-NEXT: .LBB7_5: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ebp, %edi ; i686-NEXT: movl %ebp, %edi
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: sarl %cl, %edi ; i686-NEXT: sarl %cl, %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shrl %cl, %esi ; i686-NEXT: shrl %cl, %esi
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: sarl $31, %ebp ; i686-NEXT: sarl $31, %ebp
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: subl $64, %ecx ; i686-NEXT: subl $64, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; i686-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl $0, %esi ; i686-NEXT: movl $0, %esi
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebp, %ecx ; i686-NEXT: movl %ebp, %ecx
; X86-NEXT: jne .LBB7_7 ; i686-NEXT: jne .LBB7_7
; X86-NEXT: # %bb.6: # %entry ; i686-NEXT: # %bb.6: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl %edi, %ecx ; i686-NEXT: movl %edi, %ecx
; X86-NEXT: .LBB7_7: # %entry ; i686-NEXT: .LBB7_7: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: shrdl %cl, %ebp, %esi ; i686-NEXT: shrdl %cl, %ebp, %esi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: jne .LBB7_9 ; i686-NEXT: jne .LBB7_9
; X86-NEXT: # %bb.8: # %entry ; i686-NEXT: # %bb.8: # %entry
; X86-NEXT: movl %esi, %edi ; i686-NEXT: movl %esi, %edi
; X86-NEXT: .LBB7_9: # %entry ; i686-NEXT: .LBB7_9: # %entry
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: sarl %cl, %esi ; i686-NEXT: sarl %cl, %esi
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: jne .LBB7_11 ; i686-NEXT: jne .LBB7_11
; X86-NEXT: # %bb.10: # %entry ; i686-NEXT: # %bb.10: # %entry
; X86-NEXT: movl %esi, %ecx ; i686-NEXT: movl %esi, %ecx
; X86-NEXT: .LBB7_11: # %entry ; i686-NEXT: .LBB7_11: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movb $64, %cl ; i686-NEXT: movb $64, %cl
; X86-NEXT: subb %dl, %cl ; i686-NEXT: subb %dl, %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: shldl %cl, %ebx, %ebp ; i686-NEXT: shldl %cl, %ebx, %ebp
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ebx, %ebp ; i686-NEXT: movl %ebx, %ebp
; X86-NEXT: shll %cl, %ebp ; i686-NEXT: shll %cl, %ebp
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movb $64, %bl ; i686-NEXT: movb $64, %bl
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB7_13 ; i686-NEXT: je .LBB7_13
; X86-NEXT: # %bb.12: ; i686-NEXT: # %bb.12:
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: xorl %ebp, %ebp ; i686-NEXT: xorl %ebp, %ebp
; X86-NEXT: .LBB7_13: # %entry ; i686-NEXT: .LBB7_13: # %entry
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: shrdl %cl, %edi, %esi ; i686-NEXT: shrdl %cl, %edi, %esi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: jne .LBB7_15 ; i686-NEXT: jne .LBB7_15
; X86-NEXT: # %bb.14: # %entry ; i686-NEXT: # %bb.14: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_15: # %entry ; i686-NEXT: .LBB7_15: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: subb %al, %bl ; i686-NEXT: subb %al, %bl
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: shll %cl, %ebp ; i686-NEXT: shll %cl, %ebp
; X86-NEXT: testb $32, %bl ; i686-NEXT: testb $32, %bl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: jne .LBB7_17 ; i686-NEXT: jne .LBB7_17
; X86-NEXT: # %bb.16: # %entry ; i686-NEXT: # %bb.16: # %entry
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_17: # %entry ; i686-NEXT: .LBB7_17: # %entry
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: subl $64, %ecx ; i686-NEXT: subl $64, %ecx
; X86-NEXT: sbbl $0, %esi ; i686-NEXT: sbbl $0, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: sbbl $0, %esi ; i686-NEXT: sbbl $0, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: sbbl $0, %esi ; i686-NEXT: sbbl $0, %esi
; X86-NEXT: setae %bh ; i686-NEXT: setae %bh
; X86-NEXT: jb .LBB7_19 ; i686-NEXT: jb .LBB7_19
; X86-NEXT: # %bb.18: # %entry ; i686-NEXT: # %bb.18: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_19: # %entry ; i686-NEXT: .LBB7_19: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shrdl %cl, %edi, %esi ; i686-NEXT: shrdl %cl, %edi, %esi
; X86-NEXT: sarl %cl, %edi ; i686-NEXT: sarl %cl, %edi
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: je .LBB7_20 ; i686-NEXT: je .LBB7_20
; X86-NEXT: # %bb.21: # %entry ; i686-NEXT: # %bb.21: # %entry
; X86-NEXT: testb %bh, %bh ; i686-NEXT: testb %bh, %bh
; X86-NEXT: je .LBB7_22 ; i686-NEXT: je .LBB7_22
; X86-NEXT: .LBB7_23: # %entry ; i686-NEXT: .LBB7_23: # %entry
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: jne .LBB7_25 ; i686-NEXT: jne .LBB7_25
; X86-NEXT: .LBB7_24: # %entry ; i686-NEXT: .LBB7_24: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_25: # %entry ; i686-NEXT: .LBB7_25: # %entry
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shldl %cl, %esi, %edi ; i686-NEXT: shldl %cl, %esi, %edi
; X86-NEXT: testb $32, %bl ; i686-NEXT: testb $32, %bl
; X86-NEXT: jne .LBB7_27 ; i686-NEXT: jne .LBB7_27
; X86-NEXT: # %bb.26: # %entry ; i686-NEXT: # %bb.26: # %entry
; X86-NEXT: movl %edi, %ebp ; i686-NEXT: movl %edi, %ebp
; X86-NEXT: .LBB7_27: # %entry ; i686-NEXT: .LBB7_27: # %entry
; X86-NEXT: testb %bh, %bh ; i686-NEXT: testb %bh, %bh
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: jne .LBB7_29 ; i686-NEXT: jne .LBB7_29
; X86-NEXT: # %bb.28: ; i686-NEXT: # %bb.28:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: orl %ebp, %ebx ; i686-NEXT: orl %ebp, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_29: # %entry ; i686-NEXT: .LBB7_29: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: jne .LBB7_31 ; i686-NEXT: jne .LBB7_31
; X86-NEXT: # %bb.30: # %entry ; i686-NEXT: # %bb.30: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_31: # %entry ; i686-NEXT: .LBB7_31: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: shrdl %cl, %ebp, %ebx ; i686-NEXT: shrdl %cl, %ebp, %ebx
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: jne .LBB7_33 ; i686-NEXT: jne .LBB7_33
; X86-NEXT: # %bb.32: # %entry ; i686-NEXT: # %bb.32: # %entry
; X86-NEXT: movl %ebx, %esi ; i686-NEXT: movl %ebx, %esi
; X86-NEXT: .LBB7_33: # %entry ; i686-NEXT: .LBB7_33: # %entry
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X86-NEXT: je .LBB7_35 ; i686-NEXT: je .LBB7_35
; X86-NEXT: # %bb.34: ; i686-NEXT: # %bb.34:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: orl %ebx, %ecx ; i686-NEXT: orl %ebx, %ecx
; X86-NEXT: movl %ecx, %esi ; i686-NEXT: movl %ecx, %esi
; X86-NEXT: .LBB7_35: # %entry ; i686-NEXT: .LBB7_35: # %entry
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: je .LBB7_37 ; i686-NEXT: je .LBB7_37
; X86-NEXT: # %bb.36: ; i686-NEXT: # %bb.36:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_37: # %entry ; i686-NEXT: .LBB7_37: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: orl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: orl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: orl {{[0-9]+}}(%esp), %edx ; i686-NEXT: orl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl %ecx, %edx ; i686-NEXT: orl %ecx, %edx
; X86-NEXT: je .LBB7_39 ; i686-NEXT: je .LBB7_39
; X86-NEXT: # %bb.38: # %entry ; i686-NEXT: # %bb.38: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB7_39: # %entry ; i686-NEXT: .LBB7_39: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl {{[0-9]+}}(%esp), %edx ; i686-NEXT: orl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl {{[0-9]+}}(%esp), %eax ; i686-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl %edx, %eax ; i686-NEXT: orl %edx, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: je .LBB7_41 ; i686-NEXT: je .LBB7_41
; X86-NEXT: # %bb.40: # %entry ; i686-NEXT: # %bb.40: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: .LBB7_41: # %entry ; i686-NEXT: .LBB7_41: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 28(%ecx) ; i686-NEXT: movl %edx, 28(%ecx)
; X86-NEXT: movl %edi, 24(%ecx) ; i686-NEXT: movl %edi, 24(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 12(%ecx) ; i686-NEXT: movl %edx, 12(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 8(%ecx) ; i686-NEXT: movl %edx, 8(%ecx)
; X86-NEXT: movl %esi, 20(%ecx) ; i686-NEXT: movl %esi, 20(%ecx)
; X86-NEXT: movl %eax, 16(%ecx) ; i686-NEXT: movl %eax, 16(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, 4(%ecx) ; i686-NEXT: movl %eax, 4(%ecx)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, (%ecx) ; i686-NEXT: movl %eax, (%ecx)
; X86-NEXT: addl $80, %esp ; i686-NEXT: addl $80, %esp
; X86-NEXT: popl %esi ; i686-NEXT: popl %esi
; X86-NEXT: popl %edi ; i686-NEXT: popl %edi
; X86-NEXT: popl %ebx ; i686-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; i686-NEXT: popl %ebp
; X86-NEXT: retl ; i686-NEXT: retl
; X86-NEXT: .LBB7_20: # %entry ; i686-NEXT: .LBB7_20: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: testb %bh, %bh ; i686-NEXT: testb %bh, %bh
; X86-NEXT: jne .LBB7_23 ; i686-NEXT: jne .LBB7_23
; X86-NEXT: .LBB7_22: ; i686-NEXT: .LBB7_22:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: je .LBB7_24 ; i686-NEXT: je .LBB7_24
; X86-NEXT: jmp .LBB7_25 ; i686-NEXT: jmp .LBB7_25
; ;
; X64-LABEL: test_ashr_v2i128: ; x86_64-LABEL: test_ashr_v2i128:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: movq %rcx, %r11 ; x86_64-NEXT: movq %rcx, %r11
; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 ; x86_64-NEXT: movq {{[0-9]+}}(%rsp), %r10
; X64-NEXT: movb {{[0-9]+}}(%rsp), %r9b ; x86_64-NEXT: movb {{[0-9]+}}(%rsp), %r9b
; X64-NEXT: movl %r9d, %ecx ; x86_64-NEXT: movl %r9d, %ecx
; X64-NEXT: shrdq %cl, %r11, %rdx ; x86_64-NEXT: shrdq %cl, %r11, %rdx
; X64-NEXT: movl %r8d, %ecx ; x86_64-NEXT: movl %r8d, %ecx
; X64-NEXT: shrdq %cl, %rsi, %rdi ; x86_64-NEXT: shrdq %cl, %rsi, %rdi
; X64-NEXT: movq %rsi, %rax ; x86_64-NEXT: movq %rsi, %rax
; X64-NEXT: sarq %cl, %rax ; x86_64-NEXT: sarq %cl, %rax
; X64-NEXT: sarq $63, %rsi ; x86_64-NEXT: sarq $63, %rsi
; X64-NEXT: testb $64, %r8b ; x86_64-NEXT: testb $64, %r8b
; X64-NEXT: cmovneq %rax, %rdi ; x86_64-NEXT: cmovneq %rax, %rdi
; X64-NEXT: cmoveq %rax, %rsi ; x86_64-NEXT: cmoveq %rax, %rsi
; X64-NEXT: movq %r11, %rax ; x86_64-NEXT: movq %r11, %rax
; X64-NEXT: movl %r9d, %ecx ; x86_64-NEXT: movl %r9d, %ecx
; X64-NEXT: sarq %cl, %rax ; x86_64-NEXT: sarq %cl, %rax
; X64-NEXT: sarq $63, %r11 ; x86_64-NEXT: sarq $63, %r11
; X64-NEXT: testb $64, %r9b ; x86_64-NEXT: testb $64, %r9b
; X64-NEXT: cmovneq %rax, %rdx ; x86_64-NEXT: cmovneq %rax, %rdx
; X64-NEXT: cmoveq %rax, %r11 ; x86_64-NEXT: cmoveq %rax, %r11
; X64-NEXT: movq %r11, 24(%r10) ; x86_64-NEXT: movq %r11, 24(%r10)
; X64-NEXT: movq %rdx, 16(%r10) ; x86_64-NEXT: movq %rdx, 16(%r10)
; X64-NEXT: movq %rsi, 8(%r10) ; x86_64-NEXT: movq %rsi, 8(%r10)
; X64-NEXT: movq %rdi, (%r10) ; x86_64-NEXT: movq %rdi, (%r10)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = ashr <2 x i128> %x, %a %0 = ashr <2 x i128> %x, %a
store <2 x i128> %0, <2 x i128>* %r, align 16 store <2 x i128> %0, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_shl_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind { define void @test_shl_v2i128(<2 x i128> %x, <2 x i128> %a, <2 x i128>* nocapture %r) nounwind {
; X86-LABEL: test_shl_v2i128: ; i686-LABEL: test_shl_v2i128:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: pushl %ebp ; i686-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; i686-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; i686-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; i686-NEXT: pushl %esi
; X86-NEXT: subl $72, %esp ; i686-NEXT: subl $72, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: shll %cl, %ebp ; i686-NEXT: shll %cl, %ebp
; X86-NEXT: shll %cl, %esi ; i686-NEXT: shll %cl, %esi
; X86-NEXT: movl %edx, %eax ; i686-NEXT: movl %edx, %eax
; X86-NEXT: subl $64, %eax ; i686-NEXT: subl $64, %eax
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sbbl $0, %eax ; i686-NEXT: sbbl $0, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sbbl $0, %eax ; i686-NEXT: sbbl $0, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sbbl $0, %eax ; i686-NEXT: sbbl $0, %eax
; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; i686-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: testb $32, %bl ; i686-NEXT: testb $32, %bl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl $0, %eax ; i686-NEXT: movl $0, %eax
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB8_2 ; i686-NEXT: jne .LBB8_2
; X86-NEXT: # %bb.1: # %entry ; i686-NEXT: # %bb.1: # %entry
; X86-NEXT: movl %esi, %eax ; i686-NEXT: movl %esi, %eax
; X86-NEXT: movl %ebp, %ecx ; i686-NEXT: movl %ebp, %ecx
; X86-NEXT: .LBB8_2: # %entry ; i686-NEXT: .LBB8_2: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, %eax ; i686-NEXT: movl %edi, %eax
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: shldl %cl, %edi, %eax ; i686-NEXT: shldl %cl, %edi, %eax
; X86-NEXT: testb $32, %bl ; i686-NEXT: testb $32, %bl
; X86-NEXT: jne .LBB8_4 ; i686-NEXT: jne .LBB8_4
; X86-NEXT: # %bb.3: # %entry ; i686-NEXT: # %bb.3: # %entry
; X86-NEXT: movl %eax, %esi ; i686-NEXT: movl %eax, %esi
; X86-NEXT: .LBB8_4: # %entry ; i686-NEXT: .LBB8_4: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movb $64, %cl ; i686-NEXT: movb $64, %cl
; X86-NEXT: subb %bl, %cl ; i686-NEXT: subb %bl, %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, %esi ; i686-NEXT: movl %edi, %esi
; X86-NEXT: shrl %cl, %esi ; i686-NEXT: shrl %cl, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrdl %cl, %edi, %eax ; i686-NEXT: shrdl %cl, %edi, %eax
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: jne .LBB8_5 ; i686-NEXT: jne .LBB8_5
; X86-NEXT: # %bb.6: # %entry ; i686-NEXT: # %bb.6: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: jmp .LBB8_7 ; i686-NEXT: jmp .LBB8_7
; X86-NEXT: .LBB8_5: ; i686-NEXT: .LBB8_5:
; X86-NEXT: movl %esi, %eax ; i686-NEXT: movl %esi, %eax
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .LBB8_7: # %entry ; i686-NEXT: .LBB8_7: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shldl %cl, %esi, %edi ; i686-NEXT: shldl %cl, %esi, %edi
; X86-NEXT: testb $32, %bl ; i686-NEXT: testb $32, %bl
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: jne .LBB8_9 ; i686-NEXT: jne .LBB8_9
; X86-NEXT: # %bb.8: # %entry ; i686-NEXT: # %bb.8: # %entry
; X86-NEXT: movl %edi, %ebp ; i686-NEXT: movl %edi, %ebp
; X86-NEXT: .LBB8_9: # %entry ; i686-NEXT: .LBB8_9: # %entry
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, %ebp ; i686-NEXT: movl %ecx, %ebp
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: shll %cl, %ebp ; i686-NEXT: shll %cl, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shll %cl, %esi ; i686-NEXT: shll %cl, %esi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl $0, %edi ; i686-NEXT: movl $0, %edi
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: jne .LBB8_11 ; i686-NEXT: jne .LBB8_11
; X86-NEXT: # %bb.10: # %entry ; i686-NEXT: # %bb.10: # %entry
; X86-NEXT: movl %esi, %edi ; i686-NEXT: movl %esi, %edi
; X86-NEXT: movl %ebp, %ecx ; i686-NEXT: movl %ebp, %ecx
; X86-NEXT: .LBB8_11: # %entry ; i686-NEXT: .LBB8_11: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: shldl %cl, %ebx, %edi ; i686-NEXT: shldl %cl, %ebx, %edi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: jne .LBB8_13 ; i686-NEXT: jne .LBB8_13
; X86-NEXT: # %bb.12: # %entry ; i686-NEXT: # %bb.12: # %entry
; X86-NEXT: movl %edi, %ebp ; i686-NEXT: movl %edi, %ebp
; X86-NEXT: .LBB8_13: # %entry ; i686-NEXT: .LBB8_13: # %entry
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movb $64, %cl ; i686-NEXT: movb $64, %cl
; X86-NEXT: subb %dl, %cl ; i686-NEXT: subb %dl, %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: shrl %cl, %ebx ; i686-NEXT: shrl %cl, %ebx
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; i686-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl $0, %ecx ; i686-NEXT: movl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: jne .LBB8_15 ; i686-NEXT: jne .LBB8_15
; X86-NEXT: # %bb.14: # %entry ; i686-NEXT: # %bb.14: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: .LBB8_15: # %entry ; i686-NEXT: .LBB8_15: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl %edx, %ecx ; i686-NEXT: movl %edx, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: shldl %cl, %ebp, %edi ; i686-NEXT: shldl %cl, %ebp, %edi
; X86-NEXT: testb $32, %dl ; i686-NEXT: testb $32, %dl
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: jne .LBB8_17 ; i686-NEXT: jne .LBB8_17
; X86-NEXT: # %bb.16: # %entry ; i686-NEXT: # %bb.16: # %entry
; X86-NEXT: movl %edi, %esi ; i686-NEXT: movl %edi, %esi
; X86-NEXT: .LBB8_17: # %entry ; i686-NEXT: .LBB8_17: # %entry
; X86-NEXT: orl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: orl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl %ebx, %eax ; i686-NEXT: movl %ebx, %eax
; X86-NEXT: subl $64, %eax ; i686-NEXT: subl $64, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: movl %ebp, %ecx ; i686-NEXT: movl %ebp, %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: sbbl $0, %ecx ; i686-NEXT: sbbl $0, %ecx
; X86-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; i686-NEXT: setb {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill
; X86-NEXT: jb .LBB8_19 ; i686-NEXT: jb .LBB8_19
; X86-NEXT: # %bb.18: # %entry ; i686-NEXT: # %bb.18: # %entry
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .LBB8_19: # %entry ; i686-NEXT: .LBB8_19: # %entry
; X86-NEXT: jb .LBB8_21 ; i686-NEXT: jb .LBB8_21
; X86-NEXT: # %bb.20: # %entry ; i686-NEXT: # %bb.20: # %entry
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: .LBB8_21: # %entry ; i686-NEXT: .LBB8_21: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ebp, %ebx ; i686-NEXT: movl %ebp, %ebx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: shll %cl, %ebx ; i686-NEXT: shll %cl, %ebx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: shldl %cl, %ebp, %edi ; i686-NEXT: shldl %cl, %ebp, %edi
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: movl %ebx, %ecx ; i686-NEXT: movl %ebx, %ecx
; X86-NEXT: jne .LBB8_23 ; i686-NEXT: jne .LBB8_23
; X86-NEXT: # %bb.22: # %entry ; i686-NEXT: # %bb.22: # %entry
; X86-NEXT: movl %edi, %ecx ; i686-NEXT: movl %edi, %ecx
; X86-NEXT: .LBB8_23: # %entry ; i686-NEXT: .LBB8_23: # %entry
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: shll %cl, %edi ; i686-NEXT: shll %cl, %edi
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: movl $0, %edi ; i686-NEXT: movl $0, %edi
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload
; X86-NEXT: jne .LBB8_25 ; i686-NEXT: jne .LBB8_25
; X86-NEXT: # %bb.24: # %entry ; i686-NEXT: # %bb.24: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: .LBB8_25: # %entry ; i686-NEXT: .LBB8_25: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: jne .LBB8_27 ; i686-NEXT: jne .LBB8_27
; X86-NEXT: # %bb.26: # %entry ; i686-NEXT: # %bb.26: # %entry
; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB8_27: # %entry ; i686-NEXT: .LBB8_27: # %entry
; X86-NEXT: movl %eax, %ecx ; i686-NEXT: movl %eax, %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: shldl %cl, %edi, %esi ; i686-NEXT: shldl %cl, %edi, %esi
; X86-NEXT: testb $32, %al ; i686-NEXT: testb $32, %al
; X86-NEXT: jne .LBB8_29 ; i686-NEXT: jne .LBB8_29
; X86-NEXT: # %bb.28: # %entry ; i686-NEXT: # %bb.28: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB8_29: # %entry ; i686-NEXT: .LBB8_29: # %entry
; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; i686-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload ; i686-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: jne .LBB8_30 ; i686-NEXT: jne .LBB8_30
; X86-NEXT: # %bb.31: # %entry ; i686-NEXT: # %bb.31: # %entry
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: je .LBB8_32 ; i686-NEXT: je .LBB8_32
; X86-NEXT: .LBB8_33: # %entry ; i686-NEXT: .LBB8_33: # %entry
; X86-NEXT: testb $32, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: testb $32, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: jne .LBB8_35 ; i686-NEXT: jne .LBB8_35
; X86-NEXT: .LBB8_34: # %entry ; i686-NEXT: .LBB8_34: # %entry
; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB8_35: # %entry ; i686-NEXT: .LBB8_35: # %entry
; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload ; i686-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Reload
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: shrdl %cl, %ebx, %esi ; i686-NEXT: shrdl %cl, %ebx, %esi
; X86-NEXT: testb $32, %cl ; i686-NEXT: testb $32, %cl
; X86-NEXT: jne .LBB8_37 ; i686-NEXT: jne .LBB8_37
; X86-NEXT: # %bb.36: # %entry ; i686-NEXT: # %bb.36: # %entry
; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB8_37: # %entry ; i686-NEXT: .LBB8_37: # %entry
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: jne .LBB8_38 ; i686-NEXT: jne .LBB8_38
; X86-NEXT: # %bb.39: # %entry ; i686-NEXT: # %bb.39: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: jne .LBB8_41 ; i686-NEXT: jne .LBB8_41
; X86-NEXT: jmp .LBB8_42 ; i686-NEXT: jmp .LBB8_42
; X86-NEXT: .LBB8_30: ; i686-NEXT: .LBB8_30:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: orl %ebp, %ecx ; i686-NEXT: orl %ebp, %ecx
; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: jne .LBB8_33 ; i686-NEXT: jne .LBB8_33
; X86-NEXT: .LBB8_32: # %entry ; i686-NEXT: .LBB8_32: # %entry
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; i686-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-NEXT: testb $32, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; i686-NEXT: testb $32, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
; X86-NEXT: je .LBB8_34 ; i686-NEXT: je .LBB8_34
; X86-NEXT: jmp .LBB8_35 ; i686-NEXT: jmp .LBB8_35
; X86-NEXT: .LBB8_38: ; i686-NEXT: .LBB8_38:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: testb %al, %al ; i686-NEXT: testb %al, %al
; X86-NEXT: je .LBB8_42 ; i686-NEXT: je .LBB8_42
; X86-NEXT: .LBB8_41: ; i686-NEXT: .LBB8_41:
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; i686-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB8_42: # %entry ; i686-NEXT: .LBB8_42: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl {{[0-9]+}}(%esp), %eax ; i686-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: orl {{[0-9]+}}(%esp), %edx ; i686-NEXT: orl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl %eax, %edx ; i686-NEXT: orl %eax, %edx
; X86-NEXT: je .LBB8_44 ; i686-NEXT: je .LBB8_44
; X86-NEXT: # %bb.43: # %entry ; i686-NEXT: # %bb.43: # %entry
; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; i686-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-NEXT: .LBB8_44: # %entry ; i686-NEXT: .LBB8_44: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl {{[0-9]+}}(%esp), %edx ; i686-NEXT: orl {{[0-9]+}}(%esp), %edx
; X86-NEXT: orl {{[0-9]+}}(%esp), %ebx ; i686-NEXT: orl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: orl %edx, %ebx ; i686-NEXT: orl %edx, %ebx
; X86-NEXT: je .LBB8_46 ; i686-NEXT: je .LBB8_46
; X86-NEXT: # %bb.45: # %entry ; i686-NEXT: # %bb.45: # %entry
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; X86-NEXT: .LBB8_46: # %entry ; i686-NEXT: .LBB8_46: # %entry
; X86-NEXT: movl %esi, 20(%eax) ; i686-NEXT: movl %esi, 20(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 16(%eax) ; i686-NEXT: movl %edx, 16(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, 4(%eax) ; i686-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; X86-NEXT: movl %edx, (%eax) ; i686-NEXT: movl %edx, (%eax)
; X86-NEXT: movl %edi, 28(%eax) ; i686-NEXT: movl %edi, 28(%eax)
; X86-NEXT: movl %ecx, 24(%eax) ; i686-NEXT: movl %ecx, 24(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, 12(%eax) ; i686-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; i686-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; X86-NEXT: movl %ecx, 8(%eax) ; i686-NEXT: movl %ecx, 8(%eax)
; X86-NEXT: addl $72, %esp ; i686-NEXT: addl $72, %esp
; X86-NEXT: popl %esi ; i686-NEXT: popl %esi
; X86-NEXT: popl %edi ; i686-NEXT: popl %edi
; X86-NEXT: popl %ebx ; i686-NEXT: popl %ebx
; X86-NEXT: popl %ebp ; i686-NEXT: popl %ebp
; X86-NEXT: retl ; i686-NEXT: retl
; ;
; X64-LABEL: test_shl_v2i128: ; x86_64-LABEL: test_shl_v2i128:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: movq %rcx, %rax ; x86_64-NEXT: movq %rcx, %rax
; X64-NEXT: movq {{[0-9]+}}(%rsp), %r10 ; x86_64-NEXT: movq {{[0-9]+}}(%rsp), %r10
; X64-NEXT: movb {{[0-9]+}}(%rsp), %r9b ; x86_64-NEXT: movb {{[0-9]+}}(%rsp), %r9b
; X64-NEXT: movl %r9d, %ecx ; x86_64-NEXT: movl %r9d, %ecx
; X64-NEXT: shldq %cl, %rdx, %rax ; x86_64-NEXT: shldq %cl, %rdx, %rax
; X64-NEXT: movl %r8d, %ecx ; x86_64-NEXT: movl %r8d, %ecx
; X64-NEXT: shldq %cl, %rdi, %rsi ; x86_64-NEXT: shldq %cl, %rdi, %rsi
; X64-NEXT: shlq %cl, %rdi ; x86_64-NEXT: shlq %cl, %rdi
; X64-NEXT: xorl %r11d, %r11d ; x86_64-NEXT: xorl %r11d, %r11d
; X64-NEXT: testb $64, %r8b ; x86_64-NEXT: testb $64, %r8b
; X64-NEXT: cmovneq %rdi, %rsi ; x86_64-NEXT: cmovneq %rdi, %rsi
; X64-NEXT: cmovneq %r11, %rdi ; x86_64-NEXT: cmovneq %r11, %rdi
; X64-NEXT: movl %r9d, %ecx ; x86_64-NEXT: movl %r9d, %ecx
; X64-NEXT: shlq %cl, %rdx ; x86_64-NEXT: shlq %cl, %rdx
; X64-NEXT: testb $64, %r9b ; x86_64-NEXT: testb $64, %r9b
; X64-NEXT: cmovneq %rdx, %rax ; x86_64-NEXT: cmovneq %rdx, %rax
; X64-NEXT: cmovneq %r11, %rdx ; x86_64-NEXT: cmovneq %r11, %rdx
; X64-NEXT: movq %rax, 24(%r10) ; x86_64-NEXT: movq %rax, 24(%r10)
; X64-NEXT: movq %rdx, 16(%r10) ; x86_64-NEXT: movq %rdx, 16(%r10)
; X64-NEXT: movq %rsi, 8(%r10) ; x86_64-NEXT: movq %rsi, 8(%r10)
; X64-NEXT: movq %rdi, (%r10) ; x86_64-NEXT: movq %rdi, (%r10)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = shl <2 x i128> %x, %a %0 = shl <2 x i128> %x, %a
store <2 x i128> %0, <2 x i128>* %r, align 16 store <2 x i128> %0, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_lshr_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { define void @test_lshr_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind {
; CHECK-LABEL: test_lshr_v2i128_outofrange: ; ALL-LABEL: test_lshr_v2i128_outofrange:
; CHECK: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; CHECK-NEXT: ret{{[l|q]}} ; ALL-NEXT: ret{{[l|q]}}
entry: entry:
%0 = lshr <2 x i128> %x, <i128 -1, i128 -1> %0 = lshr <2 x i128> %x, <i128 -1, i128 -1>
store <2 x i128> %0, <2 x i128>* %r, align 16 store <2 x i128> %0, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_ashr_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { define void @test_ashr_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind {
; CHECK-LABEL: test_ashr_v2i128_outofrange: ; ALL-LABEL: test_ashr_v2i128_outofrange:
; CHECK: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; CHECK-NEXT: ret{{[l|q]}} ; ALL-NEXT: ret{{[l|q]}}
entry: entry:
%0 = ashr <2 x i128> %x, <i128 -1, i128 -1> %0 = ashr <2 x i128> %x, <i128 -1, i128 -1>
store <2 x i128> %0, <2 x i128>* %r, align 16 store <2 x i128> %0, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_shl_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { define void @test_shl_v2i128_outofrange(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind {
; CHECK-LABEL: test_shl_v2i128_outofrange: ; ALL-LABEL: test_shl_v2i128_outofrange:
; CHECK: # %bb.0: # %entry ; ALL: # %bb.0: # %entry
; CHECK-NEXT: ret{{[l|q]}} ; ALL-NEXT: ret{{[l|q]}}
entry: entry:
%0 = shl <2 x i128> %x, <i128 -1, i128 -1> %0 = shl <2 x i128> %x, <i128 -1, i128 -1>
store <2 x i128> %0, <2 x i128>* %r, align 16 store <2 x i128> %0, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_lshr_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { define void @test_lshr_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind {
; X86-LABEL: test_lshr_v2i128_outofrange_sum: ; i686-LABEL: test_lshr_v2i128_outofrange_sum:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl $0, 28(%eax) ; i686-NEXT: movl $0, 28(%eax)
; X86-NEXT: movl $0, 24(%eax) ; i686-NEXT: movl $0, 24(%eax)
; X86-NEXT: movl $0, 20(%eax) ; i686-NEXT: movl $0, 20(%eax)
; X86-NEXT: movl $0, 16(%eax) ; i686-NEXT: movl $0, 16(%eax)
; X86-NEXT: movl $0, 12(%eax) ; i686-NEXT: movl $0, 12(%eax)
; X86-NEXT: movl $0, 8(%eax) ; i686-NEXT: movl $0, 8(%eax)
; X86-NEXT: movl $0, 4(%eax) ; i686-NEXT: movl $0, 4(%eax)
; X86-NEXT: movl $0, (%eax) ; i686-NEXT: movl $0, (%eax)
; X86-NEXT: retl ; i686-NEXT: retl
; ;
; X64-LABEL: test_lshr_v2i128_outofrange_sum: ; x86_64-LABEL: test_lshr_v2i128_outofrange_sum:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: xorps %xmm0, %xmm0 ; x86_64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 16(%r8) ; x86_64-NEXT: movaps %xmm0, 16(%r8)
; X64-NEXT: movaps %xmm0, (%r8) ; x86_64-NEXT: movaps %xmm0, (%r8)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = lshr <2 x i128> %x, <i128 -1, i128 -1> %0 = lshr <2 x i128> %x, <i128 -1, i128 -1>
%1 = lshr <2 x i128> %0, <i128 1, i128 1> %1 = lshr <2 x i128> %0, <i128 1, i128 1>
store <2 x i128> %1, <2 x i128>* %r, align 16 store <2 x i128> %1, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_ashr_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { define void @test_ashr_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind {
; X86-LABEL: test_ashr_v2i128_outofrange_sum: ; i686-LABEL: test_ashr_v2i128_outofrange_sum:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl $0, 28(%eax) ; i686-NEXT: movl $0, 28(%eax)
; X86-NEXT: movl $0, 24(%eax) ; i686-NEXT: movl $0, 24(%eax)
; X86-NEXT: movl $0, 20(%eax) ; i686-NEXT: movl $0, 20(%eax)
; X86-NEXT: movl $0, 16(%eax) ; i686-NEXT: movl $0, 16(%eax)
; X86-NEXT: movl $0, 12(%eax) ; i686-NEXT: movl $0, 12(%eax)
; X86-NEXT: movl $0, 8(%eax) ; i686-NEXT: movl $0, 8(%eax)
; X86-NEXT: movl $0, 4(%eax) ; i686-NEXT: movl $0, 4(%eax)
; X86-NEXT: movl $0, (%eax) ; i686-NEXT: movl $0, (%eax)
; X86-NEXT: retl ; i686-NEXT: retl
; ;
; X64-LABEL: test_ashr_v2i128_outofrange_sum: ; x86_64-LABEL: test_ashr_v2i128_outofrange_sum:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: xorps %xmm0, %xmm0 ; x86_64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 16(%r8) ; x86_64-NEXT: movaps %xmm0, 16(%r8)
; X64-NEXT: movaps %xmm0, (%r8) ; x86_64-NEXT: movaps %xmm0, (%r8)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = ashr <2 x i128> %x, <i128 -1, i128 -1> %0 = ashr <2 x i128> %x, <i128 -1, i128 -1>
%1 = ashr <2 x i128> %0, <i128 1, i128 1> %1 = ashr <2 x i128> %0, <i128 1, i128 1>
store <2 x i128> %1, <2 x i128>* %r, align 16 store <2 x i128> %1, <2 x i128>* %r, align 16
ret void ret void
} }
define void @test_shl_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind { define void @test_shl_v2i128_outofrange_sum(<2 x i128> %x, <2 x i128>* nocapture %r) nounwind {
; X86-LABEL: test_shl_v2i128_outofrange_sum: ; i686-LABEL: test_shl_v2i128_outofrange_sum:
; X86: # %bb.0: # %entry ; i686: # %bb.0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl $0, 28(%eax) ; i686-NEXT: movl $0, 28(%eax)
; X86-NEXT: movl $0, 24(%eax) ; i686-NEXT: movl $0, 24(%eax)
; X86-NEXT: movl $0, 20(%eax) ; i686-NEXT: movl $0, 20(%eax)
; X86-NEXT: movl $0, 16(%eax) ; i686-NEXT: movl $0, 16(%eax)
; X86-NEXT: movl $0, 12(%eax) ; i686-NEXT: movl $0, 12(%eax)
; X86-NEXT: movl $0, 8(%eax) ; i686-NEXT: movl $0, 8(%eax)
; X86-NEXT: movl $0, 4(%eax) ; i686-NEXT: movl $0, 4(%eax)
; X86-NEXT: movl $0, (%eax) ; i686-NEXT: movl $0, (%eax)
; X86-NEXT: retl ; i686-NEXT: retl
; ;
; X64-LABEL: test_shl_v2i128_outofrange_sum: ; x86_64-LABEL: test_shl_v2i128_outofrange_sum:
; X64: # %bb.0: # %entry ; x86_64: # %bb.0: # %entry
; X64-NEXT: xorps %xmm0, %xmm0 ; x86_64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 16(%r8) ; x86_64-NEXT: movaps %xmm0, 16(%r8)
; X64-NEXT: movaps %xmm0, (%r8) ; x86_64-NEXT: movaps %xmm0, (%r8)
; X64-NEXT: retq ; x86_64-NEXT: retq
entry: entry:
%0 = shl <2 x i128> %x, <i128 -1, i128 -1> %0 = shl <2 x i128> %x, <i128 -1, i128 -1>
%1 = shl <2 x i128> %0, <i128 1, i128 1> %1 = shl <2 x i128> %0, <i128 1, i128 1>
store <2 x i128> %1, <2 x i128>* %r, align 16 store <2 x i128> %1, <2 x i128>* %r, align 16
ret void ret void
} }
; ;
; Combines ; Combines
; ;
define <2 x i256> @shl_sext_shl_outofrange(<2 x i128> %a0) { define <2 x i256> @shl_sext_shl_outofrange(<2 x i128> %a0) {
; X86-LABEL: shl_sext_shl_outofrange: ; i686-LABEL: shl_sext_shl_outofrange:
; X86: # %bb.0: ; i686: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl $0, 60(%eax) ; i686-NEXT: movl $0, 60(%eax)
; X86-NEXT: movl $0, 56(%eax) ; i686-NEXT: movl $0, 56(%eax)
; X86-NEXT: movl $0, 52(%eax) ; i686-NEXT: movl $0, 52(%eax)
; X86-NEXT: movl $0, 48(%eax) ; i686-NEXT: movl $0, 48(%eax)
; X86-NEXT: movl $0, 44(%eax) ; i686-NEXT: movl $0, 44(%eax)
; X86-NEXT: movl $0, 40(%eax) ; i686-NEXT: movl $0, 40(%eax)
; X86-NEXT: movl $0, 36(%eax) ; i686-NEXT: movl $0, 36(%eax)
; X86-NEXT: movl $0, 32(%eax) ; i686-NEXT: movl $0, 32(%eax)
; X86-NEXT: movl $0, 28(%eax) ; i686-NEXT: movl $0, 28(%eax)
; X86-NEXT: movl $0, 24(%eax) ; i686-NEXT: movl $0, 24(%eax)
; X86-NEXT: movl $0, 20(%eax) ; i686-NEXT: movl $0, 20(%eax)
; X86-NEXT: movl $0, 16(%eax) ; i686-NEXT: movl $0, 16(%eax)
; X86-NEXT: movl $0, 12(%eax) ; i686-NEXT: movl $0, 12(%eax)
; X86-NEXT: movl $0, 8(%eax) ; i686-NEXT: movl $0, 8(%eax)
; X86-NEXT: movl $0, 4(%eax) ; i686-NEXT: movl $0, 4(%eax)
; X86-NEXT: movl $0, (%eax) ; i686-NEXT: movl $0, (%eax)
; X86-NEXT: retl $4 ; i686-NEXT: retl $4
; ;
; X64-LABEL: shl_sext_shl_outofrange: ; x86_64-LABEL: shl_sext_shl_outofrange:
; X64: # %bb.0: ; x86_64: # %bb.0:
; X64-NEXT: movq %rdi, %rax ; x86_64-NEXT: movq %rdi, %rax
; X64-NEXT: xorps %xmm0, %xmm0 ; x86_64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 48(%rdi) ; x86_64-NEXT: movaps %xmm0, 48(%rdi)
; X64-NEXT: movaps %xmm0, 32(%rdi) ; x86_64-NEXT: movaps %xmm0, 32(%rdi)
; X64-NEXT: movaps %xmm0, 16(%rdi) ; x86_64-NEXT: movaps %xmm0, 16(%rdi)
; X64-NEXT: movaps %xmm0, (%rdi) ; x86_64-NEXT: movaps %xmm0, (%rdi)
; X64-NEXT: retq ; x86_64-NEXT: retq
%1 = shl <2 x i128> %a0, <i128 -1, i128 -1> %1 = shl <2 x i128> %a0, <i128 -1, i128 -1>
%2 = sext <2 x i128> %1 to <2 x i256> %2 = sext <2 x i128> %1 to <2 x i256>
%3 = shl <2 x i256> %2, <i256 128, i256 128> %3 = shl <2 x i256> %2, <i256 128, i256 128>
ret <2 x i256> %3 ret <2 x i256> %3
} }
define <2 x i256> @shl_zext_shl_outofrange(<2 x i128> %a0) { define <2 x i256> @shl_zext_shl_outofrange(<2 x i128> %a0) {
; X86-LABEL: shl_zext_shl_outofrange: ; i686-LABEL: shl_zext_shl_outofrange:
; X86: # %bb.0: ; i686: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl $0, 60(%eax) ; i686-NEXT: movl $0, 60(%eax)
; X86-NEXT: movl $0, 56(%eax) ; i686-NEXT: movl $0, 56(%eax)
; X86-NEXT: movl $0, 52(%eax) ; i686-NEXT: movl $0, 52(%eax)
; X86-NEXT: movl $0, 48(%eax) ; i686-NEXT: movl $0, 48(%eax)
; X86-NEXT: movl $0, 44(%eax) ; i686-NEXT: movl $0, 44(%eax)
; X86-NEXT: movl $0, 40(%eax) ; i686-NEXT: movl $0, 40(%eax)
; X86-NEXT: movl $0, 36(%eax) ; i686-NEXT: movl $0, 36(%eax)
; X86-NEXT: movl $0, 32(%eax) ; i686-NEXT: movl $0, 32(%eax)
; X86-NEXT: movl $0, 28(%eax) ; i686-NEXT: movl $0, 28(%eax)
; X86-NEXT: movl $0, 24(%eax) ; i686-NEXT: movl $0, 24(%eax)
; X86-NEXT: movl $0, 20(%eax) ; i686-NEXT: movl $0, 20(%eax)
; X86-NEXT: movl $0, 16(%eax) ; i686-NEXT: movl $0, 16(%eax)
; X86-NEXT: movl $0, 12(%eax) ; i686-NEXT: movl $0, 12(%eax)
; X86-NEXT: movl $0, 8(%eax) ; i686-NEXT: movl $0, 8(%eax)
; X86-NEXT: movl $0, 4(%eax) ; i686-NEXT: movl $0, 4(%eax)
; X86-NEXT: movl $0, (%eax) ; i686-NEXT: movl $0, (%eax)
; X86-NEXT: retl $4 ; i686-NEXT: retl $4
; ;
; X64-LABEL: shl_zext_shl_outofrange: ; x86_64-LABEL: shl_zext_shl_outofrange:
; X64: # %bb.0: ; x86_64: # %bb.0:
; X64-NEXT: movq %rdi, %rax ; x86_64-NEXT: movq %rdi, %rax
; X64-NEXT: xorps %xmm0, %xmm0 ; x86_64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 48(%rdi) ; x86_64-NEXT: movaps %xmm0, 48(%rdi)
; X64-NEXT: movaps %xmm0, 32(%rdi) ; x86_64-NEXT: movaps %xmm0, 32(%rdi)
; X64-NEXT: movaps %xmm0, 16(%rdi) ; x86_64-NEXT: movaps %xmm0, 16(%rdi)
; X64-NEXT: movaps %xmm0, (%rdi) ; x86_64-NEXT: movaps %xmm0, (%rdi)
; X64-NEXT: retq ; x86_64-NEXT: retq
%1 = shl <2 x i128> %a0, <i128 -1, i128 -1> %1 = shl <2 x i128> %a0, <i128 -1, i128 -1>
%2 = zext <2 x i128> %1 to <2 x i256> %2 = zext <2 x i128> %1 to <2 x i256>
%3 = shl <2 x i256> %2, <i256 128, i256 128> %3 = shl <2 x i256> %2, <i256 128, i256 128>
ret <2 x i256> %3 ret <2 x i256> %3
} }
define <2 x i256> @shl_zext_lshr_outofrange(<2 x i128> %a0) { define <2 x i256> @shl_zext_lshr_outofrange(<2 x i128> %a0) {
; X86-LABEL: shl_zext_lshr_outofrange: ; i686-LABEL: shl_zext_lshr_outofrange:
; X86: # %bb.0: ; i686: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl $0, 60(%eax) ; i686-NEXT: movl $0, 60(%eax)
; X86-NEXT: movl $0, 56(%eax) ; i686-NEXT: movl $0, 56(%eax)
; X86-NEXT: movl $0, 52(%eax) ; i686-NEXT: movl $0, 52(%eax)
; X86-NEXT: movl $0, 48(%eax) ; i686-NEXT: movl $0, 48(%eax)
; X86-NEXT: movl $0, 44(%eax) ; i686-NEXT: movl $0, 44(%eax)
; X86-NEXT: movl $0, 40(%eax) ; i686-NEXT: movl $0, 40(%eax)
; X86-NEXT: movl $0, 36(%eax) ; i686-NEXT: movl $0, 36(%eax)
; X86-NEXT: movl $0, 32(%eax) ; i686-NEXT: movl $0, 32(%eax)
; X86-NEXT: movl $0, 28(%eax) ; i686-NEXT: movl $0, 28(%eax)
; X86-NEXT: movl $0, 24(%eax) ; i686-NEXT: movl $0, 24(%eax)
; X86-NEXT: movl $0, 20(%eax) ; i686-NEXT: movl $0, 20(%eax)
; X86-NEXT: movl $0, 16(%eax) ; i686-NEXT: movl $0, 16(%eax)
; X86-NEXT: movl $0, 12(%eax) ; i686-NEXT: movl $0, 12(%eax)
; X86-NEXT: movl $0, 8(%eax) ; i686-NEXT: movl $0, 8(%eax)
; X86-NEXT: movl $0, 4(%eax) ; i686-NEXT: movl $0, 4(%eax)
; X86-NEXT: movl $0, (%eax) ; i686-NEXT: movl $0, (%eax)
; X86-NEXT: retl $4 ; i686-NEXT: retl $4
; ;
; X64-LABEL: shl_zext_lshr_outofrange: ; x86_64-LABEL: shl_zext_lshr_outofrange:
; X64: # %bb.0: ; x86_64: # %bb.0:
; X64-NEXT: movq %rdi, %rax ; x86_64-NEXT: movq %rdi, %rax
; X64-NEXT: xorps %xmm0, %xmm0 ; x86_64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: movaps %xmm0, 48(%rdi) ; x86_64-NEXT: movaps %xmm0, 48(%rdi)
; X64-NEXT: movaps %xmm0, 32(%rdi) ; x86_64-NEXT: movaps %xmm0, 32(%rdi)
; X64-NEXT: movaps %xmm0, 16(%rdi) ; x86_64-NEXT: movaps %xmm0, 16(%rdi)
; X64-NEXT: movaps %xmm0, (%rdi) ; x86_64-NEXT: movaps %xmm0, (%rdi)
; X64-NEXT: retq ; x86_64-NEXT: retq
%1 = lshr <2 x i128> %a0, <i128 -1, i128 -1> %1 = lshr <2 x i128> %a0, <i128 -1, i128 -1>
%2 = zext <2 x i128> %1 to <2 x i256> %2 = zext <2 x i128> %1 to <2 x i256>
%3 = shl <2 x i256> %2, <i256 128, i256 128> %3 = shl <2 x i256> %2, <i256 128, i256 128>
ret <2 x i256> %3 ret <2 x i256> %3
} }
define i128 @lshr_shl_mask(i128 %a0) { define i128 @lshr_shl_mask(i128 %a0) {
; X86-LABEL: lshr_shl_mask: ; i686-LABEL: lshr_shl_mask:
; X86: # %bb.0: ; i686: # %bb.0:
; X86-NEXT: pushl %edi ; i686-NEXT: pushl %edi
; X86-NEXT: .cfi_def_cfa_offset 8 ; i686-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: pushl %esi ; i686-NEXT: pushl %esi
; X86-NEXT: .cfi_def_cfa_offset 12 ; i686-NEXT: .cfi_def_cfa_offset 12
; X86-NEXT: .cfi_offset %esi, -12 ; i686-NEXT: .cfi_offset %esi, -12
; X86-NEXT: .cfi_offset %edi, -8 ; i686-NEXT: .cfi_offset %edi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; i686-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; i686-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; i686-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; i686-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl $2147483647, %edi # imm = 0x7FFFFFFF ; i686-NEXT: movl $2147483647, %edi # imm = 0x7FFFFFFF
; X86-NEXT: andl {{[0-9]+}}(%esp), %edi ; i686-NEXT: andl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%eax) ; i686-NEXT: movl %edi, 12(%eax)
; X86-NEXT: movl %esi, 8(%eax) ; i686-NEXT: movl %esi, 8(%eax)
; X86-NEXT: movl %edx, 4(%eax) ; i686-NEXT: movl %edx, 4(%eax)
; X86-NEXT: movl %ecx, (%eax) ; i686-NEXT: movl %ecx, (%eax)
; X86-NEXT: popl %esi ; i686-NEXT: popl %esi
; X86-NEXT: .cfi_def_cfa_offset 8 ; i686-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: popl %edi ; i686-NEXT: popl %edi
; X86-NEXT: .cfi_def_cfa_offset 4 ; i686-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl $4 ; i686-NEXT: retl $4
; ;
; X64-LABEL: lshr_shl_mask: ; x86_64-LABEL: lshr_shl_mask:
; X64: # %bb.0: ; x86_64: # %bb.0:
; X64-NEXT: movq %rdi, %rax ; x86_64-NEXT: movq %rdi, %rax
; X64-NEXT: movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF ; x86_64-NEXT: movabsq $9223372036854775807, %rdx # imm = 0x7FFFFFFFFFFFFFFF
; X64-NEXT: andq %rsi, %rdx ; x86_64-NEXT: andq %rsi, %rdx
; X64-NEXT: retq ; x86_64-NEXT: retq
%1 = shl i128 %a0, 1 %1 = shl i128 %a0, 1
%2 = lshr i128 %1, 1 %2 = lshr i128 %1, 1
ret i128 %2 ret i128 %2
} }

llvm/test/CodeGen/X86/shrink-fp-const1.ll

; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | not grep cvtss2sd ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s
; PR1264 ; PR1264
define double @foo(double %x) { define double @foo(double %x) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: mulsd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq
%y = fmul double %x, 5.000000e-01 %y = fmul double %x, 5.000000e-01
ret double %y ret double %y
} }

llvm/test/CodeGen/X86/shrink-fp-const2.ll

; RUN: llc < %s -mtriple=i686-- | grep flds ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; This should be a flds, not fldt. ; This should be a flds, not fldt.
define x86_fp80 @test2() nounwind { define x86_fp80 @test2() nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: flds {{\.LCPI.*}}
; CHECK-NEXT: retl
entry: entry:
ret x86_fp80 0xK3FFFC000000000000000 ret x86_fp80 0xK3FFFC000000000000000
} }

llvm/test/CodeGen/X86/split-eh-lpad-edges.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep jmp ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; rdar://6647639 ; rdar://6647639
%struct.FetchPlanHeader = type { i8*, i8*, i32, i8*, i8*, i8*, i8*, i8*, %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)*, %struct.__attributeDescriptionFlags } %struct.FetchPlanHeader = type { i8*, i8*, i32, i8*, i8*, i8*, i8*, i8*, %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...)*, %struct.__attributeDescriptionFlags }
%struct.NSArray = type { %struct.NSObject } %struct.NSArray = type { %struct.NSObject }
%struct.NSAutoreleasePool = type { %struct.NSObject, i8*, i8*, i8*, i8* } %struct.NSAutoreleasePool = type { %struct.NSObject, i8*, i8*, i8*, i8* }
%struct.NSObject = type { %struct.NSObject* } %struct.NSObject = type { %struct.NSObject* }
%struct.__attributeDescriptionFlags = type <{ i32 }> %struct.__attributeDescriptionFlags = type <{ i32 }>
%struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* } %struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* }
%struct.objc_selector = type opaque %struct.objc_selector = type opaque
@"\01l_objc_msgSend_fixup_alloc" = external global %struct._message_ref_t, align 16 ; <%struct._message_ref_t*> [#uses=2] @"\01l_objc_msgSend_fixup_alloc" = external global %struct._message_ref_t, align 16 ; <%struct._message_ref_t*> [#uses=2]
define %struct.NSArray* @newFetchedRowsForFetchPlan_MT(%struct.FetchPlanHeader* %fetchPlan, %struct.objc_selector* %selectionMethod, %struct.NSObject* %selectionParameter) ssp personality i32 (...)* @__gxx_personality_v0 { define %struct.NSArray* @newFetchedRowsForFetchPlan_MT(%struct.FetchPlanHeader* %fetchPlan, %struct.objc_selector* %selectionMethod, %struct.NSObject* %selectionParameter) ssp personality i32 (...)* @__gxx_personality_v0 {
; CHECK-LABEL: newFetchedRowsForFetchPlan_MT:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: Ltmp0:
; CHECK-NEXT: movq l_objc_msgSend_fixup_alloc@{{.*}}(%rip), %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: callq *%rax
; CHECK-NEXT: Ltmp1:
; CHECK-NEXT: ## %bb.1: ## %invcont
; CHECK-NEXT: Ltmp2:
; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq _objc_msgSend
; CHECK-NEXT: Ltmp3:
; CHECK-NEXT: ## %bb.2: ## %invcont26
; CHECK-NEXT: Ltmp4:
; CHECK-NEXT: movq l_objc_msgSend_fixup_alloc@{{.*}}(%rip), %rsi
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: callq *%rax
; CHECK-NEXT: Ltmp5:
; CHECK-NEXT: ## %bb.3: ## %invcont27
; CHECK-NEXT: ud2
; CHECK-NEXT: LBB0_4: ## %lpad
; CHECK-NEXT: Ltmp6:
; CHECK-NEXT: ud2
; CHECK-NEXT: Lfunc_end0:
entry: entry:
%0 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc") %0 = invoke %struct.NSObject* null(%struct.NSObject* null, %struct._message_ref_t* @"\01l_objc_msgSend_fixup_alloc")
to label %invcont unwind label %lpad ; <%struct.NSObject*> [#uses=1] to label %invcont unwind label %lpad ; <%struct.NSObject*> [#uses=1]
invcont: ; preds = %entry invcont: ; preds = %entry
%1 = invoke %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...) @objc_msgSend(%struct.NSObject* %0, %struct.objc_selector* null) %1 = invoke %struct.NSObject* (%struct.NSObject*, %struct.objc_selector*, ...) @objc_msgSend(%struct.NSObject* %0, %struct.objc_selector* null)
to label %invcont26 unwind label %lpad ; <%struct.NSObject*> [#uses=0] to label %invcont26 unwind label %lpad ; <%struct.NSObject*> [#uses=0]
Show All 17 Lines

llvm/test/CodeGen/X86/split-vector-bitcast.ll

; RUN: llc < %s -mtriple=i686-- -mattr=-sse2,+sse | grep addps ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=-sse2,+sse | FileCheck %s
; PR10497 + another isel issue with sse2 disabled ; PR10497 + another isel issue with sse2 disabled
; (This is primarily checking that this construct doesn't crash.) ; (This is primarily checking that this construct doesn't crash.)
define void @a(<2 x float>* %a, <2 x i32>* %b) { define void @a(<2 x float>* %a, <2 x i32>* %b) {
; CHECK-LABEL: a:
; CHECK: # %bb.0:
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
; CHECK-NEXT: addps %xmm0, %xmm0
; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl (%esp), %edx
; CHECK-NEXT: addl %edx, %edx
; CHECK-NEXT: addl %ecx, %ecx
; CHECK-NEXT: movl %ecx, (%eax)
; CHECK-NEXT: movl %edx, 4(%eax)
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
%cc = load <2 x float>, <2 x float>* %a %cc = load <2 x float>, <2 x float>* %a
%c = fadd <2 x float> %cc, %cc %c = fadd <2 x float> %cc, %cc
%dd = bitcast <2 x float> %c to <2 x i32> %dd = bitcast <2 x float> %c to <2 x i32>
%d = add <2 x i32> %dd, %dd %d = add <2 x i32> %dd, %dd
store <2 x i32> %d, <2 x i32>* %b store <2 x i32> %d, <2 x i32>* %b
ret void ret void
} }

llvm/test/CodeGen/X86/split-vector-rem.ll

; RUN: llc < %s -mtriple=x86_64-- | grep div | count 16 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | grep fmodf | count 8 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) { define <8 x i32> @foo(<8 x i32> %t, <8 x i32> %u) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; CHECK-NEXT: movd %xmm0, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,1,2,3]
; CHECK-NEXT: movd %xmm0, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[2,3,0,1]
; CHECK-NEXT: movd %xmm5, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[2,3,0,1]
; CHECK-NEXT: movd %xmm5, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm5
; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1]
; CHECK-NEXT: movd %xmm4, %eax
; CHECK-NEXT: movd %xmm2, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,2,3]
; CHECK-NEXT: movd %xmm4, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,2,3]
; CHECK-NEXT: movd %xmm2, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm5[0]
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
; CHECK-NEXT: movd %xmm2, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[3,1,2,3]
; CHECK-NEXT: movd %xmm2, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
; CHECK-NEXT: movd %xmm4, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,3,0,1]
; CHECK-NEXT: movd %xmm4, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm4
; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-NEXT: movd %xmm1, %eax
; CHECK-NEXT: movd %xmm3, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
; CHECK-NEXT: movd %xmm1, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,2,3]
; CHECK-NEXT: movd %xmm1, %ecx
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %ecx
; CHECK-NEXT: movd %edx, %xmm1
; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; CHECK-NEXT: movdqa %xmm2, %xmm1
; CHECK-NEXT: retq
%m = srem <8 x i32> %t, %u %m = srem <8 x i32> %t, %u
ret <8 x i32> %m ret <8 x i32> %m
} }
define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) { define <8 x i32> @bar(<8 x i32> %t, <8 x i32> %u) {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movdqa %xmm0, %xmm4
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
; CHECK-NEXT: movd %xmm0, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[3,1,2,3]
; CHECK-NEXT: movd %xmm0, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm4[2,3,0,1]
; CHECK-NEXT: movd %xmm5, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm2[2,3,0,1]
; CHECK-NEXT: movd %xmm5, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm5
; CHECK-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm0[0],xmm5[1],xmm0[1]
; CHECK-NEXT: movd %xmm4, %eax
; CHECK-NEXT: movd %xmm2, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,2,3]
; CHECK-NEXT: movd %xmm4, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,2,3]
; CHECK-NEXT: movd %xmm2, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm5[0]
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
; CHECK-NEXT: movd %xmm2, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[3,1,2,3]
; CHECK-NEXT: movd %xmm2, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,0,1]
; CHECK-NEXT: movd %xmm4, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,3,0,1]
; CHECK-NEXT: movd %xmm4, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm4
; CHECK-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-NEXT: movd %xmm1, %eax
; CHECK-NEXT: movd %xmm3, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
; CHECK-NEXT: movd %xmm1, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,2,3]
; CHECK-NEXT: movd %xmm1, %ecx
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ecx
; CHECK-NEXT: movd %edx, %xmm1
; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; CHECK-NEXT: movdqa %xmm2, %xmm1
; CHECK-NEXT: retq
%m = urem <8 x i32> %t, %u %m = urem <8 x i32> %t, %u
ret <8 x i32> %m ret <8 x i32> %m
} }
define <8 x float> @qux(<8 x float> %t, <8 x float> %u) { define <8 x float> @qux(<8 x float> %t, <8 x float> %u) {
; CHECK-LABEL: qux:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $104, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 112
; CHECK-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; CHECK-NEXT: movaps %xmm2, %xmm1
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm2[2,3]
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1,2,3]
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
; CHECK-NEXT: callq fmodf
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $104, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
%m = frem <8 x float> %t, %u %m = frem <8 x float> %t, %u
ret <8 x float> %m ret <8 x float> %m
} }

llvm/test/CodeGen/X86/sse-align-1.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movap | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define <4 x float> @foo(<4 x float>* %p) nounwind { define <4 x float> @foo(<4 x float>* %p) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: retq
%t = load <4 x float>, <4 x float>* %p %t = load <4 x float>, <4 x float>* %p
ret <4 x float> %t ret <4 x float> %t
} }
define <2 x double> @bar(<2 x double>* %p) nounwind { define <2 x double> @bar(<2 x double>* %p) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: retq
%t = load <2 x double>, <2 x double>* %p %t = load <2 x double>, <2 x double>* %p
ret <2 x double> %t ret <2 x double> %t
} }

llvm/test/CodeGen/X86/sse-align-11.ll

; RUN: llc < %s -mcpu=yonah -mtriple=i686-apple-darwin8 | grep movaps ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=yonah -mtriple=i686-linux-gnu | grep movaps ; RUN: llc < %s -mcpu=yonah -mtriple=i686-apple-darwin8 | FileCheck %s --check-prefix=i686-apple-darwin8
; RUN: llc < %s -mcpu=yonah -mtriple=i686-linux-gnu | FileCheck %s --check-prefix=i686-linux-gnu
; PR8969 - make 32-bit linux have a 16-byte aligned stack ; PR8969 - make 32-bit linux have a 16-byte aligned stack
define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind { define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {
; i686-apple-darwin8-LABEL: foo:
; i686-apple-darwin8: ## %bb.0: ## %entry
; i686-apple-darwin8-NEXT: movaps {{[0-9]+}}(%esp), %xmm0
; i686-apple-darwin8-NEXT: retl
;
; i686-linux-gnu-LABEL: foo:
; i686-linux-gnu: # %bb.0: # %entry
; i686-linux-gnu-NEXT: movaps {{[0-9]+}}(%esp), %xmm0
; i686-linux-gnu-NEXT: retl
entry: entry:
%tmp6 = insertelement <4 x float> undef, float %a, i32 0 %tmp6 = insertelement <4 x float> undef, float %a, i32 0
%tmp7 = insertelement <4 x float> %tmp6, float %b, i32 1 %tmp7 = insertelement <4 x float> %tmp6, float %b, i32 1
%tmp8 = insertelement <4 x float> %tmp7, float %c, i32 2 %tmp8 = insertelement <4 x float> %tmp7, float %c, i32 2
%tmp9 = insertelement <4 x float> %tmp8, float %d, i32 3 %tmp9 = insertelement <4 x float> %tmp8, float %d, i32 3
ret <4 x float> %tmp9 ret <4 x float> %tmp9
} }

llvm/test/CodeGen/X86/sse-align-4.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movup | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define void @foo(<4 x float>* %p, <4 x float> %x) nounwind { define void @foo(<4 x float>* %p, <4 x float> %x) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: retq
store <4 x float> %x, <4 x float>* %p, align 4 store <4 x float> %x, <4 x float>* %p, align 4
ret void ret void
} }
define void @bar(<2 x double>* %p, <2 x double> %x) nounwind { define void @bar(<2 x double>* %p, <2 x double> %x) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: retq
store <2 x double> %x, <2 x double>* %p, align 8 store <2 x double> %x, <2 x double>* %p, align 8
ret void ret void
} }

llvm/test/CodeGen/X86/sse-align-5.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movaps | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define <2 x i64> @bar(<2 x i64>* %p) nounwind { define <2 x i64> @bar(<2 x i64>* %p) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: retq
%t = load <2 x i64>, <2 x i64>* %p %t = load <2 x i64>, <2 x i64>* %p
ret <2 x i64> %t ret <2 x i64> %t
} }

llvm/test/CodeGen/X86/sse-align-6.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movdqu | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x) nounwind { define <2 x i64> @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movdqu (%rdi), %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: psrlq $32, %xmm2
; CHECK-NEXT: pmuludq %xmm1, %xmm2
; CHECK-NEXT: movdqa %xmm1, %xmm3
; CHECK-NEXT: psrlq $32, %xmm3
; CHECK-NEXT: pmuludq %xmm0, %xmm3
; CHECK-NEXT: paddq %xmm2, %xmm3
; CHECK-NEXT: psllq $32, %xmm3
; CHECK-NEXT: pmuludq %xmm1, %xmm0
; CHECK-NEXT: paddq %xmm3, %xmm0
; CHECK-NEXT: retq
%t = load <2 x i64>, <2 x i64>* %p, align 8 %t = load <2 x i64>, <2 x i64>* %p, align 8
%z = mul <2 x i64> %t, %x %z = mul <2 x i64> %t, %x
ret <2 x i64> %z ret <2 x i64> %z
} }

llvm/test/CodeGen/X86/sse-align-8.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movups | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind { define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: retq
store <2 x i64> %x, <2 x i64>* %p, align 8 store <2 x i64> %x, <2 x i64>* %p, align 8
ret void ret void
} }

llvm/test/CodeGen/X86/sse-align-9.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movup | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define <4 x float> @foo(<4 x float>* %p) nounwind { define <4 x float> @foo(<4 x float>* %p) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movups (%rdi), %xmm0
; CHECK-NEXT: retq
%t = load <4 x float>, <4 x float>* %p, align 4 %t = load <4 x float>, <4 x float>* %p, align 4
ret <4 x float> %t ret <4 x float> %t
} }
define <2 x double> @bar(<2 x double>* %p) nounwind { define <2 x double> @bar(<2 x double>* %p) nounwind {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: movups (%rdi), %xmm0
; CHECK-NEXT: retq
%t = load <2 x double>, <2 x double>* %p, align 8 %t = load <2 x double>, <2 x double>* %p, align 8
ret <2 x double> %t ret <2 x double> %t
} }

llvm/test/CodeGen/X86/sse-load-ret.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | not grep movss ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | not grep xmm ; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s
define double @test1(double* %P) { define double @test1(double* %P) {
; CHECK-LABEL: test1:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: fldl (%eax)
; CHECK-NEXT: retl
%X = load double, double* %P ; <double> [#uses=1] %X = load double, double* %P ; <double> [#uses=1]
ret double %X ret double %X
} }
define double @test2() { define double @test2() {
; CHECK-LABEL: test2:
; CHECK: # %bb.0:
; CHECK-NEXT: fldl {{\.LCPI.*}}
; CHECK-NEXT: retl
ret double 1.234560e+03 ret double 1.234560e+03
} }
; FIXME: Todo define double @test3(i1 %B) {
;double %test3(bool %B) { ; CHECK-LABEL: test3:
; %C = select bool %B, double 123.412, double 523.01123123 ; CHECK: # %bb.0:
; ret double %C ; CHECK-NEXT: pushl %ebp
;} ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: testb $1, 8(%ebp)
; CHECK-NEXT: jne .LBB2_1
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: jmp .LBB2_3
; CHECK-NEXT: .LBB2_1:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: .LBB2_3:
; CHECK-NEXT: movsd %xmm0, (%esp)
; CHECK-NEXT: fldl (%esp)
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl
%C = select i1 %B, double 123.412, double 523.01123123
ret double %C
}

llvm/test/CodeGen/X86/sse-varargs.ll

; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | grep xmm | grep esp ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
define i32 @t() nounwind { define i32 @t() nounwind {
; CHECK-LABEL: t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: andl $-16, %esp
; CHECK-NEXT: subl $48, %esp
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [10,11,12,13]
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $1, (%esp)
; CHECK-NEXT: calll foo
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl
entry: entry:
tail call void (i32, ...) @foo( i32 1, <4 x i32> < i32 10, i32 11, i32 12, i32 13 > ) nounwind tail call void (i32, ...) @foo( i32 1, <4 x i32> < i32 10, i32 11, i32 12, i32 13 > ) nounwind
ret i32 0 ret i32 0
} }
declare void @foo(i32, ...) declare void @foo(i32, ...)

llvm/test/CodeGen/X86/store-global-address.ll

; RUN: llc < %s -mtriple=i686-- | grep movl | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
@dst = global i32 0 ; <i32*> [#uses=1] @dst = global i32 0 ; <i32*> [#uses=1]
@ptr = global i32* null ; <i32**> [#uses=1] @ptr = global i32* null ; <i32**> [#uses=1]
define void @test() { define void @test() {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $dst, ptr
; CHECK-NEXT: retl
store i32* @dst, i32** @ptr store i32* @dst, i32** @ptr
ret void ret void
} }

llvm/test/CodeGen/X86/storetrunc-fp.ll

; RUN: llc < %s -mtriple=i686-- | not grep flds ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define void @foo(x86_fp80 %a, x86_fp80 %b, float* %fp) { define void @foo(x86_fp80 %a, x86_fp80 %b, float* %fp) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: fldt {{[0-9]+}}(%esp)
; CHECK-NEXT: faddp %st, %st(1)
; CHECK-NEXT: fstps (%eax)
; CHECK-NEXT: retl
%c = fadd x86_fp80 %a, %b %c = fadd x86_fp80 %a, %b
%d = fptrunc x86_fp80 %c to float %d = fptrunc x86_fp80 %c to float
store float %d, float* %fp store float %d, float* %fp
ret void ret void
} }

llvm/test/CodeGen/X86/subreg-to-reg-0.ll

; RUN: llc < %s -mtriple=x86_64-- | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; Do eliminate the zero-extension instruction and rely on ; Do eliminate the zero-extension instruction and rely on
; x86-64's implicit zero-extension! ; x86-64's implicit zero-extension!
define i64 @foo(i32* %p) nounwind { define i64 @foo(i32* %p) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: incl %eax
; CHECK-NEXT: retq
%t = load i32, i32* %p %t = load i32, i32* %p
%n = add i32 %t, 1 %n = add i32 %t, 1
%z = zext i32 %n to i64 %z = zext i32 %n to i64
ret i64 %z ret i64 %z
} }

llvm/test/CodeGen/X86/subreg-to-reg-2.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
; rdar://6707985 ; rdar://6707985
%XXOO = type { %"struct.XXC::XXCC", i8*, %"struct.XXC::XXOO::$_71" } %XXOO = type { %"struct.XXC::XXCC", i8*, %"struct.XXC::XXOO::$_71" }
%XXValue = type opaque %XXValue = type opaque
%"struct.XXC::ArrayStorage" = type { i32, i32, i32, i8*, i8*, [1 x %XXValue*] } %"struct.XXC::ArrayStorage" = type { i32, i32, i32, i8*, i8*, [1 x %XXValue*] }
%"struct.XXC::XXArray" = type { %XXOO, i32, %"struct.XXC::ArrayStorage"* } %"struct.XXC::XXArray" = type { %XXOO, i32, %"struct.XXC::ArrayStorage"* }
%"struct.XXC::XXCC" = type { i32 (...)**, i8* } %"struct.XXC::XXCC" = type { i32 (...)**, i8* }
%"struct.XXC::XXOO::$_71" = type { [2 x %XXValue*] } %"struct.XXC::XXOO::$_71" = type { [2 x %XXValue*] }
define internal fastcc %XXValue* @t(i64* %out, %"struct.XXC::ArrayStorage"* %tmp9) nounwind { define internal fastcc %XXValue* @t(i64* %out, %"struct.XXC::ArrayStorage"* %tmp9) nounwind {
; CHECK-LABEL: t:
; CHECK: ## %bb.0: ## %prologue
; CHECK-NEXT: movq 22222222, %rax
; CHECK-NEXT: movq %rax, (%rdi)
; CHECK-NEXT: movl %eax, %eax
; CHECK-NEXT: movq 32(%rsi,%rax,8), %rax
; CHECK-NEXT: retq
prologue: prologue:
%array = load %XXValue*, %XXValue** inttoptr (i64 11111111 to %XXValue**) ; <%XXValue*> [#uses=0] %array = load %XXValue*, %XXValue** inttoptr (i64 11111111 to %XXValue**) ; <%XXValue*> [#uses=0]
%index = load %XXValue*, %XXValue** inttoptr (i64 22222222 to %XXValue**) ; <%XXValue*> [#uses=1] %index = load %XXValue*, %XXValue** inttoptr (i64 22222222 to %XXValue**) ; <%XXValue*> [#uses=1]
%tmp = ptrtoint %XXValue* %index to i64 ; <i64> [#uses=2] %tmp = ptrtoint %XXValue* %index to i64 ; <i64> [#uses=2]
store i64 %tmp, i64* %out store i64 %tmp, i64* %out
%tmp6 = trunc i64 %tmp to i32 ; <i32> [#uses=1] %tmp6 = trunc i64 %tmp to i32 ; <i32> [#uses=1]
br label %bb5 br label %bb5
bb5: ; preds = %prologue bb5: ; preds = %prologue
%tmp10 = zext i32 %tmp6 to i64 ; <i64> [#uses=1] %tmp10 = zext i32 %tmp6 to i64 ; <i64> [#uses=1]
%tmp11 = getelementptr %"struct.XXC::ArrayStorage", %"struct.XXC::ArrayStorage"* %tmp9, i64 0, i32 5, i64 %tmp10 ; <%XXValue**> [#uses=1] %tmp11 = getelementptr %"struct.XXC::ArrayStorage", %"struct.XXC::ArrayStorage"* %tmp9, i64 0, i32 5, i64 %tmp10 ; <%XXValue**> [#uses=1]
%tmp12 = load %XXValue*, %XXValue** %tmp11, align 8 ; <%XXValue*> [#uses=1] %tmp12 = load %XXValue*, %XXValue** %tmp11, align 8 ; <%XXValue*> [#uses=1]
ret %XXValue* %tmp12 ret %XXValue* %tmp12
} }

llvm/test/CodeGen/X86/subreg-to-reg-4.ll

; RUN: llc < %s -mtriple=x86_64-- > %t ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not grep leaq %t ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; RUN: not grep incq %t
; RUN: not grep decq %t
; RUN: not grep negq %t
; RUN: not grep addq %t
; RUN: not grep subq %t
; RUN: not grep "movl %" %t
; Utilize implicit zero-extension on x86-64 to eliminate explicit ; Utilize implicit zero-extension on x86-64 to eliminate explicit
; zero-extensions. Shrink 64-bit adds to 32-bit when the high ; zero-extensions. Shrink 64-bit adds to 32-bit when the high
; 32-bits will be zeroed. ; 32-bits will be zeroed.
define void @bar(i64 %x, i64 %y, i64* %z) nounwind readnone { define void @bar(i64 %x, i64 %y, i64* %z) nounwind readnone {
; CHECK-LABEL: bar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addl %esi, %edi
; CHECK-NEXT: movq %rdi, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%t0 = add i64 %x, %y %t0 = add i64 %x, %y
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @easy(i32 %x, i32 %y, i64* %z) nounwind readnone { define void @easy(i32 %x, i32 %y, i64* %z) nounwind readnone {
; CHECK-LABEL: easy:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: addl %esi, %edi
; CHECK-NEXT: movq %rdi, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%t0 = add i32 %x, %y %t0 = add i32 %x, %y
%tn = zext i32 %t0 to i64 %tn = zext i32 %t0 to i64
%t1 = and i64 %tn, 4294967295 %t1 = and i64 %tn, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @cola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone { define void @cola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
; CHECK-LABEL: cola:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addl (%rdi), %esi
; CHECK-NEXT: xorq %rcx, %rsi
; CHECK-NEXT: movq %rsi, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%p = load i64, i64* %x %p = load i64, i64* %x
%t0 = add i64 %p, %y %t0 = add i64 %p, %y
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
%t2 = xor i64 %t1, %u %t2 = xor i64 %t1, %u
store i64 %t2, i64* %z store i64 %t2, i64* %z
ret void ret void
} }
define void @yaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone { define void @yaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
; CHECK-LABEL: yaks:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addl (%rdi), %esi
; CHECK-NEXT: xorl %esi, %ecx
; CHECK-NEXT: movq %rcx, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%p = load i64, i64* %x %p = load i64, i64* %x
%t0 = add i64 %p, %y %t0 = add i64 %p, %y
%t1 = xor i64 %t0, %u %t1 = xor i64 %t0, %u
%t2 = and i64 %t1, 4294967295 %t2 = and i64 %t1, 4294967295
store i64 %t2, i64* %z store i64 %t2, i64* %z
ret void ret void
} }
define void @foo(i64 *%x, i64 *%y, i64* %z) nounwind readnone { define void @foo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: addl (%rsi), %eax
; CHECK-NEXT: movq %rax, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%a = load i64, i64* %x %a = load i64, i64* %x
%b = load i64, i64* %y %b = load i64, i64* %y
%t0 = add i64 %a, %b %t0 = add i64 %a, %b
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @avo(i64 %x, i64* %z, i64 %u) nounwind readnone { define void @avo(i64 %x, i64* %z, i64 %u) nounwind readnone {
; CHECK-LABEL: avo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addl $734847, %edi # imm = 0xB367F
; CHECK-NEXT: xorq %rdx, %rdi
; CHECK-NEXT: movq %rdi, (%rsi)
; CHECK-NEXT: retq
entry: entry:
%t0 = add i64 %x, 734847 %t0 = add i64 %x, 734847
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
%t2 = xor i64 %t1, %u %t2 = xor i64 %t1, %u
store i64 %t2, i64* %z store i64 %t2, i64* %z
ret void ret void
} }
define void @phe(i64 %x, i64* %z, i64 %u) nounwind readnone { define void @phe(i64 %x, i64* %z, i64 %u) nounwind readnone {
; CHECK-LABEL: phe:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addl $734847, %edi # imm = 0xB367F
; CHECK-NEXT: xorl %edi, %edx
; CHECK-NEXT: movq %rdx, (%rsi)
; CHECK-NEXT: retq
entry: entry:
%t0 = add i64 %x, 734847 %t0 = add i64 %x, 734847
%t1 = xor i64 %t0, %u %t1 = xor i64 %t0, %u
%t2 = and i64 %t1, 4294967295 %t2 = and i64 %t1, 4294967295
store i64 %t2, i64* %z store i64 %t2, i64* %z
ret void ret void
} }
define void @oze(i64 %y, i64* %z) nounwind readnone { define void @oze(i64 %y, i64* %z) nounwind readnone {
; CHECK-LABEL: oze:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: incl %edi
; CHECK-NEXT: movq %rdi, (%rsi)
; CHECK-NEXT: retq
entry: entry:
%t0 = add i64 %y, 1 %t0 = add i64 %y, 1
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @sbar(i64 %x, i64 %y, i64* %z) nounwind readnone { define void @sbar(i64 %x, i64 %y, i64* %z) nounwind readnone {
; CHECK-LABEL: sbar:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl %esi, %edi
; CHECK-NEXT: movq %rdi, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%t0 = sub i64 %x, %y %t0 = sub i64 %x, %y
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @seasy(i32 %x, i32 %y, i64* %z) nounwind readnone { define void @seasy(i32 %x, i32 %y, i64* %z) nounwind readnone {
; CHECK-LABEL: seasy:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: subl %esi, %edi
; CHECK-NEXT: movq %rdi, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%t0 = sub i32 %x, %y %t0 = sub i32 %x, %y
%tn = zext i32 %t0 to i64 %tn = zext i32 %t0 to i64
%t1 = and i64 %tn, 4294967295 %t1 = and i64 %tn, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @scola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone { define void @scola(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
; CHECK-LABEL: scola:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: subl %esi, %eax
; CHECK-NEXT: xorq %rcx, %rax
; CHECK-NEXT: movq %rax, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%p = load i64, i64* %x %p = load i64, i64* %x
%t0 = sub i64 %p, %y %t0 = sub i64 %p, %y
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
%t2 = xor i64 %t1, %u %t2 = xor i64 %t1, %u
store i64 %t2, i64* %z store i64 %t2, i64* %z
ret void ret void
} }
define void @syaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone { define void @syaks(i64 *%x, i64 %y, i64* %z, i64 %u) nounwind readnone {
; CHECK-LABEL: syaks:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: subl %esi, %eax
; CHECK-NEXT: xorl %eax, %ecx
; CHECK-NEXT: movq %rcx, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%p = load i64, i64* %x %p = load i64, i64* %x
%t0 = sub i64 %p, %y %t0 = sub i64 %p, %y
%t1 = xor i64 %t0, %u %t1 = xor i64 %t0, %u
%t2 = and i64 %t1, 4294967295 %t2 = and i64 %t1, 4294967295
store i64 %t2, i64* %z store i64 %t2, i64* %z
ret void ret void
} }
define void @sfoo(i64 *%x, i64 *%y, i64* %z) nounwind readnone { define void @sfoo(i64 *%x, i64 *%y, i64* %z) nounwind readnone {
; CHECK-LABEL: sfoo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: subl (%rsi), %eax
; CHECK-NEXT: movq %rax, (%rdx)
; CHECK-NEXT: retq
entry: entry:
%a = load i64, i64* %x %a = load i64, i64* %x
%b = load i64, i64* %y %b = load i64, i64* %y
%t0 = sub i64 %a, %b %t0 = sub i64 %a, %b
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @swya(i64 %y, i64* %z) nounwind readnone { define void @swya(i64 %y, i64* %z) nounwind readnone {
; CHECK-LABEL: swya:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: negl %edi
; CHECK-NEXT: movq %rdi, (%rsi)
; CHECK-NEXT: retq
entry: entry:
%t0 = sub i64 0, %y %t0 = sub i64 0, %y
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }
define void @soze(i64 %y, i64* %z) nounwind readnone { define void @soze(i64 %y, i64* %z) nounwind readnone {
; CHECK-LABEL: soze:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: decl %edi
; CHECK-NEXT: movq %rdi, (%rsi)
; CHECK-NEXT: retq
entry: entry:
%t0 = sub i64 %y, 1 %t0 = sub i64 %y, 1
%t1 = and i64 %t0, 4294967295 %t1 = and i64 %t0, 4294967295
store i64 %t1, i64* %z store i64 %t1, i64* %z
ret void ret void
} }

llvm/test/CodeGen/X86/switch-zextload.ll

; RUN: llc < %s | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; Do zextload, instead of a load and a separate zext. ; Do zextload, instead of a load and a separate zext.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.6" target triple = "i386-apple-darwin9.6"
%struct.move_s = type { i32, i32, i32, i32, i32, i32 } %struct.move_s = type { i32, i32, i32, i32, i32, i32 }
%struct.node_t = type { i8, i8, i8, i8, i32, i32, %struct.node_t**, %struct.node_t*, %struct.move_s } %struct.node_t = type { i8, i8, i8, i8, i32, i32, %struct.node_t**, %struct.node_t*, %struct.move_s }
define fastcc void @set_proof_and_disproof_numbers(%struct.node_t* nocapture %node) nounwind { define fastcc void @set_proof_and_disproof_numbers(%struct.node_t* nocapture %node) nounwind {
; CHECK-LABEL: set_proof_and_disproof_numbers:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movzbl 0, %eax
; CHECK-NEXT: cmpl $3, %eax
; CHECK-NEXT: ja LBB0_3
; CHECK-NEXT: ## %bb.1: ## %entry
; CHECK-NEXT: jmpl *LJTI0_0(,%eax,4)
; CHECK-NEXT: LBB0_3: ## %return
; CHECK-NEXT: retl
; CHECK-NEXT: LBB0_2: ## %bb31
; CHECK-NEXT: ud2
entry: entry:
%0 = load i8, i8* null, align 1 ; <i8> [#uses=1] %0 = load i8, i8* null, align 1 ; <i8> [#uses=1]
switch i8 %0, label %return [ switch i8 %0, label %return [
i8 2, label %bb31 i8 2, label %bb31
i8 0, label %bb80 i8 0, label %bb80
i8 1, label %bb82 i8 1, label %bb82
i8 3, label %bb84 i8 3, label %bb84
] ]
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llvm/test/CodeGen/X86/tailcall.ll

; RUN: llc < %s -mtriple=i686-- -tailcallopt | grep TAILCALL | count 7 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -tailcallopt | FileCheck %s
; With -tailcallopt, CodeGen guarantees a tail call optimization ; With -tailcallopt, CodeGen guarantees a tail call optimization
; for all of these. ; for all of these.
declare fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) declare fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4)
define fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind { define fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
; CHECK-LABEL: tailcaller:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: jmp tailcallee # TAILCALL
entry: entry:
%tmp11 = tail call fastcc i32 @tailcallee(i32 %in1, i32 %in2, i32 %in1, i32 %in2) %tmp11 = tail call fastcc i32 @tailcallee(i32 %in1, i32 %in2, i32 %in1, i32 %in2)
ret i32 %tmp11 ret i32 %tmp11
} }
declare fastcc i8* @alias_callee() declare fastcc i8* @alias_callee()
define fastcc noalias i8* @noalias_caller() nounwind { define fastcc noalias i8* @noalias_caller() nounwind {
; CHECK-LABEL: noalias_caller:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp alias_callee # TAILCALL
%p = tail call fastcc i8* @alias_callee() %p = tail call fastcc i8* @alias_callee()
ret i8* %p ret i8* %p
} }
declare fastcc noalias i8* @noalias_callee() declare fastcc noalias i8* @noalias_callee()
define fastcc i8* @alias_caller() nounwind { define fastcc i8* @alias_caller() nounwind {
; CHECK-LABEL: alias_caller:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp noalias_callee # TAILCALL
%p = tail call fastcc noalias i8* @noalias_callee() %p = tail call fastcc noalias i8* @noalias_callee()
ret i8* %p ret i8* %p
} }
declare fastcc i32 @i32_callee() declare fastcc i32 @i32_callee()
define fastcc i32 @ret_undef() nounwind { define fastcc i32 @ret_undef() nounwind {
; CHECK-LABEL: ret_undef:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp i32_callee # TAILCALL
%p = tail call fastcc i32 @i32_callee() %p = tail call fastcc i32 @i32_callee()
ret i32 undef ret i32 undef
} }
declare fastcc void @does_not_return() declare fastcc void @does_not_return()
define fastcc i32 @noret() nounwind { define fastcc i32 @noret() nounwind {
; CHECK-LABEL: noret:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp does_not_return # TAILCALL
tail call fastcc void @does_not_return() tail call fastcc void @does_not_return()
unreachable unreachable
} }
define fastcc void @void_test(i32, i32, i32, i32) { define fastcc void @void_test(i32, i32, i32, i32) {
; CHECK-LABEL: void_test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: jmp void_test # TAILCALL
entry: entry:
tail call fastcc void @void_test( i32 %0, i32 %1, i32 %2, i32 %3) tail call fastcc void @void_test( i32 %0, i32 %1, i32 %2, i32 %3)
ret void ret void
} }
define fastcc i1 @i1test(i32, i32, i32, i32) { define fastcc i1 @i1test(i32, i32, i32, i32) {
; CHECK-LABEL: i1test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: jmp i1test # TAILCALL
entry: entry:
%4 = tail call fastcc i1 @i1test( i32 %0, i32 %1, i32 %2, i32 %3) %4 = tail call fastcc i1 @i1test( i32 %0, i32 %1, i32 %2, i32 %3)
ret i1 %4 ret i1 %4
} }

llvm/test/CodeGen/X86/twoaddr-coalesce.ll

; RUN: llc < %s -mtriple=i686-- | grep mov | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; rdar://6523745 ; rdar://6523745
@"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] @"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1]
define i32 @foo() nounwind { define i32 @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %bb1.thread
; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb1
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %ebx, %eax
; CHECK-NEXT: shrb $7, %al
; CHECK-NEXT: addb %bl, %al
; CHECK-NEXT: sarb %al
; CHECK-NEXT: movsbl %al, %eax
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $LC
; CHECK-NEXT: calll printf
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: incl %ebx
; CHECK-NEXT: cmpl $258, %ebx # imm = 0x102
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %bb2
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popl %ebx
; CHECK-NEXT: retl
bb1.thread: bb1.thread:
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb1.thread bb1: ; preds = %bb1, %bb1.thread
%i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ] ; <i32> [#uses=2] %i.0.reg2mem.0 = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ] ; <i32> [#uses=2]
%0 = trunc i32 %i.0.reg2mem.0 to i8 ; <i8> [#uses=1] %0 = trunc i32 %i.0.reg2mem.0 to i8 ; <i8> [#uses=1]
%1 = sdiv i8 %0, 2 ; <i8> [#uses=1] %1 = sdiv i8 %0, 2 ; <i8> [#uses=1]
%2 = sext i8 %1 to i32 ; <i32> [#uses=1] %2 = sext i8 %1 to i32 ; <i32> [#uses=1]
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llvm/test/CodeGen/X86/umul-with-carry.ll

; RUN: llc < %s -mtriple=i386-- | grep "jc" | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; XFAIL: * ; RUN: llc < %s -mtriple=i386-- | FileCheck %s
; FIXME: umul-with-overflow not supported yet. ; FIXME: umul-with-overflow not supported yet.
@ok = internal constant [4 x i8] c"%d\0A\00" @ok = internal constant [4 x i8] c"%d\0A\00"
@no = internal constant [4 x i8] c"no\0A\00" @no = internal constant [4 x i8] c"no\0A\00"
define i1 @func(i32 %v1, i32 %v2) nounwind { define i1 @func(i32 %v1, i32 %v2) nounwind {
; CHECK-LABEL: func:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: mull {{[0-9]+}}(%esp)
; CHECK-NEXT: jno .LBB0_1
; CHECK-NEXT: # %bb.2: # %carry
; CHECK-NEXT: pushl $no
; CHECK-NEXT: calll printf
; CHECK-NEXT: addl $4, %esp
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retl
; CHECK-NEXT: .LBB0_1: # %normal
; CHECK-NEXT: pushl %eax
; CHECK-NEXT: pushl $ok
; CHECK-NEXT: calll printf
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: movb $1, %al
; CHECK-NEXT: retl
entry: entry:
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2) %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%sum = extractvalue {i32, i1} %t, 0 %sum = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1 %obit = extractvalue {i32, i1} %t, 1
br i1 %obit, label %carry, label %normal br i1 %obit, label %carry, label %normal
normal: normal:
%t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
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llvm/test/CodeGen/X86/variable-sized-darwin-bzero.ll

; RUN: llc < %s -mtriple=i686-apple-darwin10 | grep __bzero ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin10 | FileCheck %s
define void @foo(i8* %p, i64 %n) { define void @foo(i8* %p, i64 %n) {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0:
; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, (%esp)
; CHECK-NEXT: calll ___bzero
; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl
call void @llvm.memset.p0i8.i64(i8* align 4 %p, i8 0, i64 %n, i1 false) call void @llvm.memset.p0i8.i64(i8* align 4 %p, i8 0, i64 %n, i1 false)
ret void ret void
} }
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind

llvm/test/CodeGen/X86/vec_align.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=yonah -relocation-model=static | grep movaps | count 2 ; RUN: llc < %s -mcpu=yonah -relocation-model=static | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
%f4 = type <4 x float> %f4 = type <4 x float>
@G = external global { float,float,float,float}, align 16 @G = external global { float,float,float,float}, align 16
define %f4 @test1(float %W, float %X, float %Y, float %Z) nounwind { define %f4 @test1(float %W, float %X, float %Y, float %Z) nounwind {
; CHECK-LABEL: test1:
; CHECK: ## %bb.0:
; CHECK-NEXT: movaps {{[0-9]+}}(%esp), %xmm0
; CHECK-NEXT: retl
%tmp = insertelement %f4 undef, float %W, i32 0 %tmp = insertelement %f4 undef, float %W, i32 0
%tmp2 = insertelement %f4 %tmp, float %X, i32 1 %tmp2 = insertelement %f4 %tmp, float %X, i32 1
%tmp4 = insertelement %f4 %tmp2, float %Y, i32 2 %tmp4 = insertelement %f4 %tmp2, float %Y, i32 2
%tmp6 = insertelement %f4 %tmp4, float %Z, i32 3 %tmp6 = insertelement %f4 %tmp4, float %Z, i32 3
ret %f4 %tmp6 ret %f4 %tmp6
} }
define %f4 @test2() nounwind { define %f4 @test2() nounwind {
; CHECK-LABEL: test2:
; CHECK: ## %bb.0:
; CHECK-NEXT: movaps _G, %xmm0
; CHECK-NEXT: retl
%Wp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 0 %Wp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 0
%Xp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 1 %Xp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 1
%Yp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 2 %Yp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 2
%Zp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 3 %Zp = getelementptr { float,float,float,float}, { float,float,float,float}* @G, i32 0, i32 3
%W = load float, float* %Wp %W = load float, float* %Wp
%X = load float, float* %Xp %X = load float, float* %Xp
%Y = load float, float* %Yp %Y = load float, float* %Yp
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llvm/test/CodeGen/X86/vec_call.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=generic -mattr=+sse2 -mtriple=i686-apple-darwin8 | \ ; RUN: llc < %s -mcpu=generic -mattr=+sse2 -mtriple=i686-apple-darwin8 | FileCheck %s
; RUN: grep "subl.*60"
; RUN: llc < %s -mcpu=generic -mattr=+sse2 -mtriple=i686-apple-darwin8 | \
; RUN: grep "movaps.*32"
define void @test() { define void @test() {
; CHECK-LABEL: test:
; CHECK: ## %bb.0:
; CHECK-NEXT: subl $60, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [0,1,3,9]
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $7, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $6, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $5, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $4, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $3, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $2, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl $1, (%esp)
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4,3,2,1]
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [8,7,6,5]
; CHECK-NEXT: movaps {{.*#+}} xmm2 = [6,4,2,0]
; CHECK-NEXT: movaps {{.*#+}} xmm3 = [8,4,2,1]
; CHECK-NEXT: calll _xx
; CHECK-NEXT: addl $60, %esp
; CHECK-NEXT: retl
tail call void @xx( i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <2 x i64> bitcast (<4 x i32> < i32 4, i32 3, i32 2, i32 1 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 8, i32 7, i32 6, i32 5 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 6, i32 4, i32 2, i32 0 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 8, i32 4, i32 2, i32 1 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 0, i32 1, i32 3, i32 9 > to <2 x i64>) ) tail call void @xx( i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <2 x i64> bitcast (<4 x i32> < i32 4, i32 3, i32 2, i32 1 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 8, i32 7, i32 6, i32 5 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 6, i32 4, i32 2, i32 0 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 8, i32 4, i32 2, i32 1 > to <2 x i64>), <2 x i64> bitcast (<4 x i32> < i32 0, i32 1, i32 3, i32 9 > to <2 x i64>) )
ret void ret void
} }
declare void @xx(i32, i32, i32, i32, i32, i32, i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>) declare void @xx(i32, i32, i32, i32, i32, i32, i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>)

llvm/test/CodeGen/X86/vector-intrinsics.ll

; RUN: llc < %s -mtriple=x86_64-- | grep call | count 43 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
declare <4 x double> @llvm.sin.v4f64(<4 x double> %p) declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
declare <4 x double> @llvm.cos.v4f64(<4 x double> %p) declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q) declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32) declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32)
define <4 x double> @foo(<4 x double> %p) define <4 x double> @foo(<4 x double> %p)
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq sin
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq sin
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq sin
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq sin
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
{ {
%t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p) %t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p)
ret <4 x double> %t ret <4 x double> %t
} }
define <4 x double> @goo(<4 x double> %p) define <4 x double> @goo(<4 x double> %p)
; CHECK-LABEL: goo:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq cos
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq cos
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq cos
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq cos
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $56, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
{ {
%t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p) %t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p)
ret <4 x double> %t ret <4 x double> %t
} }
define <4 x double> @moo(<4 x double> %p, <4 x double> %q) define <4 x double> @moo(<4 x double> %p, <4 x double> %q)
; CHECK-LABEL: moo:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $88, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: movaps %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, %xmm1
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $88, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
{ {
%t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q) %t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
ret <4 x double> %t ret <4 x double> %t
} }
define <4 x double> @zoo(<4 x double> %p, i32 %q) define <4 x double> @zoo(<4 x double> %p, i32 %q)
; CHECK-LABEL: zoo:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: subq $48, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 64
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movl %edi, %ebx
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebx, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebx, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebx, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: addq $48, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
{ {
%t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q) %t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
ret <4 x double> %t ret <4 x double> %t
} }
declare <9 x double> @llvm.exp.v9f64(<9 x double> %a) declare <9 x double> @llvm.exp.v9f64(<9 x double> %a)
declare <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b) declare <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b)
declare <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32) declare <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32)
define void @a(<9 x double>* %p) nounwind { define void @a(<9 x double>* %p) nounwind {
; CHECK-LABEL: a:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $96, %rsp
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 16(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps 32(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq exp
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: callq exp
; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 16(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 32(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 48(%rbx)
; CHECK-NEXT: addq $96, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
%a = load <9 x double>, <9 x double>* %p %a = load <9 x double>, <9 x double>* %p
%r = call <9 x double> @llvm.exp.v9f64(<9 x double> %a) %r = call <9 x double> @llvm.exp.v9f64(<9 x double> %a)
store <9 x double> %r, <9 x double>* %p store <9 x double> %r, <9 x double>* %p
ret void ret void
} }
define void @b(<9 x double>* %p, <9 x double>* %q) nounwind { define void @b(<9 x double>* %p, <9 x double>* %q) nounwind {
; CHECK-LABEL: b:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $160, %rsp
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 16(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps 32(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rdi), %xmm2
; CHECK-NEXT: movaps %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rsi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 16(%rsi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 32(%rsi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rsi), %xmm1
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps %xmm2, %xmm0
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: callq pow
; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 16(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 32(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 48(%rbx)
; CHECK-NEXT: addq $160, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
%a = load <9 x double>, <9 x double>* %p %a = load <9 x double>, <9 x double>* %p
%b = load <9 x double>, <9 x double>* %q %b = load <9 x double>, <9 x double>* %q
%r = call <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b) %r = call <9 x double> @llvm.pow.v9f64(<9 x double> %a, <9 x double> %b)
store <9 x double> %r, <9 x double>* %p store <9 x double> %r, <9 x double>* %p
ret void ret void
} }
define void @c(<9 x double>* %p, i32 %n) nounwind { define void @c(<9 x double>* %p, i32 %n) nounwind {
; CHECK-LABEL: c:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbp
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: subq $104, %rsp
; CHECK-NEXT: movl %esi, %ebp
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movaps (%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 16(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps 32(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps 48(%rdi), %xmm0
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movl %esi, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movl %ebp, %edi
; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movsd %xmm0, 64(%rbx)
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, (%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 16(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 32(%rbx)
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movaps %xmm0, 48(%rbx)
; CHECK-NEXT: addq $104, %rsp
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: retq
%a = load <9 x double>, <9 x double>* %p %a = load <9 x double>, <9 x double>* %p
%r = call <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32 %n) %r = call <9 x double> @llvm.powi.v9f64(<9 x double> %a, i32 %n)
store <9 x double> %r, <9 x double>* %p store <9 x double> %r, <9 x double>* %p
ret void ret void
} }

llvm/test/CodeGen/X86/vector-variable-idx.ll

; RUN: llc < %s -mtriple=x86_64-- | grep movss | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
; PR2676 ; PR2676
define float @foo(<4 x float> %p, i32 %t) { define float @foo(<4 x float> %p, i32 %t) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $3, %edi
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: retq
%z = extractelement <4 x float> %p, i32 %t %z = extractelement <4 x float> %p, i32 %t
ret float %z ret float %z
} }
define <4 x float> @bar(<4 x float> %p, float %f, i32 %t) { define <4 x float> @bar(<4 x float> %p, float %f, i32 %t) {
; CHECK-LABEL: bar:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: andl $3, %edi
; CHECK-NEXT: movss %xmm1, -24(%rsp,%rdi,4)
; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: retq
%z = insertelement <4 x float> %p, float %f, i32 %t %z = insertelement <4 x float> %p, float %f, i32 %t
ret <4 x float> %z ret <4 x float> %z
} }

llvm/test/CodeGen/X86/volatile.ll

; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | grep movsd | count 5 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=sse2 -O0 | grep -v esp | grep movsd | count 5 ; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | FileCheck %s -check-prefixes=ALL,OPT
; RUN: llc < %s -mtriple=i686-- -mattr=sse2 -O0 | FileCheck %s --check-prefixes=ALL,NOOPT
@x = external global double @x = external global double
define void @foo() nounwind { define void @foo() nounwind {
; OPT-LABEL: foo:
; OPT: # %bb.0:
; OPT-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; OPT-NEXT: xorps %xmm0, %xmm0
; OPT-NEXT: movsd %xmm0, x
; OPT-NEXT: movsd %xmm0, x
; OPT-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; OPT-NEXT: retl
;
; NOOPT-LABEL: foo:
; NOOPT: # %bb.0:
; NOOPT-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; NOOPT-NEXT: xorps %xmm1, %xmm1
; NOOPT-NEXT: movsd %xmm1, x
; NOOPT-NEXT: movsd %xmm1, x
; NOOPT-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; NOOPT-NEXT: retl
%a = load volatile double, double* @x %a = load volatile double, double* @x
store volatile double 0.0, double* @x store volatile double 0.0, double* @x
store volatile double 0.0, double* @x store volatile double 0.0, double* @x
%b = load volatile double, double* @x %b = load volatile double, double* @x
ret void ret void
} }
define void @bar() nounwind { define void @bar() nounwind {
; ALL-LABEL: bar:
; ALL: # %bb.0:
; ALL-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; ALL-NEXT: retl
%c = load volatile double, double* @x %c = load volatile double, double* @x
ret void ret void
} }

llvm/test/CodeGen/X86/x86-64-arg.ll

; RUN: llc < %s | grep "movl %edi, %eax" ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; The input value is already sign extended, don't re-extend it. ; The input value is already sign extended, don't re-extend it.
; This testcase corresponds to: ; This testcase corresponds to:
; int test(short X) { return (int)X; } ; int test(short X) { return (int)X; }
target datalayout = "e-p:64:64" target datalayout = "e-p:64:64"
target triple = "x86_64-apple-darwin8" target triple = "x86_64-apple-darwin8"
define i32 @test(i16 signext %X) { define i32 @test(i16 signext %X) {
; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
entry: entry:
%tmp12 = sext i16 %X to i32 ; <i32> [#uses=1] %tmp12 = sext i16 %X to i32 ; <i32> [#uses=1]
ret i32 %tmp12 ret i32 %tmp12
} }

llvm/test/CodeGen/X86/x86-64-disp.ll

; RUN: llc < %s | grep mov | count 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; Fold an offset into an address even if it's not a 32-bit ; Fold an offset into an address even if it's not a 32-bit
; signed integer. ; signed integer.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@call_used_regs = external global [53 x i8], align 32 @call_used_regs = external global [53 x i8], align 32
define fastcc void @foo() nounwind { define fastcc void @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
; CHECK-NEXT: movb $1, call_used_regs(%rax)
; CHECK-NEXT: retq
%t = getelementptr [53 x i8], [53 x i8]* @call_used_regs, i64 0, i64 4294967295 %t = getelementptr [53 x i8], [53 x i8]* @call_used_regs, i64 0, i64 4294967295
store i8 1, i8* %t, align 1 store i8 1, i8* %t, align 1
ret void ret void
} }

llvm/test/CodeGen/X86/x86-64-gv-offset.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep lea ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
%struct.x = type { float, double } %struct.x = type { float, double }
@X = global %struct.x { float 1.000000e+00, double 2.000000e+00 }, align 16 ; <%struct.x*> [#uses=2] @X = global %struct.x { float 1.000000e+00, double 2.000000e+00 }, align 16 ; <%struct.x*> [#uses=2]
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq _t
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
entry: entry:
%tmp2 = load float, float* getelementptr (%struct.x, %struct.x* @X, i32 0, i32 0), align 16 ; <float> [#uses=1] %tmp2 = load float, float* getelementptr (%struct.x, %struct.x* @X, i32 0, i32 0), align 16 ; <float> [#uses=1]
%tmp4 = load double, double* getelementptr (%struct.x, %struct.x* @X, i32 0, i32 1), align 8 ; <double> [#uses=1] %tmp4 = load double, double* getelementptr (%struct.x, %struct.x* @X, i32 0, i32 1), align 8 ; <double> [#uses=1]
tail call void @t( float %tmp2, double %tmp4 ) nounwind tail call void @t( float %tmp2, double %tmp4 ) nounwind
ret i32 0 ret i32 0
} }
declare void @t(float, double) declare void @t(float, double)

llvm/test/CodeGen/X86/x86-64-mem.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep GOTPCREL %t1 | count 4 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s --check-prefix=DARWIN
; RUN: grep %%rip %t1 | count 6 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=static | FileCheck %s --check-prefix=LINUX
; RUN: grep movq %t1 | count 6
; RUN: grep leaq %t1 | count 1
; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=static -o %t2
; RUN: grep movl %t2 | count 2
; RUN: grep movq %t2 | count 2
@ptr = external global i32* ; <i32**> [#uses=1] @ptr = external global i32* ; <i32**> [#uses=1]
@src = external global [0 x i32] ; <[0 x i32]*> [#uses=1] @src = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
@dst = external global [0 x i32] ; <[0 x i32]*> [#uses=1] @dst = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
@lptr = internal global i32* null ; <i32**> [#uses=1] @lptr = internal global i32* null ; <i32**> [#uses=1]
@ldst = internal global [500 x i32] zeroinitializer, align 32 ; <[500 x i32]*> [#uses=1] @ldst = internal global [500 x i32] zeroinitializer, align 32 ; <[500 x i32]*> [#uses=1]
@lsrc = internal global [500 x i32] zeroinitializer, align 32 ; <[500 x i32]*> [#uses=0] @lsrc = internal global [500 x i32] zeroinitializer, align 32 ; <[500 x i32]*> [#uses=0]
@bsrc = internal global [500000 x i32] zeroinitializer, align 32 ; <[500000 x i32]*> [#uses=0] @bsrc = internal global [500000 x i32] zeroinitializer, align 32 ; <[500000 x i32]*> [#uses=0]
@bdst = internal global [500000 x i32] zeroinitializer, align 32 ; <[500000 x i32]*> [#uses=0] @bdst = internal global [500000 x i32] zeroinitializer, align 32 ; <[500000 x i32]*> [#uses=0]
define void @test1() nounwind { define void @test1() nounwind {
; DARWIN-LABEL: test1:
; DARWIN: ## %bb.0:
; DARWIN-NEXT: movq _src@{{.*}}(%rip), %rax
; DARWIN-NEXT: movl (%rax), %eax
; DARWIN-NEXT: movq _dst@{{.*}}(%rip), %rcx
; DARWIN-NEXT: movl %eax, (%rcx)
; DARWIN-NEXT: retq
;
; LINUX-LABEL: test1:
; LINUX: # %bb.0:
; LINUX-NEXT: movl {{.*}}(%rip), %eax
; LINUX-NEXT: movl %eax, {{.*}}(%rip)
; LINUX-NEXT: retq
%tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @src, i32 0, i32 0) ; <i32> [#uses=1] %tmp = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @src, i32 0, i32 0) ; <i32> [#uses=1]
store i32 %tmp, i32* getelementptr ([0 x i32], [0 x i32]* @dst, i32 0, i32 0) store i32 %tmp, i32* getelementptr ([0 x i32], [0 x i32]* @dst, i32 0, i32 0)
ret void ret void
} }
define void @test2() nounwind { define void @test2() nounwind {
; DARWIN-LABEL: test2:
; DARWIN: ## %bb.0:
; DARWIN-NEXT: movq _dst@{{.*}}(%rip), %rax
; DARWIN-NEXT: movq _ptr@{{.*}}(%rip), %rcx
; DARWIN-NEXT: movq %rax, (%rcx)
; DARWIN-NEXT: retq
;
; LINUX-LABEL: test2:
; LINUX: # %bb.0:
; LINUX-NEXT: movq $dst, {{.*}}(%rip)
; LINUX-NEXT: retq
store i32* getelementptr ([0 x i32], [0 x i32]* @dst, i32 0, i32 0), i32** @ptr store i32* getelementptr ([0 x i32], [0 x i32]* @dst, i32 0, i32 0), i32** @ptr
ret void ret void
} }
define void @test3() nounwind { define void @test3() nounwind {
; DARWIN-LABEL: test3:
; DARWIN: ## %bb.0:
; DARWIN-NEXT: leaq {{.*}}(%rip), %rax
; DARWIN-NEXT: movq %rax, {{.*}}(%rip)
; DARWIN-NEXT: retq
;
; LINUX-LABEL: test3:
; LINUX: # %bb.0:
; LINUX-NEXT: movq $ldst, {{.*}}(%rip)
; LINUX-NEXT: retq
store i32* getelementptr ([500 x i32], [500 x i32]* @ldst, i32 0, i32 0), i32** @lptr store i32* getelementptr ([500 x i32], [500 x i32]* @ldst, i32 0, i32 0), i32** @lptr
br label %return br label %return
return: ; preds = %0 return: ; preds = %0
ret void ret void
} }

llvm/test/CodeGen/X86/x86-64-pic-1.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "callq f@PLT" %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
define void @g() { define void @g() {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq f@PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry: entry:
call void @f( ) call void @f( )
ret void ret void
} }
declare void @f() declare void @f()

llvm/test/CodeGen/X86/x86-64-pic-10.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "callq g@PLT" %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
@g = weak alias i32 (), i32 ()* @f @g = weak alias i32 (), i32 ()* @f
define void @h() { define void @h() {
; CHECK-LABEL: h:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq g@PLT
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry: entry:
%tmp31 = call i32 @g() %tmp31 = call i32 @g()
ret void ret void
} }
define weak i32 @f() { define weak i32 @f() {
; CHECK-LABEL: f:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: retq
ret i32 42 ret i32 42
} }

llvm/test/CodeGen/X86/x86-64-pic-11.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "callq __fixunsxfti@PLT" %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
define i128 @f(x86_fp80 %a) nounwind { define i128 @f(x86_fp80 %a) nounwind {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt (%rsp)
; CHECK-NEXT: callq __fixunsxfti@PLT
; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: retq
entry: entry:
%tmp78 = fptoui x86_fp80 %a to i128 %tmp78 = fptoui x86_fp80 %a to i128
ret i128 %tmp78 ret i128 %tmp78
} }

llvm/test/CodeGen/X86/x86-64-pic-2.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "callq f" %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
; RUN: not grep "callq f@PLT" %t1
define void @g() { define void @g() {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq f
; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry: entry:
call void @f( ) call void @f( )
ret void ret void
} }
declare hidden void @f() declare hidden void @f()

llvm/test/CodeGen/X86/x86-64-pic-4.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "movq a@GOTPCREL(%rip)," %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
@a = global i32 0 @a = global i32 0
define i32 @get_a() { define i32 @get_a() {
; CHECK-LABEL: get_a:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq a@{{.*}}(%rip), %rax
; CHECK-NEXT: movl (%rax), %eax
; CHECK-NEXT: retq
entry: entry:
%tmp1 = load i32, i32* @a, align 4 %tmp1 = load i32, i32* @a, align 4
ret i32 %tmp1 ret i32 %tmp1
} }

llvm/test/CodeGen/X86/x86-64-pic-5.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "movl a(%rip)," %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
; RUN: not grep GOTPCREL %t1
@a = hidden global i32 0 @a = hidden global i32 0
define i32 @get_a() { define i32 @get_a() {
; CHECK-LABEL: get_a:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
; CHECK-NEXT: retq
entry: entry:
%tmp1 = load i32, i32* @a, align 4 %tmp1 = load i32, i32* @a, align 4
ret i32 %tmp1 ret i32 %tmp1
} }

llvm/test/CodeGen/X86/x86-64-pic-6.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "movl a(%rip)," %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
; RUN: not grep GOTPCREL %t1
@a = internal global i32 0 @a = internal global i32 0
define i32 @get_a() nounwind { define i32 @get_a() nounwind {
; CHECK-LABEL: get_a:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
; CHECK-NEXT: retq
entry: entry:
%tmp1 = load i32, i32* @a, align 4 %tmp1 = load i32, i32* @a, align 4
ret i32 %tmp1 ret i32 %tmp1
} }

llvm/test/CodeGen/X86/x86-64-pic-7.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "movq f@GOTPCREL(%rip)," %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
define void ()* @g() nounwind { define void ()* @g() nounwind {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq f@{{.*}}(%rip), %rax
; CHECK-NEXT: retq
entry: entry:
ret void ()* @f ret void ()* @f
} }
declare void @f() declare void @f()

llvm/test/CodeGen/X86/x86-64-pic-8.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "leaq f(%rip)," %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
; RUN: not grep GOTPCREL %t1
define void ()* @g() { define void ()* @g() {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: leaq {{.*}}(%rip), %rax
; CHECK-NEXT: retq
entry: entry:
ret void ()* @f ret void ()* @f
} }
declare hidden void @f() declare hidden void @f()

llvm/test/CodeGen/X86/x86-64-pic-9.ll

; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: grep "leaq f(%rip)," %t1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s
; RUN: not grep GOTPCREL %t1
define void ()* @g() nounwind { define void ()* @g() nounwind {
; CHECK-LABEL: g:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: leaq {{.*}}(%rip), %rax
; CHECK-NEXT: retq
entry: entry:
ret void ()* @f ret void ()* @f
} }
define internal void @f() nounwind { define internal void @f() nounwind {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: retq
entry: entry:
ret void ret void
} }

llvm/test/CodeGen/X86/x86-64-ret0.ll

; RUN: llc < %s -mtriple=x86_64-- | grep mov | count 1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
define i32 @f() nounwind { define i32 @f() nounwind {
; CHECK-LABEL: f:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movl $1, %edi
; CHECK-NEXT: callq t
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
tail call void @t( i32 1 ) nounwind tail call void @t( i32 1 ) nounwind
ret i32 0 ret i32 0
} }
declare void @t(i32) declare void @t(i32)

llvm/test/CodeGen/X86/x86-64-varargs.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -code-model=large -relocation-model=static | grep call | not grep rax ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -code-model=large -relocation-model=static | FileCheck %s
@.str = internal constant [26 x i8] c"%d, %f, %d, %lld, %d, %f\0A\00" ; <[26 x i8]*> [#uses=1] @.str = internal constant [26 x i8] c"%d, %f, %d, %lld, %d, %f\0A\00" ; <[26 x i8]*> [#uses=1]
declare i32 @printf(i8*, ...) nounwind declare i32 @printf(i8*, ...) nounwind
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: movabsq $_.str, %rdi
; CHECK-NEXT: movabsq $_printf, %r9
; CHECK-NEXT: movabsq $LCPI0_0, %rax
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movabsq $LCPI0_1, %rax
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: movabsq $123456677890, %rcx ## imm = 0x1CBE976802
; CHECK-NEXT: movl $12, %esi
; CHECK-NEXT: movl $120, %edx
; CHECK-NEXT: movl $-10, %r8d
; CHECK-NEXT: movb $2, %al
; CHECK-NEXT: callq *%r9
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: popq %rcx
; CHECK-NEXT: retq
entry: entry:
%tmp10.i = tail call i32 (i8*, ...) @printf( i8* getelementptr ([26 x i8], [26 x i8]* @.str, i32 0, i64 0), i32 12, double 0x3FF3EB8520000000, i32 120, i64 123456677890, i32 -10, double 4.500000e+15 ) nounwind ; <i32> [#uses=0] %tmp10.i = tail call i32 (i8*, ...) @printf( i8* getelementptr ([26 x i8], [26 x i8]* @.str, i32 0, i64 0), i32 12, double 0x3FF3EB8520000000, i32 120, i64 123456677890, i32 -10, double 4.500000e+15 ) nounwind ; <i32> [#uses=0]
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/x86-store-gv-addr.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=static | not grep lea ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -relocation-model=static | not grep lea ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=static | FileCheck %s --check-prefix=x86_64-darwin
; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -relocation-model=static | FileCheck %s --check-prefix=x86_64-linux
@v = external global i32, align 8 @v = external global i32, align 8
@v_addr = external global i32*, align 8 @v_addr = external global i32*, align 8
define void @t() nounwind optsize { define void @t() nounwind optsize {
; x86_64-darwin-LABEL: t:
; x86_64-darwin: ## %bb.0:
; x86_64-darwin-NEXT: movq _v@{{.*}}(%rip), %rax
; x86_64-darwin-NEXT: movq _v_addr@{{.*}}(%rip), %rcx
; x86_64-darwin-NEXT: movq %rax, (%rcx)
; x86_64-darwin-NEXT: ud2
;
; x86_64-linux-LABEL: t:
; x86_64-linux: # %bb.0:
; x86_64-linux-NEXT: movq $v, {{.*}}(%rip)
store i32* @v, i32** @v_addr, align 8 store i32* @v, i32** @v_addr, align 8
unreachable unreachable
} }

llvm/test/CodeGen/X86/xray-selective-instrumentation-miss.ll

; RUN: llc -mcpu=nehalem < %s | not grep xray_sled_ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=nehalem < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8" target triple = "x86_64-apple-darwin8"
define i32 @foo() nounwind uwtable "xray-instruction-threshold"="3" { define i32 @foo() nounwind uwtable "xray-instruction-threshold"="3" {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
entry: entry:
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/xray-selective-instrumentation.ll

; RUN: llc -verify-machineinstrs -mcpu=nehalem < %s | grep xray_sled_ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -mcpu=nehalem | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8" target triple = "x86_64-apple-darwin8"
define i32 @foo() nounwind uwtable "xray-instruction-threshold"="1" { define i32 @foo() nounwind uwtable "xray-instruction-threshold"="1" {
; CHECK-LABEL: foo:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: .p2align 1, 0x90
; CHECK-NEXT: Lxray_sled_0:
; CHECK-NEXT: .ascii "\353\t"
; CHECK-NEXT: nopw 512(%rax,%rax)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .p2align 1, 0x90
; CHECK-NEXT: Lxray_sled_1:
; CHECK-NEXT: retq
; CHECK-NEXT: nopw %cs:512(%rax,%rax)
entry: entry:
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/zext-inreg-1.ll

; RUN: llc < %s -mtriple=i686-- | not grep and ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; These tests differ from the ones in zext-inreg-0.ll in that ; These tests differ from the ones in zext-inreg-0.ll in that
; on x86-64 they do require and instructions. ; on x86-64 they do require and instructions.
; These should use movzbl instead of 'and 255'. ; These should use movzbl instead of 'and 255'.
; This related to not having ZERO_EXTEND_REG node. ; This related to not having ZERO_EXTEND_REG node.
define i64 @l(i64 %d) nounwind { define i64 @l(i64 %d) nounwind {
; CHECK-LABEL: l:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: addl $1, %eax
; CHECK-NEXT: adcl $0, %ecx
; CHECK-NEXT: movzbl %cl, %edx
; CHECK-NEXT: retl
%e = add i64 %d, 1 %e = add i64 %d, 1
%retval = and i64 %e, 1099511627775 %retval = and i64 %e, 1099511627775
ret i64 %retval ret i64 %retval
} }
define i64 @m(i64 %d) nounwind { define i64 @m(i64 %d) nounwind {
; CHECK-LABEL: m:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: addl $1, %eax
; CHECK-NEXT: adcl $0, %ecx
; CHECK-NEXT: movzwl %cx, %edx
; CHECK-NEXT: retl
%e = add i64 %d, 1 %e = add i64 %d, 1
%retval = and i64 %e, 281474976710655 %retval = and i64 %e, 281474976710655
ret i64 %retval ret i64 %retval
} }
llvm/test/CodeGen/X86/shift-coalesce.ll