[PowerPC][NFC] Rename ANDI(S)o8 to ANDI(S)8o

[jsji]

Summary

This is found during https://reviews.llvm.org/D70758
All the other record forms are having suffix o at the end.
ANDIo8 and ANDISo8 are the only two that put o before 8.

This patch rename them to be consistent with others.

[jhibbits]

llvm/lib/Target/PowerPC/P9InstrResources.td

134

It looks to me like we need another change for P9InstrResources.td (not entirely related to this one), to fix some of these regex's to add the '(o)' suffix as well (ADDC, SUBF, SUBFC appear to need that)

[jsji]

Thanks @jhibbits !

llvm/lib/Target/PowerPC/P9InstrResources.td

134

SUBF is just defined below im line 138.

ADDC/SUBBFC are defined later in around line 1035, as they are cracked.

1035 // Cracked ALU operations.
1036 // Here the two ALU ops can actually be done in parallel and therefore the
1037 // latencies are not added together. Otherwise this is like having two
1038 // instructions running together on two pipelines and 2 dispatches. ALU ops are
1039 // 2 cycles each.
1040 def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
1041               DISP_1C, DISP_1C],
1042       (instrs
1043     (instregex "ADDC(8)?(O)?r$"),
1044     (instregex "SUBFC(8)?(O)?r$")
1045 )>;

[jsji]

llvm/lib/Target/PowerPC/P9InstrResources.td

134

Oops, r above in line 1043/1044 should be o. Sorry, I copied wrongly from my working branch where I have done renaming.

[jsji]

Rebased.

[merge_guards_bot]

Build result: pass - 60520 tests passed, 0 failed and 726 were skipped.

Log files: console-log.txt, CMakeCache.txt

llvm/lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C],
     (instregex "SRAD(I)?$"),
     (instregex "EXTSWSLI_32_64$"),
     (instregex "MFV(S)?RD$"),
     (instregex "MTV(S)?RD$"),
     (instregex "MTV(S)?RW(A|Z)$"),
     (instregex "CMP(WI|LWI|W|LW)(8)?$"),
     (instregex "CMP(L)?D(I)?$"),
     (instregex "SUBF(I)?C(8)?(O)?$"),
-    (instregex "ANDI(S)?o(8)?$"),
+    (instregex "ANDI(S)?(8)?(o)?$"),
     (instregex "ADDC(8)?(O)?$"),
     (instregex "ADDIC(8)?(o)?$"),
     (instregex "ADD(8|4)(O)?(o)?$"),
     (instregex "ADD(E|ME|ZE)(8)?(O)?(o)?$"),
     (instregex "SUBF(E|ME|ZE)?(8)?(O)?(o)?$"),
     (instregex "NEG(8)?(O)?(o)?$"),
     (instregex "POPCNTB$"),
     (instregex "ADD(I|IS)?(8)?$"),
     (instregex "LI(S)?(8)?$"),

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

for (ValueRotInfo &VRI : ValueRotsVec) {
 
       SDValue TotalVal;
       if (Use32BitInsts) {
         assert((ANDIMask != 0 || ANDISMask != 0) &&
                "No set bits in mask when using 32-bit ands for 64-bit value");
 
         SDValue ANDIVal, ANDISVal;
         if (ANDIMask != 0)
-          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
+          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64,
                                                    ExtendToInt64(VRot, dl),
                                                    getI32Imm(ANDIMask, dl)),
                             0);
         if (ANDISMask != 0)
-          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
+          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64,
                                                     ExtendToInt64(VRot, dl),
                                                     getI32Imm(ANDISMask, dl)),
                              0);
 
         if (!ANDIVal)
           TotalVal = ANDISVal;
         else if (!ANDISVal)
           TotalVal = ANDIVal;
if (LateMask) {
                "No set bits in mask when using 32-bit ands for 64-bit value");
 
         if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
                                  (unsigned) (ANDISMask != 0) +
                                  (unsigned) (ANDIMask != 0 && ANDISMask != 0);
 
         SDValue ANDIVal, ANDISVal;
         if (ANDIMask != 0)
-          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
+          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64,
                               ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0);
         if (ANDISMask != 0)
-          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
+          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64,
                                ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0);
 
         if (!ANDIVal)
           Res = ANDISVal;
         else if (!ANDISVal)
           Res = ANDIVal;
         else
           Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
if (NewOpc != -1 && IsBitwiseNegate) {
     WideOp =
       SDValue(CurDAG->getMachineNode(NewOpc, dl,
                                      OpToConvToRecForm.getValueType(),
                                      MVT::Glue, Ops), 0);
   } else {
     assert((NewOpc != -1 || !IsBitwiseNegate) &&
            "No record form available for AND8/OR8/XOR8?");
     WideOp =
-      SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
+      SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDI8o : NewOpc, dl,
                                      MVT::i64, MVT::Glue, LHS, RHS), 0);
   }
 
   // Select this node to a single bit from CR0 set by the record-form node
   // just created. For bitwise negation, use the EQ bit which is the equivalent
   // of negating the result (i.e. it is a bit set when the result of the
   // operation is zero).
   SDValue SRIdxVal =
void PPCDAGToDAGISel::Select(SDNode *N) {
   case PPCISD::ANDIo_1_GT_BIT: {
     if (!ANDIGlueBug)
       break;
 
     EVT InVT = N->getOperand(0).getValueType();
     assert((InVT == MVT::i64 || InVT == MVT::i32) &&
            "Invalid input type for ANDIo_1_EQ_BIT");
 
-    unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
+    unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8o : PPC::ANDIo;
     SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
                                         N->getOperand(0),
                                         CurDAG->getTargetConstant(1, dl, InVT)),
                  0);
     SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
     SDValue SRIdxVal =
       CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
                                 PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
for (SDNode *PN : ToPromote) {
       case PPC::CNTLZW:    NewOpcode = PPC::CNTLZW8; break;
       case PPC::CNTTZW:    NewOpcode = PPC::CNTTZW8; break;
       case PPC::RLWIMI:    NewOpcode = PPC::RLWIMI8; break;
       case PPC::OR:        NewOpcode = PPC::OR8; break;
       case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
       case PPC::ORI:       NewOpcode = PPC::ORI8; break;
       case PPC::ORIS:      NewOpcode = PPC::ORIS8; break;
       case PPC::AND:       NewOpcode = PPC::AND8; break;
-      case PPC::ANDIo:     NewOpcode = PPC::ANDIo8; break;
-      case PPC::ANDISo:    NewOpcode = PPC::ANDISo8; break;
+      case PPC::ANDIo:     NewOpcode = PPC::ANDI8o; break;
+      case PPC::ANDISo:    NewOpcode = PPC::ANDIS8o; break;
       }
 
       // Note: During the replacement process, the nodes will be in an
       // inconsistent state (some instructions will have operands with values
       // of the wrong type). Once done, however, everything should be right
       // again.
 
       SmallVector<SDValue, 4> Ops;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
     // Restore FPSCR value.
     BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
   } else if (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
              MI.getOpcode() == PPC::ANDIo_1_GT_BIT ||
              MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
              MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) {
     unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
                        MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
-                          ? PPC::ANDIo8
+                          ? PPC::ANDI8o
                           : PPC::ANDIo;
     bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
                  MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);
 
     MachineRegisterInfo &RegInfo = F->getRegInfo();
     Register Dest = RegInfo.createVirtualRegister(
         Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
 

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                      [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                      "xor", "$rA, $rS, $rB", IIC_IntSimple,
                      [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
 } // let isCommutable = 1
 
 // Logical ops with immediate.
 let Defs = [CR0] in {
-def ANDIo8  : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
+def ANDI8o  : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "andi. $dst, $src1, $src2", IIC_IntGeneral,
                       [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
                       isDOT;
-def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
+def ANDIS8o : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                      "andis. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
                      isDOT;
 }
 def ORI8    : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "ori $dst, $src1, $src2", IIC_IntSimple,
                       [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
 def ORIS8   : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
   if (!MI && !Sub)
     return false;
 
   // The single candidate is called MI.
   if (!MI) MI = Sub;
 
   int NewOpC = -1;
   int MIOpC = MI->getOpcode();
-  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
-      MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
+  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDI8o ||
+      MIOpC == PPC::ANDISo || MIOpC == PPC::ANDIS8o)
     NewOpC = MIOpC;
   else {
     NewOpC = PPC::getRecordFormOpcode(MIOpC);
     if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
       NewOpC = MIOpC;
   }
 
   // FIXME: On the non-embedded POWER architectures, only some of the record
if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
       uint64_t Mask = ~0LLU;
 
       if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
         Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
         // The mask value needs to shift right 16 if we're emitting andis.
         Mask >>= MBInLoHWord ? 0 : 16;
         NewOpC = MIOpC == PPC::RLWINM ?
           (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
-          (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
+          (MBInLoHWord ? PPC::ANDI8o :PPC::ANDIS8o);
       } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
                  (ME - MB + 1 == SH) && (MB >= 16)) {
         // If we are rotating by the exact number of bits as are in the mask
         // and the mask is in the least significant bits of the register,
         // that's just an andis. (as long as the GPR result has no uses).
         Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
         Mask >>= 16;
-        NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
+        NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDIS8o;
       }
       // If we've set the mask, we can transform.
       if (Mask != ~0LLU) {
         MI->RemoveOperand(4);
         MI->RemoveOperand(3);
         MI->getOperand(2).setImm(Mask);
         NumRcRotatesConvertedToRcAnd++;
       }
     } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
       int64_t MB = MI->getOperand(3).getImm();
       if (MB >= 48) {
         uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
-        NewOpC = PPC::ANDIo8;
+        NewOpC = PPC::ANDI8o;
         MI->RemoveOperand(3);
         MI->getOperand(2).setImm(Mask);
         NumRcRotatesConvertedToRcAnd++;
       }
     }
 
     const MCInstrDesc &NewDesc = get(NewOpC);
     MI->setDesc(NewDesc);
void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
                                       const LoadImmediateInfo &LII) const {
   // Remove existing operands.
   int OperandToKeep = LII.SetCR ? 1 : 0;
   for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
     MI.RemoveOperand(i);
 
   // Replace the instruction.
   if (LII.SetCR) {
-    MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
+    MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8o : PPC::ANDIo));
     // Set the immediate.
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
         .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
     return;
   }
   else
     MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
 
bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg,
   case PPC::XOR8:
     III.SignedImm = false;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = true;
     switch(Opc) {
     default: llvm_unreachable("Unknown opcode");
     case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
-    case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
+    case PPC::AND8o: III.ImmOpcode = PPC::ANDI8o; break;
     case PPC::OR: III.ImmOpcode = PPC::ORI; break;
     case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
     case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
     case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
     }
     break;
   case PPC::RLWNM:
   case PPC::RLWNM8:
PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
   }
 
   case PPC::ANDIo:
   case PPC::ANDISo:
   case PPC::ORI:
   case PPC::ORIS:
   case PPC::XORI:
   case PPC::XORIS:
-  case PPC::ANDIo8:
-  case PPC::ANDISo8:
+  case PPC::ANDI8o:
+  case PPC::ANDIS8o:
   case PPC::ORI8:
   case PPC::ORIS8:
   case PPC::XORI8:
   case PPC::XORIS8: {
     // logical operation with 16-bit immediate does not change the upper bits.
     // So, we track the operand register as we do for register copy.
     Register SrcReg = MI.getOperand(1).getReg();
     if (!Register::isVirtualRegister(SrcReg))

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def VectorExtractions {
 
   /*  BE variable byte
       The algorithm here is the same as the LE variable byte except:
       - The shift in the VMX register is by 0/8 for opposite element numbers so
         we simply AND the element number with 0x8
       - The order of elements after the move to GPR is reversed, so we invert
         the bits of the index prior to truncating to the range 0-7
   */
-  dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDIo8 $Idx, 8)));
+  dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8o $Idx, 8)));
   dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC));
   dag BE_MV_VBYTE = (MFVSRD
                       (EXTRACT_SUBREG
                         (v2i64 (COPY_TO_REGCLASS BE_VBYTE_PERMUTE, VSRC)),
                         sub_64));
   dag BE_VBYTE_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 7), $Idx), 3, 60),
                                        sub_32);
   dag BE_VARIABLE_BYTE = (EXTRACT_SUBREG (SRD BE_MV_VBYTE, BE_VBYTE_SHIFT),
                                          sub_32);
 
   /*  BE variable halfword
       The algorithm here is the same as the LE variable halfword except:
       - The shift in the VMX register is by 0/8 for opposite element numbers so
         we simply AND the element number with 0x4 and multiply by 2
       - The order of elements after the move to GPR is reversed, so we invert
         the bits of the index prior to truncating to the range 0-3
   */
   dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                       (RLDICR (ANDIo8 $Idx, 4), 1, 62)));
+                                       (RLDICR (ANDI8o $Idx, 4), 1, 62)));
   dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC));
   dag BE_MV_VHALF = (MFVSRD
                       (EXTRACT_SUBREG
                         (v2i64 (COPY_TO_REGCLASS BE_VHALF_PERMUTE, VSRC)),
                         sub_64));
   dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59),
                                        sub_32);
   dag BE_VARIABLE_HALF = (EXTRACT_SUBREG (SRD BE_MV_VHALF, BE_VHALF_SHIFT),
                                          sub_32);
 
   /*  BE variable word
       The algorithm is the same as the LE variable word except:
       - The shift in the VMX register happens for opposite element numbers
       - The order of elements after the move to GPR is reversed, so we invert
         the bits of the index prior to truncating to the range 0-1
   */
   dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                       (RLDICR (ANDIo8 $Idx, 2), 2, 61)));
+                                       (RLDICR (ANDI8o $Idx, 2), 2, 61)));
   dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC));
   dag BE_MV_VWORD = (MFVSRD
                       (EXTRACT_SUBREG
                         (v2i64 (COPY_TO_REGCLASS BE_VWORD_PERMUTE, VSRC)),
                         sub_64));
   dag BE_VWORD_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 1), $Idx), 5, 58),
                                        sub_32);
   dag BE_VARIABLE_WORD = (EXTRACT_SUBREG (SRD BE_MV_VWORD, BE_VWORD_SHIFT),
                                          sub_32);
 
   /*  BE variable doubleword
       Same as the LE doubleword except we shift in the VMX register for opposite
       element indices.
   */
   dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                        (RLDICR (ANDIo8 $Idx, 1), 3, 60)));
+                                        (RLDICR (ANDI8o $Idx, 1), 3, 60)));
   dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC));
   dag BE_VARIABLE_DWORD =
         (MFVSRD (EXTRACT_SUBREG
                   (v2i64 (COPY_TO_REGCLASS BE_VDWORD_PERMUTE, VSRC)),
                   sub_64));
 
   /*  BE variable float
       - Shift the vector to line up the desired element to BE Word 0

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 88
     %3 = SLDo %0, killed %2, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 0, implicit-def $cr0
+    ; CHECK: ANDI8o %0, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 64
     %3 = SRDo %0, killed %2, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 0, implicit-def $cr0
+    ; CHECK: ANDI8o %0, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = LI8 321
     %0 = COPY $x3
     %2 = AND8o %1, %0, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 321, implicit-def $cr0
+    ; CHECK: ANDI8o %0, 321, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 321
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %0, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = LI8 -1
     %2 = RLDICLo %0, 53, 48, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 65535
+    ; CHECK: ANDI8o %0, 65535
     ; CHECK-LATE: li 3, -1
     ; CHECK-LATE: andi. 3, 3, 65535
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = LI8 200
     %2 = RLDICLo %0, 61, 3, implicit-def $cr0
     ; CHECK: LI8 25
-    ; CHECK: ANDIo8 %0, 25
+    ; CHECK: ANDI8o %0, 25
     ; CHECK-LATE-NOT: andi.
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = LI8 2
     %2 = RLDICLo %0, 32, 32, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 0
+    ; CHECK: ANDI8o %0, 0
     ; CHECK-LATE: li 3, 2
     ; CHECK-LATE: andi. 3, 3, 0
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -22
     %4 = RLWINMo %3, 5, 24, 31, implicit-def $cr0
     ; CHECK: LI -22
-    ; CHECK-NOT: ANDIo8 %3, 65514
+    ; CHECK-NOT: ANDI8o %3, 65514
     ; CHECK-LATE-NOT: andi.
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
     %7 = INSERT_SUBREG %8, killed %6, 1
     %9 = RLDICL killed %7, 0, 32
     $x3 = COPY %9
     BLR8 implicit $lr8, implicit $rm, implicit $x3

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI8 -18
     %3 = RLWINM8o %2, 4, 20, 27, implicit-def $cr0
-    ; CHECK: ANDIo8 %2, 3808
+    ; CHECK: ANDI8o %2, 3808
     ; CHECK-LATE: li 3, -18
     ; CHECK-LATE: andi. 3, 3, 3808
     %7 = COPY killed $cr0
     %6 = RLDICL killed %3, 0, 32
     %8 = ISEL8 %1, %6, %7.sub_eq
     $x3 = COPY %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 

llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir

 # RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -run-pass=if-converter %s -o - | FileCheck %s
 ---
 name:           foo
 body:           |
   bb.0:
   liveins: $x0, $x3
   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 
-  dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+  dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
   $cr2lt = CROR $cr0gt, $cr0gt
   BCn killed renamable $cr2lt, %bb.2
   B %bb.1
 
   bb.1:
     renamable $x3 = LIS8 4096
     MTLR8 $x0, implicit-def $lr8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
   bb.2:
     renamable $x3 = LIS8 4096
     MTLR8 $x0, implicit-def $lr8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 ...
 
 # Diamond testcase with equivalent branches terminating in returns.
 
 # CHECK: body:             |          
 # CHECK:  bb.0:
-# CHECK:    dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+# CHECK:    dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
 # CHECK:    $cr2lt = CROR $cr0gt, $cr0gt
 # CHECK:    renamable $x3 = LIS8 4096
 # CHECK:    MTLR8 $x0, implicit-def $lr8
 # CHECK:    BLR8 implicit $lr8, implicit $rm, implicit $x3
 

llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

 ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64le-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
 
 ; CHECK-LABEL: fn1
 define signext i32 @fn1(i32 %baz) {
   %1 = mul nsw i32 %baz, 208
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
-; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead $cr0
+; CHECK: ANDI8o killed {{[^,]+}}, 65520, implicit-def dead $cr0
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
-; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def $cr0
+; CHECK: ANDI8o {{[^,]+}}, 65520, implicit-def $cr0
 ; CHECK: COPY $cr0
 ; CHECK: BCC
   %5 = icmp eq i64 %4, 0
   br i1 %5, label %foo, label %bar
 
 foo:
   ret i32 1
 

llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
 # RUN: -simplify-mir %s -o - | FileCheck %s
 ---
 name:            poc
 alignment:       16
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: poc
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1, %bb.2
   ; CHECK:   liveins: $x3, $x4, $x5, $x6
   ; CHECK:   [[COPY:%[0-9]+]]:g8rc = COPY $x6
   ; CHECK:   [[COPY1:%[0-9]+]]:g8rc = COPY $x5
   ; CHECK:   [[COPY2:%[0-9]+]]:g8rc = COPY $x4
   ; CHECK:   [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
-  ; CHECK:   [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0
+  ; CHECK:   [[ANDI8o_:%[0-9]+]]:g8rc = ANDI8o [[COPY1]], 1, implicit-def $cr0
   ; CHECK:   [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
   ; CHECK:   BCn killed [[COPY4]], %bb.2
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   liveins: $x3
   ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
-  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
+  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8o_]], 2, 61
   ; CHECK:   $x3 = COPY [[RLDICR]]
   ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
   ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
   ; CHECK:   $x3 = COPY [[ADD8_]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   ; CHECK: bb.2:
   ; CHECK:   [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
   ; CHECK:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
   ; CHECK:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
   ; CHECK:   $x3 = COPY [[INSERT_SUBREG]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   bb.0.entry:
     successors: %bb.1, %bb.2
     liveins: $x3, $x4, $x5, $x6
 
     %4:g8rc = COPY $x6
     %3:g8rc = COPY $x5
     %2:g8rc = COPY $x4
     %1:g8rc_and_g8rc_nox0 = COPY $x3
-    %11:g8rc = ANDIo8 %3, 1, implicit-def $cr0
+    %11:g8rc = ANDI8o %3, 1, implicit-def $cr0
     %6:crbitrc = COPY $cr0gt
     BCn killed %6, %bb.2
     B %bb.1
 
   bb.1:
     liveins: $x3
 
     %0:g8rc = EXTSW $x3

llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc = LI8 -11
     %2:g8rc_and_g8rc_nox0  = RLDICLo %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 32727
-    ; CHECK: ANDIo8 %0, 32727
+    ; CHECK: ANDI8o %0, 32727
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0
     %4:g8rc = ISEL8 %2, %1, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc_and_g8rc_nox0 = LI8 1
     %2:g8rc = RLDICLo %0, 32, 33, implicit-def $cr0
     ; CHECK: LI8 1
-    ; CHECK: ANDIo8 %0, 0
+    ; CHECK: ANDI8o %0, 0
     ; CHECK-LATE: li [[IMM:[0-9]+]], 1
     ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
     %3:crrc = COPY killed $cr0
     %4:g8rc = ISEL8 %0, %1, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc_and_g8rc_nox0 = LI8 -11
     %2:g8rc = RLDICLo %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 -11
-    ; CHECK: ANDIo8 %0, 65525
+    ; CHECK: ANDI8o %0, 65525
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0
     %4:g8rc = ISEL8 %0, %1, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...