[DAGCombiner] Allow zextended load combines.

[courbet]

Summary

or(zext(load8(base)), zext(load8(base+1)) -> zext(load16 base)

[courbet]

Rebase to show test diffs.

[RKSimon]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6517

NFC fix?

6748

why are you adding const? most of the time we don't bother

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

637

regression

llvm/test/CodeGen/ARM/load-combine.ll

666

regression

[courbet]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

637

Yes, that's something I meant to highlight in thsi patch, but forgot to send the comment:

I've seen in other tests for ARM we're OK paying quite a large number of instructions to avoid loads, e.g.

define i32 @load_i32_by_i8_bswap(i32* %arg) {
; BSWAP is not supported by 32 bit target
; CHECK-LABEL: load_i32_by_i8_bswap:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    ldr r0, [r0]
; CHECK-NEXT:    mov r1, #65280
; CHECK-NEXT:    mov r2, #16711680
; CHECK-NEXT:    and r1, r1, r0, lsr #8
; CHECK-NEXT:    and r2, r2, r0, lsl #8
; CHECK-NEXT:    orr r1, r1, r0, lsr #24
; CHECK-NEXT:    orr r0, r2, r0, lsl #24
; CHECK-NEXT:    orr r0, r0, r1
; CHECK-NEXT:    mov pc, lr

I'm not very familiar with these targets, where do we draw the line ?

[dmgreen]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

637

This appears to be running under a very old architecture where bswap is not legal.

Any idea why it is trying to perform this optimisation when there is no bswap to make it efficient?

[courbet]

rebase on NFC change

[courbet]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

637

// Before legalize we can introduce illegal bswaps which will be later
// converted to an explicit bswap sequence. This way we end up with a single
// load and byte shuffling instead of several loads and byte shuffling.
if (NeedsBswap && LegalOperations && !TLI.isOperationLegal(ISD::BSWAP, VT))
  return SDValue();

I can always bail out on zext:

if (NeedsBswap && (LegalOperations || NeedsZext) && !TLI.isOperationLegal(ISD::BSWAP, VT))
  return SDValue();

But it's not clear to me what's worth between a load and 4 arithmetic instructions on ARM.

[courbet]

Be conservative on ARM and do not introduce illegal BSWAPs when zero-extending.

[courbet]

When zero-extending, check the legality of the zero-extended load.

[RKSimon]

couple of minors

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

6784

Extra brackets to avoid static analyzer precedence warnings

(++ZeroExtendedBytes != (ByteWidth - static_cast<unsigned>(i)))

6789

Improve the assertion message

[courbet]

Address comments.

[dmgreen]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

637

I think:

• On any remotely modern ARM system we will have a rev instruction, so I'm not very worried about the regressions here. They do show that an architecture without bswap may get worse though, if that is a thing that comes up in other places (I think all the archs here will have a bswap of some sort).
• I think counting instructions can be as good a measure as any on some of the smaller arm devices. Maybe something like 2:1 for loads to arithmetic.
• I'm not sure why we would do this at-all if we need a bswap but don't have one. But if the VT is still an illegal type, it will likely always look illegal even if it is eventually expanded into something sane.

Can you add these two targets to the two test files:
-mtriple=thumbv6m-none-eabi
-mtriple=thumbv7m-none-eabi

If they are OK (along with the armv6 case) then I, from an ARM perspective, am happy with this.

[courbet]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

637

I think counting instructions can be as good a measure as any on some of the smaller arm devices. Maybe something like 2:1 for loads to arithmetic.

OK, so it looks like this was a real regression. So I've disabled illegal bswaps when zext-ending. Thanks for the information !

Can you add these two targets to the two test files:

Done.

[courbet]

Rebase on thumb tests.

[RKSimon]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

3–4

@dmgreen Is this a big endian triple?

[dmgreen]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

3–4

Ah, yeah. Try thumbv6meb-none-eabi and thumbv7meb-none-eabi for big endian.

[courbet]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

3–4

D'oh. Sorry about that.

[courbet]

Use the right triple for big-endian thumb.

[dmgreen]

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

3–4

Nice one.

I'm happy, if RKSimon is happy.

[RKSimon]

LGTM - cheers

[courbet]

Thanks for the review.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 
 static unsigned BigEndianByteAt(unsigned BW, unsigned i) {
   return BW - i - 1;
 }
 
 // Check if the bytes offsets we are looking at match with either big or
 // little endian value loaded. Return true for big endian, false for little
 // endian, and None if match failed.
 static Optional<bool> isBigEndian(const ArrayRef<int64_t> ByteOffsets,
                                   int64_t FirstOffset) {
   // The endian can be decided only when it is 2 bytes at least.
   unsigned Width = ByteOffsets.size();
   if (Width < 2)
     return None;
 
   bool BigEndian = true, LittleEndian = true;
   for (unsigned i = 0; i < Width; i++) {

 /// t33: i32 = or t23, t32
 /// As a possible fix visitLoad can check if the load can be a part of a load
 /// combine pattern and add corresponding OR roots to the worklist.
 SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
   assert(N->getOpcode() == ISD::OR &&
          "Can only match load combining against OR nodes");
 
   // Handles simple types only
   EVT VT = N->getValueType(0);
   if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
     return SDValue();
   unsigned ByteWidth = VT.getSizeInBits() / 8;
 
-  // Before legalize we can introduce too wide illegal loads which will be later
-  // split into legal sized loads. This enables us to combine i64 load by i8
-  // patterns to a couple of i32 loads on 32 bit targets.
-  if (LegalOperations && !TLI.isOperationLegal(ISD::LOAD, VT))
-    return SDValue();
-
   bool IsBigEndianTarget = DAG.getDataLayout().isBigEndian();
   auto MemoryByteOffset = [&] (ByteProvider P) {
     assert(P.isMemory() && "Must be a memory byte provider");
     unsigned LoadBitWidth = P.Load->getMemoryVT().getSizeInBits();
     assert(LoadBitWidth % 8 == 0 &&
            "can only analyze providers for individual bytes not bit");
     unsigned LoadByteWidth = LoadBitWidth / 8;
     return IsBigEndianTarget
             ? BigEndianByteAt(LoadByteWidth, P.ByteOffset)
             : LittleEndianByteAt(LoadByteWidth, P.ByteOffset);
   };
 
   Optional<BaseIndexOffset> Base;
   SDValue Chain;
 
   SmallPtrSet<LoadSDNode *, 8> Loads;
   Optional<ByteProvider> FirstByteProvider;
   int64_t FirstOffset = INT64_MAX;
 
   // Check if all the bytes of the OR we are looking at are loaded from the same
   // base address. Collect bytes offsets from Base address in ByteOffsets.
   SmallVector<int64_t, 8> ByteOffsets(ByteWidth);
-  for (unsigned i = 0; i < ByteWidth; i++) {
+  unsigned ZeroExtendedBytes = 0;
+  for (int i = ByteWidth - 1; i >= 0; --i) {
     auto P = calculateByteProvider(SDValue(N, 0), i, 0, /*Root=*/true);
-    if (!P || !P->isMemory()) // All the bytes must be loaded from memory
+    if (!P)
       return SDValue();
 
+    if (P->isConstantZero()) {
+      // It's OK for the N most significant bytes to be 0, we can just
+      // zero-extend the load.
+      if (++ZeroExtendedBytes != ByteWidth - static_cast<unsigned>(i))
+        return SDValue();
+      continue;
+    }
+
+    assert(P->isMemory() && "unimplemented");
+
     LoadSDNode *L = P->Load;
     assert(L->hasNUsesOfValue(1, 0) && L->isSimple() &&
            !L->isIndexed() &&
            "Must be enforced by calculateByteProvider");
     assert(L->getOffset().isUndef() && "Unindexed load must have undef offset");
 
     // All loads must share the same chain
     SDValue LChain = L->getChain();
for (int i = ByteWidth - 1; i >= 0; --i) {
 
     Loads.insert(L);
   }
   assert(!Loads.empty() && "All the bytes of the value must be loaded from "
          "memory, so there must be at least one load which produces the value");
   assert(Base && "Base address of the accessed memory location must be set");
   assert(FirstOffset != INT64_MAX && "First byte offset must be set");
 
+  bool NeedsZext = ZeroExtendedBytes > 0;
+
+  EVT MemVT =
+      EVT::getIntegerVT(*DAG.getContext(), (ByteWidth - ZeroExtendedBytes) * 8);
+
+  // Before legalize we can introduce too wide illegal loads which will be later
+  // split into legal sized loads. This enables us to combine i64 load by i8
+  // patterns to a couple of i32 loads on 32 bit targets.
+  if (LegalOperations && !TLI.isOperationLegal(ISD::LOAD, MemVT))
+    return SDValue();
+
   // Check if the bytes of the OR we are looking at match with either big or
   // little endian value load
-  Optional<bool> IsBigEndian = isBigEndian(ByteOffsets, FirstOffset);
+  Optional<bool> IsBigEndian = isBigEndian(
+      makeArrayRef(ByteOffsets).drop_back(ZeroExtendedBytes), FirstOffset);
   if (!IsBigEndian.hasValue())
     return SDValue();
 
   assert(FirstByteProvider && "must be set");
 
   // Ensure that the first byte is loaded from zero offset of the first load.
   // So the combined value can be loaded from the first load address.
   if (MemoryByteOffset(*FirstByteProvider) != 0)
     return SDValue();
   LoadSDNode *FirstLoad = FirstByteProvider->Load;
 
   // The node we are looking at matches with the pattern, check if we can
-  // replace it with a single load and bswap if needed.
+  // replace it with a single (possibly zero-extended) load and bswap + shift if
+  // needed.
 
   // If the load needs byte swap check if the target supports it
   bool NeedsBswap = IsBigEndianTarget != *IsBigEndian;
 
   // Before legalize we can introduce illegal bswaps which will be later
   // converted to an explicit bswap sequence. This way we end up with a single
   // load and byte shuffling instead of several loads and byte shuffling.
   if (NeedsBswap && LegalOperations && !TLI.isOperationLegal(ISD::BSWAP, VT))
     return SDValue();
 
+  // If we need to bswap and zero extend, we have to insert a shift. Check that
+  // it is legal.
+  if (NeedsBswap && NeedsZext && LegalOperations &&
+      !TLI.isOperationLegal(ISD::SHL, VT))
+    return SDValue();
+
   // Check that a load of the wide type is both allowed and fast on the target
   bool Fast = false;
-  bool Allowed = TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
-                                        VT, *FirstLoad->getMemOperand(), &Fast);
+  bool Allowed = TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
+                                        *FirstLoad->getMemOperand(), &Fast);
   if (!Allowed || !Fast)
     return SDValue();
 
-  SDValue NewLoad =
-      DAG.getLoad(VT, SDLoc(N), Chain, FirstLoad->getBasePtr(),
-                  FirstLoad->getPointerInfo(), FirstLoad->getAlignment());
+  SDValue NewLoad = DAG.getExtLoad(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD,
+                                   SDLoc(N), VT, Chain, FirstLoad->getBasePtr(),
+                                   FirstLoad->getPointerInfo(), MemVT,
+                                   FirstLoad->getAlignment());
 
   // Transfer chain users from old loads to the new load.
   for (LoadSDNode *L : Loads)
     DAG.ReplaceAllUsesOfValueWith(SDValue(L, 1), SDValue(NewLoad.getNode(), 1));
 
-  return NeedsBswap ? DAG.getNode(ISD::BSWAP, SDLoc(N), VT, NewLoad) : NewLoad;
+  if (!NeedsBswap)
+    return NewLoad;
+
+  SDValue ShiftedLoad =
+      NeedsZext
+          ? DAG.getNode(ISD::SHL, SDLoc(N), VT, NewLoad,
+                        DAG.getShiftAmountConstant(ZeroExtendedBytes * 8, VT,
+                                                   SDLoc(N), LegalOperations))
+          : NewLoad;
+  return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, ShiftedLoad);
 }
 
 // If the target has andn, bsl, or a similar bit-select instruction,
 // we want to unfold masked merge, with canonical pattern of:
 //   |        A  |  |B|
 //   ((x ^ y) & m) ^ y
 //    |  D  |
 // Into:

llvm/test/CodeGen/AArch64/load-combine-big-endian.ll

; CHECK-NEXT:    ret
   %tmp48 = or i32 %tmp42, %tmp47
   ret i32 %tmp48
 }
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[0] | ((i32) p[1] << 8)
 define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrb w8, [x0]
-; CHECK-NEXT:    ldrb w9, [x0, #1]
-; CHECK-NEXT:    bfi w8, w9, #8, #8
-; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    lsl w8, w8, #16
+; CHECK-NEXT:    rev w0, w8
 ; CHECK-NEXT:    ret
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 2
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp5 = load i8, i8* %tmp4, align 1
; CHECK-NEXT:    ret
   %tmp8 = or i32 %tmp7, %tmp30
   ret i32 %tmp8
 }
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[1] | ((i32) p[0] << 8)
 define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrb w8, [x0, #1]
-; CHECK-NEXT:    ldrb w9, [x0]
-; CHECK-NEXT:    bfi w8, w9, #8, #8
-; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ldrh w0, [x0]
 ; CHECK-NEXT:    ret
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp5 = load i8, i8* %tmp4, align 2

llvm/test/CodeGen/AArch64/load-combine.ll

; CHECK-NEXT:    ret
   ret i32 %tmp48
 }
 
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[0] | ((i32) p[1] << 8)
 define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrb w8, [x0]
-; CHECK-NEXT:    ldrb w9, [x0, #1]
-; CHECK-NEXT:    bfi w8, w9, #8, #8
-; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ldrh w0, [x0]
 ; CHECK-NEXT:    ret
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 2
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp5 = load i8, i8* %tmp4, align 1
; CHECK-NEXT:    ret
   %tmp8 = or i32 %tmp7, %tmp30
   ret i32 %tmp8
 }
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[1] | ((i32) p[0] << 8)
 define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldrb w8, [x0, #1]
-; CHECK-NEXT:    ldrb w9, [x0]
-; CHECK-NEXT:    bfi w8, w9, #8, #8
-; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ldrh w8, [x0]
+; CHECK-NEXT:    lsl w8, w8, #16
+; CHECK-NEXT:    rev w0, w8
 ; CHECK-NEXT:    ret
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp5 = load i8, i8* %tmp4, align 2

llvm/test/CodeGen/ARM/load-combine-big-endian.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=armeb-unknown | FileCheck %s
 ; RUN: llc < %s -mtriple=armv6eb-unknown | FileCheck %s --check-prefix=CHECK-ARMv6
 
 ; i8* p; // p is 4 byte aligned
 ; ((i32) p[0] << 24) | ((i32) p[1] << 16) | ((i32) p[2] << 8) | (i32) p[3]
 define i32 @load_i32_by_i8_big_endian(i32* %arg) {
 ; CHECK-LABEL: load_i32_by_i8_big_endian:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    ldr r0, [r0]
 ; CHECK-NEXT:    mov pc, lr
 ;
; CHECK-ARMv6-NEXT:    bx lr
   ret i32 %tmp48
 }
 
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[0] | ((i32) p[1] << 8)
 define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    ldrb r1, [r0]
-; CHECK-NEXT:    ldrb r0, [r0, #1]
-; CHECK-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-NEXT:    ldrh r0, [r0]
+; CHECK-NEXT:    mov r1, #255
+; CHECK-NEXT:    orr r1, r1, #65280
+; CHECK-NEXT:    and r1, r1, r0, lsl #8
+; CHECK-NEXT:    lsl r0, r0, #16
+; CHECK-NEXT:    orr r0, r1, r0, lsr #24
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
 ; CHECK-ARMv6:       @ %bb.0:
-; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
-; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-ARMv6-NEXT:    ldrh r0, [r0]
+; CHECK-ARMv6-NEXT:    lsl r0, r0, #16
+; CHECK-ARMv6-NEXT:    rev r0, r0
 ; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 2
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp5 = load i8, i8* %tmp4, align 1
; CHECK-ARMv6-NEXT:    bx lr
   ret i32 %tmp8
 }
 
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[1] | ((i32) p[0] << 8)
 define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    ldrb r1, [r0]
-; CHECK-NEXT:    ldrb r0, [r0, #1]
-; CHECK-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-NEXT:    ldrh r0, [r0]
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK-ARMv6:       @ %bb.0:
-; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
-; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-ARMv6-NEXT:    ldrh r0, [r0]
 ; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp5 = load i8, i8* %tmp4, align 2

llvm/test/CodeGen/ARM/load-combine.ll

; CHECK-ARMv6-NEXT:    bx lr
   ret i32 %tmp48
 }
 
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[0] | ((i32) p[1] << 8)
 define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    ldrb r1, [r0]
-; CHECK-NEXT:    ldrb r0, [r0, #1]
-; CHECK-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-NEXT:    ldrh r0, [r0]
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8:
 ; CHECK-ARMv6:       @ %bb.0:
-; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
-; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT:    orr r0, r1, r0, lsl #8
+; CHECK-ARMv6-NEXT:    ldrh r0, [r0]
 ; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 2
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp5 = load i8, i8* %tmp4, align 1
; CHECK-ARMv6-NEXT:    bx lr
   ret i32 %tmp8
 }
 
 ; i8* p; // p is 2 byte aligned
 ; (i32) p[1] | ((i32) p[0] << 8)
 define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    ldrb r1, [r0]
-; CHECK-NEXT:    ldrb r0, [r0, #1]
-; CHECK-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-NEXT:    ldrh r0, [r0]
+; CHECK-NEXT:    mov r1, #255
+; CHECK-NEXT:    orr r1, r1, #65280
+; CHECK-NEXT:    and r1, r1, r0, lsl #8
+; CHECK-NEXT:    lsl r0, r0, #16
+; CHECK-NEXT:    orr r0, r1, r0, lsr #24
 ; CHECK-NEXT:    mov pc, lr
 ;
 ; CHECK-ARMv6-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK-ARMv6:       @ %bb.0:
-; CHECK-ARMv6-NEXT:    ldrb r1, [r0]
-; CHECK-ARMv6-NEXT:    ldrb r0, [r0, #1]
-; CHECK-ARMv6-NEXT:    orr r0, r0, r1, lsl #8
+; CHECK-ARMv6-NEXT:    ldrh r0, [r0]
+; CHECK-ARMv6-NEXT:    lsl r0, r0, #16
+; CHECK-ARMv6-NEXT:    rev r0, r0
 ; CHECK-ARMv6-NEXT:    bx lr
 
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp5 = load i8, i8* %tmp4, align 2

llvm/test/CodeGen/X86/load-combine.ll

 }
 
 ; i8* p;
 ; (i32) p[0] | ((i32) p[1] << 8)
 define i32 @zext_load_i32_by_i8(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movzbl (%eax), %ecx
-; CHECK-NEXT:    movzbl 1(%eax), %eax
-; CHECK-NEXT:    shll $8, %eax
-; CHECK-NEXT:    orl %ecx, %eax
+; CHECK-NEXT:    movzwl (%eax), %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: zext_load_i32_by_i8:
 ; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    movzbl (%rdi), %ecx
-; CHECK64-NEXT:    movzbl 1(%rdi), %eax
-; CHECK64-NEXT:    shll $8, %eax
-; CHECK64-NEXT:    orl %ecx, %eax
+; CHECK64-NEXT:    movzwl (%rdi), %eax
 ; CHECK64-NEXT:    retq
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp5 = load i8, i8* %tmp4, align 1
   %tmp6 = zext i8 %tmp5 to i32

 }
 
 ; i8* p;
 ; (i32) p[1] | ((i32) p[0] << 8)
 define i32 @zext_load_i32_by_i8_bswap(i32* %arg) {
 ; CHECK-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movzbl 1(%eax), %ecx
-; CHECK-NEXT:    movzbl (%eax), %eax
-; CHECK-NEXT:    shll $8, %eax
-; CHECK-NEXT:    orl %ecx, %eax
+; CHECK-NEXT:    movzwl (%eax), %eax
+; CHECK-NEXT:    shll $16, %eax
+; CHECK-NEXT:    bswapl %eax
 ; CHECK-NEXT:    retl
 ;
 ; CHECK64-LABEL: zext_load_i32_by_i8_bswap:
 ; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    movzbl 1(%rdi), %ecx
-; CHECK64-NEXT:    movzbl (%rdi), %eax
-; CHECK64-NEXT:    shll $8, %eax
-; CHECK64-NEXT:    orl %ecx, %eax
+; CHECK64-NEXT:    movzwl (%rdi), %eax
+; CHECK64-NEXT:    shll $16, %eax
+; CHECK64-NEXT:    bswapl %eax
 ; CHECK64-NEXT:    retq
   %tmp = bitcast i32* %arg to i8*
   %tmp1 = getelementptr inbounds i8, i8* %tmp, i32 1
   %tmp2 = load i8, i8* %tmp1, align 1
   %tmp3 = zext i8 %tmp2 to i32
   %tmp4 = getelementptr inbounds i8, i8* %tmp, i32 0
   %tmp5 = load i8, i8* %tmp4, align 1
   %tmp6 = zext i8 %tmp5 to i32