[ARM][MVE] Add invalidForTailPredication to TSFlags

[samparker]

Summary

Set this bit for the MVE reduction instructions to prevent a loop from becoming tail predicated in their presence.

[SjoerdMeijer]

At this point I am not sure if we should "pollute" the generic MC description with this property, mainly because the ARM backend will be the only user, and it looks like this could be simple target hook switching over the opcodes, like already done in the added unittest. Not pretty, but very simple and effective....
At the same time, there is enough prior art here, adding all sorts of things, so I am in two minds. But I think I would more lean towards a target hook, because it's not very generic/widely used.

Adding @MatzeB as a reviewer, who had some opinions on this in past if I remember that well.

[samtebbs]

In D67444#1667873, @SjoerdMeijer wrote:

At this point I am not sure if we should "pollute" the generic MC description with this property, mainly because the ARM backend will be the only user, and it looks like this could be simple target hook switching over the opcodes, like already done in the added unittest. Not pretty, but very simple and effective....
At the same time, there is enough prior art here, adding all sorts of things, so I am in two minds. But I think I would more lean towards a target hook, because it's not very generic/widely used.

I agree that this could be implemented solely in the backend. The problem I see, however, is what happens when adding new reduction instructions, as someone adding a new tablegen def won't know to add it to where these instructions are checked. Adding the flag to tablegen makes it easier to spot and add.

[SjoerdMeijer]

I agree that this could be implemented solely in the backend. The problem I see, however, is what happens when adding new reduction instructions, as someone adding a new tablegen def won't know to add it to where these instructions are checked. Adding the flag to tablegen makes it easier to spot and add.

Yes, I see that...but designing things for the future that may or may not happen at all is a bit tricky. As it's such a simple opcode check, I don't see why we should make things more complicated now for a thing that may never happen. And if it happens, it's not that we need to do a complete redesign of a tricky bit of logic. If it happens, then it will be pretty obvious from the codegen that new opcodes were not added to the TTI->isMVEReductionStmt hook, and then a decision can be made I guess.

[samparker]

Is there a way of writing to the TSFlags, of MCInstrDesc, via tablegen? Then we can get the nice markup and not have it affect the general flags. We could also do this later for our truncate and extend instructions too...

[SjoerdMeijer]

+1 to that.

[samtebbs]

+1 :)

[samparker]

Ported to TSFlags. Removed and added opcode to the test.

[SjoerdMeijer]

Nice one.

Bikeshedding: wondering if invalidForTailPredication is the same as not VPT Block Compatible, the term used in the ARM ARM....

[samparker]

They are different things. I actually don't think that the specification prevents any instructions from being in a TP loop, we just need to be careful of these. We should be able to allow most (all?) of these once we implement some better checks in the backend to look at the operands.

[SjoerdMeijer]

They are different things. I actually don't think that the specification prevents any instructions from being in a TP loop, we just need to be careful of these. We should be able to allow most (all?) of these once we implement some better checks in the backend to look at the operands.

Thanks, make sense, agreed.

unittests/Target/ARM/MachineInstrTest.cpp

16 ↗

(On Diff #220305)

Does this TODO mean we are currently allowing instructions that should not be allowed? If so, is that a problem?

164 ↗

(On Diff #220305)

Perhaps the message can be a little bit more informative what exactly is wrong here.

[samparker]

unittests/Target/ARM/MachineInstrTest.cpp

16 ↗

(On Diff #220305)

We're not generating any TP loops yet, so we're okay! The approach will be to all the suspicious instructions here first so we don't have to test all of them when we finally implement the last part of predication.

[SjoerdMeijer]

We're not generating any TP loops yet, so we're okay!

yes, that's true..... :-)

The approach will be to all the suspicious instructions here first so we don't have to test all of them when we finally implement the last part of predication.

but okay, that sounds like a little plan.

This looks good to me.

[samparker]

Improved error message.

[danilaml]

llvm/trunk/unittests/Target/ARM/CMakeLists.txt

2 ↗

(On Diff #220440)

Perhaps those need to be ${LLVM_MAIN_SRC_DIR} and ${LLVM_BINARY_DIR}, in case top-level CMake is in not in the llvm dir?

llvm/include/llvm/MC/MCInstrDesc.h

enum Flag {
   ExtraDefRegAllocReq,
   RegSequence,
   ExtractSubreg,
   InsertSubreg,
   Convergent,
   Add,
   Trap,
   VariadicOpsAreDefs,
+  VectorReduction,
 };
 }
 
 /// Describe properties that are true of each instruction in the target
 /// description file.  This captures information about side effects, register
 /// use and many other things.  There is one instance of this struct for each
 /// target instruction class, and the MachineInstr class points to this struct
 /// directly to describe itself.
public:
   /// Return true if this is a branch which always
   /// transfers control flow to some other block.  The
   /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
   /// about this branch.
   bool isUnconditionalBranch() const {
     return isBranch() & isBarrier() & !isIndirectBranch();
   }
 
+  bool isVectorReduction() const {
+    return Flags & (1ULL << MCID::VectorReduction);
+  }
+
   /// Return true if this is a branch or an instruction which directly
   /// writes to the program counter. Considered 'may' affect rather than
   /// 'does' affect as things like predication are not taken into account.
   bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const;
 
   /// Return true if this instruction has a predicate operand
   /// that controls execution. It may be set to 'always', or may be set to other
   /// values. There are various methods in TargetInstrInfo that can be used to

llvm/include/llvm/Target/Target.td

class Instruction : InstructionEncoding {
   bit isCompare    = 0;     // Is this instruction a comparison instruction?
   bit isMoveImm    = 0;     // Is this instruction a move immediate instruction?
   bit isMoveReg    = 0;     // Is this instruction a move register instruction?
   bit isBitcast    = 0;     // Is this instruction a bitcast instruction?
   bit isSelect     = 0;     // Is this instruction a select instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit isAdd        = 0;     // Is this instruction an add instruction?
+  bit isVectorReduction = 0;
   bit isTrap       = 0;     // Is this instruction a trap instruction?
   bit canFoldAsLoad = 0;    // Can this be folded as a simple memory operand?
   bit mayLoad      = ?;     // Is it possible for this inst to read memory?
   bit mayStore     = ?;     // Is it possible for this inst to write memory?
   bit mayRaiseFPException = 0; // Can this raise a floating-point exception?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VABAV<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   let Inst{16} = 0b0;
   let Inst{15-12} = Rda{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
+
+  let isVectorReduction = 1;
 }
 
 def MVE_VABAVs8  : MVE_VABAV<"s8", 0b0, 0b00>;
 def MVE_VABAVs16 : MVE_VABAV<"s16", 0b0, 0b01>;
 def MVE_VABAVs32 : MVE_VABAV<"s32", 0b0, 0b10>;
 def MVE_VABAVu8  : MVE_VABAV<"u8", 0b1, 0b00>;
 def MVE_VABAVu16 : MVE_VABAV<"u16", 0b1, 0b01>;
 def MVE_VABAVu32 : MVE_VABAV<"u32", 0b1, 0b10>;
class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
   let Inst{19-18} = size{1-0};
   let Inst{17-16} = 0b01;
   let Inst{15-13} = Rda{3-1};
   let Inst{12} = 0b0;
   let Inst{8-6} = 0b100;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VADDV_A<string suffix, bit U, bits<2> size,
                        list<dag> pattern=[]> {
   def acc    : MVE_VADDV<"vaddva", suffix,
                          (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
                          0b1, U, size, pattern>;
   def no_acc : MVE_VADDV<"vaddv", suffix,
class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
   let Inst{19-18} = 0b10;
   let Inst{17-16} = 0b01;
   let Inst{15-13} = RdaLo{3-1};
   let Inst{12} = 0b0;
   let Inst{8-6} = 0b100;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
   def acc    : MVE_VADDLV<"vaddlva", suffix,
                         (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, MQPR:$Qm),
                         "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
                         0b1, U, pattern>;
   def no_acc : MVE_VADDLV<"vaddlv", suffix,
class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
   let Inst{15-12} = RdaDest{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = bit_7;
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
 
   let Predicates = [HasMVEFloat];
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMINMAXNMV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
   def f32 : MVE_VMINMAXNMV<iname, "f32", 0b0, 0b1, bit_7, pattern>;
   def f16 : MVE_VMINMAXNMV<iname, "f16", 0b1, 0b1, bit_7, pattern>;
 }
 
 defm MVE_VMINNMV : MVE_VMINMAXNMV_fty<"vminnmv", 0b1>;
class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
   let Inst{17} = bit_17;
   let Inst{16} = 0b0;
   let Inst{15-12} = RdaDest{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = bit_7;
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMINMAXV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
   def s8  : MVE_VMINMAXV<iname, "s8",  0b0, 0b00, 0b1, bit_7>;
   def s16 : MVE_VMINMAXV<iname, "s16", 0b0, 0b01, 0b1, bit_7>;
   def s32 : MVE_VMINMAXV<iname, "s32", 0b0, 0b10, 0b1, bit_7>;
   def u8  : MVE_VMINMAXV<iname, "u8",  0b1, 0b00, 0b1, bit_7>;
   def u16 : MVE_VMINMAXV<iname, "u16", 0b1, 0b01, 0b1, bit_7>;
class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
   let Inst{16} = sz;
   let Inst{15-13} = RdaDest{3-1};
   let Inst{12} = X;
   let Inst{8} = bit_8;
   let Inst{7-6} = 0b00;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMLAMLSDAV_X<string iname, string suffix, dag iops, string cstr,
                           bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
                           list<dag> pattern=[]> {
   def _noexch : MVE_VMLAMLSDAV<iname, suffix, iops, cstr, sz,
                             bit_28, A, 0b0, bit_8, bit_0, pattern>;
   def _exch   : MVE_VMLAMLSDAV<iname # "x", suffix, iops, cstr, sz,
class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
   let Inst{16} = sz;
   let Inst{15-13} = RdaLoDest{3-1};
   let Inst{12} = X;
   let Inst{8} = bit_8;
   let Inst{7-6} = 0b00;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
+
+  let isVectorReduction = 1;
 }
 
 multiclass MVE_VMLALDAVBase_X<string iname, string suffix, dag iops,
                               string cstr, bit sz, bit bit_28, bit A,
                               bit bit_8, bit bit_0, list<dag> pattern=[]> {
   def _noexch : MVE_VMLALDAVBase<iname, suffix, iops, cstr, sz,
                                bit_28, A, 0b0, bit_8, bit_0, pattern>;
   def _exch   : MVE_VMLALDAVBase<iname # "x", suffix, iops, cstr, sz,

llvm/unittests/Target/ARM/CMakeLists.txt

+include_directories(
+  ${CMAKE_SOURCE_DIR}/lib/Target/ARM
+  ${CMAKE_BINARY_DIR}/lib/Target/ARM
+  )
+
+set(LLVM_LINK_COMPONENTS
+  ${LLVM_TARGETS_TO_BUILD}
+  Analysis
+  AsmParser
+  AsmPrinter
+  ARMCodeGen
+  ARMDesc
+  ARMInfo
+  CodeGen
+  Core
+  MC
+  MIRParser
+  SelectionDAG
+  Support
+  Target
+  )
+
+add_llvm_unittest(ARMTests
+  MachineInstrTest.cpp
+  )

llvm/unittests/Target/ARM/MachineInstrTest.cpp

+#include "ARMBaseInstrInfo.h"
+#include "ARMSubtarget.h"
+#include "ARMTargetMachine.h"
+#include "llvm/CodeGen/MIRParser/MIRParser.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+TEST(MachineInstrVecReductionFlag, IsCorrect) {
+  Triple TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
+  std::string Error;
+
+  LLVMInitializeARMTargetInfo();
+  LLVMInitializeARMTarget();
+  LLVMInitializeARMTargetMC();
+
+  const Target *T = TargetRegistry::lookupTarget("", TT, Error);
+  if (!T) {
+    dbgs() << Error;
+    return;
+  }
+
+  TargetOptions Options;
+  TargetMachine *TM = T->createTargetMachine("Thumb2", "", "", Options, None,
+                                             None, CodeGenOpt::Aggressive);
+  auto MII = TM->getMCInstrInfo();
+
+  auto IsVecReductionOpcode = [](unsigned Opcode) {
+    switch (Opcode) {
+    case ARM::MVE_VABAVs8:
+    case ARM::MVE_VABAVs16:
+    case ARM::MVE_VABAVs32:
+    case ARM::MVE_VABAVu8:
+    case ARM::MVE_VABAVu16:
+    case ARM::MVE_VABAVu32:
+    case ARM::MVE_VADDVs8acc:
+    case ARM::MVE_VADDVs16acc:
+    case ARM::MVE_VADDVs32acc:
+    case ARM::MVE_VADDVu8acc:
+    case ARM::MVE_VADDVu16acc:
+    case ARM::MVE_VADDVu32acc:
+    case ARM::MVE_VADDVs8no_acc:
+    case ARM::MVE_VADDVs16no_acc:
+    case ARM::MVE_VADDVs32no_acc:
+    case ARM::MVE_VADDVu8no_acc:
+    case ARM::MVE_VADDVu16no_acc:
+    case ARM::MVE_VADDVu32no_acc:
+    case ARM::MVE_VADDLVs32no_acc:
+    case ARM::MVE_VADDLVu32no_acc:
+    case ARM::MVE_VADDLVs32acc:
+    case ARM::MVE_VADDLVu32acc:
+    case ARM::MVE_VMAXNMVf16:
+    case ARM::MVE_VMINNMVf16:
+    case ARM::MVE_VMAXNMVf32:
+    case ARM::MVE_VMINNMVf32:
+    case ARM::MVE_VMAXNMAVf16:
+    case ARM::MVE_VMINNMAVf16:
+    case ARM::MVE_VMAXNMAVf32:
+    case ARM::MVE_VMINNMAVf32:
+    case ARM::MVE_VMAXVs8:
+    case ARM::MVE_VMAXVs16:
+    case ARM::MVE_VMAXVs32:
+    case ARM::MVE_VMAXVu8:
+    case ARM::MVE_VMAXVu16:
+    case ARM::MVE_VMAXVu32:
+    case ARM::MVE_VMINVs8:
+    case ARM::MVE_VMINVs16:
+    case ARM::MVE_VMINVs32:
+    case ARM::MVE_VMINVu8:
+    case ARM::MVE_VMINVu16:
+    case ARM::MVE_VMINVu32:
+    case ARM::MVE_VMAXAVs8:
+    case ARM::MVE_VMAXAVs16:
+    case ARM::MVE_VMAXAVs32:
+    case ARM::MVE_VMINAVs8:
+    case ARM::MVE_VMINAVs16:
+    case ARM::MVE_VMINAVs32:
+    case ARM::MVE_VMLADAVs8_noacc_noexch:
+    case ARM::MVE_VMLADAVs16_noacc_noexch:
+    case ARM::MVE_VMLADAVs32_noacc_noexch:
+    case ARM::MVE_VMLADAVu8_noacc_noexch:
+    case ARM::MVE_VMLADAVu16_noacc_noexch:
+    case ARM::MVE_VMLADAVu32_noacc_noexch:
+    case ARM::MVE_VMLADAVs8_acc_noexch:
+    case ARM::MVE_VMLADAVs16_acc_noexch:
+    case ARM::MVE_VMLADAVs32_acc_noexch:
+    case ARM::MVE_VMLADAVu8_acc_noexch:
+    case ARM::MVE_VMLADAVu16_acc_noexch:
+    case ARM::MVE_VMLADAVu32_acc_noexch:
+    case ARM::MVE_VMLADAVs8_noacc_exch:
+    case ARM::MVE_VMLADAVs16_noacc_exch:
+    case ARM::MVE_VMLADAVs32_noacc_exch:
+    case ARM::MVE_VMLADAVu8_noacc_exch:
+    case ARM::MVE_VMLADAVu16_noacc_exch:
+    case ARM::MVE_VMLADAVu32_noacc_exch:
+    case ARM::MVE_VMLADAVs8_acc_exch:
+    case ARM::MVE_VMLADAVs16_acc_exch:
+    case ARM::MVE_VMLADAVs32_acc_exch:
+    case ARM::MVE_VMLADAVu8_acc_exch:
+    case ARM::MVE_VMLADAVu16_acc_exch:
+    case ARM::MVE_VMLADAVu32_acc_exch:
+    case ARM::MVE_VMLALDAVs16_noacc_noexch:
+    case ARM::MVE_VMLALDAVs32_noacc_noexch:
+    case ARM::MVE_VMLALDAVu16_noacc_noexch:
+    case ARM::MVE_VMLALDAVu32_noacc_noexch:
+    case ARM::MVE_VMLALDAVs16_acc_noexch:
+    case ARM::MVE_VMLALDAVs32_acc_noexch:
+    case ARM::MVE_VMLALDAVu16_acc_noexch:
+    case ARM::MVE_VMLALDAVu32_acc_noexch:
+    case ARM::MVE_VMLALDAVs16_noacc_exch:
+    case ARM::MVE_VMLALDAVs32_noacc_exch:
+    case ARM::MVE_VMLALDAVu16_noacc_exch:
+    case ARM::MVE_VMLALDAVu32_noacc_exch:
+    case ARM::MVE_VMLALDAVs16_acc_exch:
+    case ARM::MVE_VMLALDAVs32_acc_exch:
+    case ARM::MVE_VMLALDAVu16_acc_exch:
+    case ARM::MVE_VMLALDAVu32_acc_exch:
+    case ARM::MVE_VMLSDAVs8_noacc_noexch:
+    case ARM::MVE_VMLSDAVs16_noacc_noexch:
+    case ARM::MVE_VMLSDAVs32_noacc_noexch:
+    case ARM::MVE_VMLSDAVs8_acc_noexch:
+    case ARM::MVE_VMLSDAVs16_acc_noexch:
+    case ARM::MVE_VMLSDAVs32_acc_noexch:
+    case ARM::MVE_VMLSDAVs8_noacc_exch:
+    case ARM::MVE_VMLSDAVs16_noacc_exch:
+    case ARM::MVE_VMLSDAVs32_noacc_exch:
+    case ARM::MVE_VMLSDAVs8_acc_exch:
+    case ARM::MVE_VMLSDAVs16_acc_exch:
+    case ARM::MVE_VMLSDAVs32_acc_exch:
+    case ARM::MVE_VMLSLDAVs16_noacc_noexch:
+    case ARM::MVE_VMLSLDAVs32_noacc_noexch:
+    case ARM::MVE_VMLSLDAVs16_acc_noexch:
+    case ARM::MVE_VMLSLDAVs32_acc_noexch:
+    case ARM::MVE_VMLSLDAVs16_noacc_exch:
+    case ARM::MVE_VMLSLDAVs32_noacc_exch:
+    case ARM::MVE_VMLSLDAVs16_acc_exch:
+    case ARM::MVE_VMLSLDAVs32_acc_exch:
+    case ARM::MVE_VRMLALDAVHs32_noacc_noexch:
+    case ARM::MVE_VRMLALDAVHs32_acc_noexch:
+    case ARM::MVE_VRMLALDAVHs32_noacc_exch:
+    case ARM::MVE_VRMLALDAVHs32_acc_exch:
+    case ARM::MVE_VRMLALDAVHu32_noacc_noexch:
+    case ARM::MVE_VRMLALDAVHu32_acc_noexch:
+    case ARM::MVE_VRMLALDAVHu32_noacc_exch:
+    case ARM::MVE_VRMLALDAVHu32_acc_exch:
+    case ARM::MVE_VRMLSLDAVHs32_noacc_noexch:
+    case ARM::MVE_VRMLSLDAVHs32_acc_noexch:
+    case ARM::MVE_VRMLSLDAVHs32_noacc_exch:
+    case ARM::MVE_VRMLSLDAVHs32_acc_exch:
+      return true;
+    default:
+      return false;
+    }
+  };
+
+  unsigned i = 0;
+  while (i < ARM::INSTRUCTION_LIST_END) {
+    ASSERT_EQ(IsVecReductionOpcode(i), MII->get(i).isVectorReduction())
+        << MII->getName(i)
+        << " has the wrong isVectorReduction flag value or should be added to "
+           "this test's list of vector reductions\n";
+    i++;
+  }
+}

llvm/utils/TableGen/CodeGenInstruction.h

public:
     bool isCompare : 1;
     bool isMoveImm : 1;
     bool isMoveReg : 1;
     bool isBitcast : 1;
     bool isSelect : 1;
     bool isBarrier : 1;
     bool isCall : 1;
     bool isAdd : 1;
+    bool isVectorReduction : 1;
     bool isTrap : 1;
     bool canFoldAsLoad : 1;
     bool mayLoad : 1;
     bool mayLoad_Unset : 1;
     bool mayStore : 1;
     bool mayStore_Unset : 1;
     bool mayRaiseFPException : 1;
     bool isPredicable : 1;

llvm/utils/TableGen/CodeGenInstruction.cpp

CodeGenInstruction::CodeGenInstruction(Record *R)
   isCompare    = R->getValueAsBit("isCompare");
   isMoveImm    = R->getValueAsBit("isMoveImm");
   isMoveReg    = R->getValueAsBit("isMoveReg");
   isBitcast    = R->getValueAsBit("isBitcast");
   isSelect     = R->getValueAsBit("isSelect");
   isBarrier    = R->getValueAsBit("isBarrier");
   isCall       = R->getValueAsBit("isCall");
   isAdd        = R->getValueAsBit("isAdd");
+  isVectorReduction = R->getValueAsBit("isVectorReduction");
   isTrap       = R->getValueAsBit("isTrap");
   canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
   isPredicable = !R->getValueAsBit("isUnpredicable") && (
       Operands.isPredicable || R->getValueAsBit("isPredicable"));
   isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
   isCommutable = R->getValueAsBit("isCommutable");
   isTerminator = R->getValueAsBit("isTerminator");
   isReMaterializable = R->getValueAsBit("isReMaterializable");

llvm/utils/TableGen/InstrDocsEmitter.cpp

#define FLAG(f) if (II->f) { FlagStrings.push_back(str(f)); }
     FLAG(isIndirectBranch)
     FLAG(isCompare)
     FLAG(isMoveImm)
     FLAG(isBitcast)
     FLAG(isSelect)
     FLAG(isBarrier)
     FLAG(isCall)
     FLAG(isAdd)
+    FLAG(isVectorReduction)
     FLAG(isTrap)
     FLAG(canFoldAsLoad)
     FLAG(mayLoad)
     //FLAG(mayLoad_Unset) // Deliberately omitted.
     FLAG(mayStore)
     //FLAG(mayStore_Unset) // Deliberately omitted.
     FLAG(isPredicable)
     FLAG(isConvertibleToThreeAddress)

llvm/utils/TableGen/InstrInfoEmitter.cpp

void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isEHScopeReturn)    OS << "|(1ULL<<MCID::EHScopeReturn)";
   if (Inst.isBranch)           OS << "|(1ULL<<MCID::Branch)";
   if (Inst.isIndirectBranch)   OS << "|(1ULL<<MCID::IndirectBranch)";
   if (Inst.isCompare)          OS << "|(1ULL<<MCID::Compare)";
   if (Inst.isMoveImm)          OS << "|(1ULL<<MCID::MoveImm)";
   if (Inst.isMoveReg)          OS << "|(1ULL<<MCID::MoveReg)";
   if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
   if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
+  if (Inst.isVectorReduction)  OS << "|(1ULL<<MCID::VectorReduction)";
   if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
   if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
   if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
   if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";