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Differential D66004

[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support
ClosedPublic

Authored by RKSimon on Aug 9 2019, 4:13 AM.

Details

Reviewers
craig.topper
spatel
andreadb
lebedev.ri
Commits
rG21d02dc59579: [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle…
Summary

This patch uses partial DemandedElts masks to further simplify target shuffle chains and finally starts making target shuffle combining part of SimplifyDemandedBits/SimplifyDemandedVectorElts.

We already manage this for Depth == 0 cases, where combineX86ShuffleChain would early-out if the shuffle combined to the same op, but the patch generalizes this by manipulating the depth handling of combineX86ShufflesRecursively - calling with a new Depth = 0 and reducing the maximum shuffle combine depth accordingly.

Diff Detail

Event Timeline

RKSimon created this revision.Aug 9 2019, 4:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 9 2019, 4:13 AM
RKSimon mentioned this in D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE.Aug 12 2019, 4:18 AM
RKSimon mentioned this in rL368307: [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using….Aug 16 2019, 7:55 AM
xbolva00 added a subscriber: xbolva00.Aug 27 2019, 1:55 PM

Can this patch solve bad codegen for 'f5'?

https://godbolt.org/z/3YpVg-

craig.topper added a comment.Aug 27 2019, 2:29 PM
In D66004#1647773, @xbolva00 wrote:

Can this patch solve bad codegen for 'f5'?

https://godbolt.org/z/3YpVg-

I don't think any amount of shuffle combining is going to recover that. I think we need to look at lowerShuffleAsLanePermuteAndRepeatedMask

craig.topper added a comment.Aug 27 2019, 3:02 PM
In D66004#1647822, @craig.topper wrote:
In D66004#1647773, @xbolva00 wrote:

Can this patch solve bad codegen for 'f5'?

https://godbolt.org/z/3YpVg-

I don't think any amount of shuffle combining is going to recover that. I think we need to look at lowerShuffleAsLanePermuteAndRepeatedMask

Nevermind, that won't fix it. The two lanes have different controls for the shufpd in gcc's code. I think we need a new strategy.

xbolva00 added a comment.Aug 29 2019, 3:01 AM

They improved f1 and f2 cases to save one instruction wrt LLVM’s codegen

https://gcc.gnu.org/ml/gcc-patches/2019-08/msg01952.html

RKSimon mentioned this in rL370613: [X86][AVX] Rename + cleanup lowerShuffleAsLanePermuteAndBlend. NFCI..Sep 1 2019, 9:05 AM
RKSimon mentioned this in rG07de5292e5cf: [X86][AVX] Rename + cleanup lowerShuffleAsLanePermuteAndBlend. NFCI..
RKSimon mentioned this in rL371314: [X86][AVX] Add 'f5' v4f64 shuffle test mentioned in D66004.Sep 7 2019, 9:12 AM
RKSimon mentioned this in rG31c98abda3f9: [X86][AVX] Add 'f5' v4f64 shuffle test mentioned in D66004.
lebedev.ri added a comment.Oct 11 2019, 2:08 AM

Rebase this?

RKSimon planned changes to this revision.Oct 12 2019, 8:18 AM

WIP - PR27854 and PR43024 need to be finished first.

RKSimon mentioned this in rG9f0885d38d82: [X86][SSE] Avoid unnecessary PMOVZX in v4i8 sum reduction.Oct 12 2019, 8:19 AM
RKSimon mentioned this in rL374658: [X86][SSE] Avoid unnecessary PMOVZX in v4i8 sum reduction.
RKSimon mentioned this in rG31ed36d0447d: [X86] SimplifyDemandedVectorElts - attempt to recombine target shuffle using….Nov 4 2019, 3:53 AM
RKSimon updated this revision to Diff 227691.Nov 4 2019, 4:32 AM

rebase - still work to do to improve unpck vs insertps selection

Herald added a subscriber: hiraditya. · View Herald TranscriptNov 4 2019, 4:32 AM
RKSimon planned changes to this revision.Nov 4 2019, 5:09 AM
RKSimon updated this revision to Diff 236181.Jan 4 2020, 9:06 AM

rebase

RKSimon mentioned this in rG3804ac63d5d8: [X86][AVX] Add tests for v8f32/v8i32 089abcde and 0189abcd shuffles.Jan 10 2020, 2:47 AM
RKSimon mentioned this in rGce35010d782c: [X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP lowering.Jan 11 2020, 4:56 AM
RKSimon mentioned this in D72575: [x86] try harder to form 256-bit unpck*.Jan 13 2020, 11:51 AM
RKSimon updated this revision to Diff 239376.Jan 21 2020, 10:39 AM

rebase (still looking at this)

RKSimon updated this revision to Diff 240877.Jan 28 2020, 7:20 AM

rebase

RKSimon mentioned this in rGe71fb46a8fd1: [TargetLowering] SimplifyDemandedVectorElts - add DemandedElts mask to ISD….Mar 10 2020, 6:59 AM
RKSimon mentioned this in rGc6e5531f9b56: [X86][AVX] Combine shuffles to TRUNCATE/VTRUNC patterns.Mar 25 2020, 10:48 AM
RKSimon mentioned this in D79335: [X86][SSE] Move VZEXT_MOVL removal into SimplifyDemandedVectorEltsForTargetNode.May 4 2020, 9:21 AM
xbolva00 added a comment.Jun 6 2020, 9:29 PM

Status of this patch?

RKSimon added a comment.Jun 8 2020, 1:37 AM
In D66004#2078352, @xbolva00 wrote:

Status of this patch?

I'm still looking at this - it both affects and is affected by so much code its a yak shaving nightmare to handle it all.

The big remaining issue is the loss of INSERTPS for some BUILDVECTOR patterns, which means we lose load folding on SSE41+ targets.

Additionally, we need to stop creating nodes on the fly inside combineX86ShufflesRecursively (see PR45974) as this screws up hasOneUse checks which are often vital in SimplifyDemandedBits/SimplifyDemandedVectorElts.

RKSimon mentioned this in rG8d30945ab96a: [X86][SSE] combineX86ShuffleChain - combine INSERT_VECTOR_ELT patterns to….Jun 12 2020, 4:17 AM
RKSimon mentioned this in D81791: [X86][SSE] Add SimplifyDemandedVectorEltsForTargetShuffle to handle target shuffle variable masks..Jun 13 2020, 11:12 AM
RKSimon mentioned this in rGfb9f9dc318d6: [X86][SSE] Add SimplifyDemandedVectorEltsForTargetShuffle to handle target….Jun 21 2020, 3:41 AM
RKSimon updated this revision to Diff 272307.Jun 21 2020, 6:28 AM

rebased - the variable shuffle mask simplification has helped but theres still some work to do - next is to fix the movhlps(x,movss) vs insertps regression

Harbormaster failed remote builds in B61167: Diff 272307!Jun 21 2020, 7:56 AM
RKSimon updated this revision to Diff 272316.Jun 21 2020, 10:47 AM

fix movhlps(x,scalar_to_vector(y)) -> insertps handling

Harbormaster completed remote builds in B61170: Diff 272316.Jun 21 2020, 12:11 PM
xbolva00 added inline comments.Jun 21 2020, 12:34 PM
llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
5637 ↗(On Diff #272316)

Regression

llvm/test/CodeGen/X86/buildvec-insertvec.ll
326

Extra instructio (vs sse2)

llvm/test/CodeGen/X86/masked_expandload.ll
1302

Regression

llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
707–713

Worse

796–802

Ouch

RKSimon added a comment.Jun 22 2020, 2:03 AM

cheers @xbolva00 for what its worth, this is still a WIP, and SimplifyDemanded improvements do have a tendency to expose existing limitations (as well as find some awesome improvements.....)

llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
5637 ↗(On Diff #272316)

The original vzext_movl (which isel would consume into the movd) has been replaced with a zero_extend_vector_inreg.

llvm/test/CodeGen/X86/buildvec-insertvec.ll
326

The original vzext_movl (which isel would consume into the movd) has been replaced with a zero_extend_vector_inreg.

llvm/test/CodeGen/X86/masked_expandload.ll
1302

We've managed to change the order of load combines and we prematurely end up with different element sizes which we then can't combine together later. This is an existing problem, we've just exposed it more.

llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
707–713

still looking at these regressions - but we've always been very weak at shuffle combining different src/dst vector widths.

RKSimon updated this revision to Diff 275153.Jul 2 2020, 9:53 AM
RKSimon edited the summary of this revision. (Show Details)

Fixed the vpmovzx regressions

Harbormaster failed remote builds in B62707: Diff 275153!Jul 2 2020, 10:48 AM
RKSimon updated this revision to Diff 276954.Jul 10 2020, 1:55 AM

rebase

Harbormaster completed remote builds in B63714: Diff 276954.Jul 10 2020, 2:28 AM
RKSimon updated this revision to Diff 280728.Jul 26 2020, 6:48 AM

rebase

Harbormaster failed remote builds in B65720: Diff 280728!Jul 26 2020, 7:18 AM
RKSimon mentioned this in rG1b1901536a7d: [X86][AVX] Extend v2f64 BROADCAST(LOAD) -> BROADCAST_LOAD to v2i64/v4f32/v4i32.Aug 1 2020, 4:29 AM
RKSimon updated this revision to Diff 282388.Aug 1 2020, 4:56 AM

rebase

Harbormaster completed remote builds in B66658: Diff 282388.Aug 1 2020, 5:31 AM
RKSimon mentioned this in rGb60f99885945: [X86][SSE] Fold 128-bit PACK(EXTEND(X),EXTEND(Y)) -> CONCAT(X,Y) subvectors.Aug 5 2020, 10:29 AM
RKSimon updated this revision to Diff 283301.Aug 5 2020, 10:50 AM

rebase

Harbormaster completed remote builds in B67138: Diff 283301.Aug 5 2020, 11:59 AM
RKSimon mentioned this in D85416: [ScalarizeMaskedMemIntrin] Scalarize constant mask expandload as shuffle(build_vector,pass_through).Aug 6 2020, 3:04 AM
RKSimon mentioned this in rG13b4db4ec206: [X86][SSE] Expose all memory offsets in expand load tests.Aug 6 2020, 3:28 AM
RKSimon mentioned this in rGc0c3b9a25fee: [ScalarizeMaskedMemIntrin] Scalarize constant mask expandload as shuffle….Aug 10 2020, 3:06 AM
RKSimon updated this revision to Diff 284306.Aug 10 2020, 3:46 AM

rebase

Harbormaster completed remote builds in B67691: Diff 284306.Aug 10 2020, 4:26 AM
RKSimon mentioned this in rG1d2ede87eacb: [X86][AVX] Move lowerShuffleWithVPMOV inside explicit shuffle lowering cases.Aug 17 2020, 4:10 AM
RKSimon mentioned this in D86093: [X86][AVX] Lower v16i8/v8i16 shuffles using VTRUNC/TRUNCATE.Aug 17 2020, 10:50 AM
RKSimon mentioned this in rGd2057a8015e9: [X86][AVX] Lower v16i8/v8i16 binary shuffles using VTRUNC/TRUNCATE.Aug 18 2020, 3:12 AM
RKSimon mentioned this in rG87122c3480e2: [X86] Regenerate load-slice test labels. NFCI..Aug 18 2020, 8:09 AM
RKSimon updated this revision to Diff 286284.Aug 18 2020, 8:18 AM
RKSimon retitled this revision from [WIP][X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support to [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support.
RKSimon edited the summary of this revision. (Show Details)

All regressions should now be covered.

xbolva00 added a comment.Aug 18 2020, 8:21 AM

Amazing work Simon!

Harbormaster completed remote builds in B68755: Diff 286284.Aug 18 2020, 8:49 AM
RKSimon added a comment.Aug 28 2020, 3:41 AM

ping - I think this is ready for commital now, I delayed pinging as I knew I'd be away on holiday this week and a patch like this is likely to cause a few unexpected regressions that will need addressing.

craig.topper accepted this revision.Aug 28 2020, 3:32 PM

LGTM

This revision is now accepted and ready to land.Aug 28 2020, 3:32 PM
Herald added a subscriber: danielkiss. · View Herald TranscriptAug 28 2020, 3:32 PM
This revision was landed with ongoing or failed builds.Sep 2 2020, 1:25 AM
Closed by commit rG21d02dc59579: [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle… (authored by RKSimon). · Explain Why
This revision was automatically updated to reflect the committed changes.
RKSimon added a commit: rG21d02dc59579: [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle….
RKSimon mentioned this in D86429: [X86] Make lowerShuffleAsLanePermuteAndPermute use sublanes on AVX2.Sep 2 2020, 2:19 AM
RKSimon mentioned this in D87005: [ScalarizeMaskedMemIntrin] Scalarize constant mask load as shuffle(build_vector,pass_through).Sep 2 2020, 3:47 AM

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Diff 240877

llvm/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,991 Lines • ▼ Show 20 Lines
MVT MaskVT = MVT::getVectorVT(MaskSVT, NumMaskElts); MVT MaskVT = MVT::getVectorVT(MaskSVT, NumMaskElts);
SDLoc DL(Root); SDLoc DL(Root);
SDValue CstOp = getConstVector(ConstantBitData, UndefElts, MaskVT, DAG, DL); SDValue CstOp = getConstVector(ConstantBitData, UndefElts, MaskVT, DAG, DL);
return DAG.getBitcast(VT, CstOp); return DAG.getBitcast(VT, CstOp);
} }
namespace llvm {
namespace X86 {
enum {
MaxShuffleCombineDepth = 8
};
};
}; // namespace llvm
/// Fully generic combining of x86 shuffle instructions. /// Fully generic combining of x86 shuffle instructions.
/// ///
/// This should be the last combine run over the x86 shuffle instructions. Once /// This should be the last combine run over the x86 shuffle instructions. Once
/// they have been fully optimized, this will recursively consider all chains /// they have been fully optimized, this will recursively consider all chains
/// of single-use shuffle instructions, build a generic model of the cumulative /// of single-use shuffle instructions, build a generic model of the cumulative
/// shuffle operation, and check for simpler instructions which implement this /// shuffle operation, and check for simpler instructions which implement this
/// operation. We use this primarily for two purposes: /// operation. We use this primarily for two purposes:
/// ///
Show All 16 Lines
/// ///
/// FIXME: We will currently miss some cases where the redundant shuffling /// FIXME: We will currently miss some cases where the redundant shuffling
/// would simplify under the threshold for PSHUFB formation because of /// would simplify under the threshold for PSHUFB formation because of
/// combine-ordering. To fix this, we should do the redundant instruction /// combine-ordering. To fix this, we should do the redundant instruction
/// combining in this recursive walk. /// combining in this recursive walk.
static SDValue combineX86ShufflesRecursively( static SDValue combineX86ShufflesRecursively(
ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root, ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root,
ArrayRef<int> RootMask, ArrayRef<const SDNode *> SrcNodes, unsigned Depth, ArrayRef<int> RootMask, ArrayRef<const SDNode *> SrcNodes, unsigned Depth,
bool HasVariableMask, bool AllowVariableMask, SelectionDAG &DAG, unsigned MaxDepth, bool HasVariableMask, bool AllowVariableMask,
const X86Subtarget &Subtarget) { SelectionDAG &DAG, const X86Subtarget &Subtarget) {
assert(RootMask.size() > 0 && assert(RootMask.size() > 0 &&
(RootMask.size() > 1 || (RootMask[0] == 0 && SrcOpIndex == 0)) && (RootMask.size() > 1 || (RootMask[0] == 0 && SrcOpIndex == 0)) &&
"Illegal shuffle root mask"); "Illegal shuffle root mask");
// Bound the depth of our recursive combine because this is ultimately // Bound the depth of our recursive combine because this is ultimately
// quadratic in nature. // quadratic in nature.
const unsigned MaxRecursionDepth = 8; if (Depth >= MaxDepth)
if (Depth >= MaxRecursionDepth)
return SDValue(); return SDValue();
// Directly rip through bitcasts to find the underlying operand. // Directly rip through bitcasts to find the underlying operand.
SDValue Op = SrcOps[SrcOpIndex]; SDValue Op = SrcOps[SrcOpIndex];
Op = peekThroughOneUseBitcasts(Op); Op = peekThroughOneUseBitcasts(Op);
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
if (!VT.isVector()) if (!VT.isVector())
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines
// See if we can recurse into each shuffle source op (if it's a target // See if we can recurse into each shuffle source op (if it's a target
// shuffle). The source op should only be generally combined if it either has // shuffle). The source op should only be generally combined if it either has
// a single use (i.e. current Op) or all its users have already been combined, // a single use (i.e. current Op) or all its users have already been combined,
// if not then we can still combine but should prevent generation of variable // if not then we can still combine but should prevent generation of variable
// shuffles to avoid constant pool bloat. // shuffles to avoid constant pool bloat.
// Don't recurse if we already have more source ops than we can combine in // Don't recurse if we already have more source ops than we can combine in
// the remaining recursion depth. // the remaining recursion depth.
if (Ops.size() < (MaxRecursionDepth - Depth)) { if (Ops.size() < (MaxDepth - Depth)) {
for (int i = 0, e = Ops.size(); i < e; ++i) { for (int i = 0, e = Ops.size(); i < e; ++i) {
// For empty roots, we need to resolve zeroable elements before combining // For empty roots, we need to resolve zeroable elements before combining
// them with other shuffles. // them with other shuffles.
SmallVector<int, 64> ResolvedMask = Mask; SmallVector<int, 64> ResolvedMask = Mask;
if (EmptyRoot) if (EmptyRoot)
resolveTargetShuffleFromZeroables(ResolvedMask, OpUndef, OpZero); resolveTargetShuffleFromZeroables(ResolvedMask, OpUndef, OpZero);
bool AllowVar = false; bool AllowVar = false;
if (Ops[i].getNode()->hasOneUse() || if (Ops[i].getNode()->hasOneUse() ||
SDNode::areOnlyUsersOf(CombinedNodes, Ops[i].getNode())) SDNode::areOnlyUsersOf(CombinedNodes, Ops[i].getNode()))
AllowVar = AllowVariableMask; AllowVar = AllowVariableMask;
if (SDValue Res = combineX86ShufflesRecursively( if (SDValue Res = combineX86ShufflesRecursively(
Ops, i, Root, ResolvedMask, CombinedNodes, Depth + 1, Ops, i, Root, ResolvedMask, CombinedNodes, Depth + 1, MaxDepth,
HasVariableMask, AllowVar, DAG, Subtarget)) HasVariableMask, AllowVar, DAG, Subtarget))
return Res; return Res;
} }
} }
// Attempt to constant fold all of the constant source ops. // Attempt to constant fold all of the constant source ops.
if (SDValue Cst = combineX86ShufflesConstants( if (SDValue Cst = combineX86ShufflesConstants(
Ops, Mask, Root, HasVariableMask, DAG, Subtarget)) Ops, Mask, Root, HasVariableMask, DAG, Subtarget))
Show All 29 Lines
HasVariableMask, AllowVariableMask, HasVariableMask, AllowVariableMask,
DAG, Subtarget); DAG, Subtarget);
} }
/// Helper entry wrapper to combineX86ShufflesRecursively. /// Helper entry wrapper to combineX86ShufflesRecursively.
static SDValue combineX86ShufflesRecursively(SDValue Op, SelectionDAG &DAG, static SDValue combineX86ShufflesRecursively(SDValue Op, SelectionDAG &DAG,
const X86Subtarget &Subtarget) { const X86Subtarget &Subtarget) {
return combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 0, return combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 0,
X86::MaxShuffleCombineDepth,
/*HasVarMask*/ false, /*HasVarMask*/ false,
/*AllowVarMask*/ true, DAG, Subtarget); /*AllowVarMask*/ true, DAG, Subtarget);
} }
/// Get the PSHUF-style mask from PSHUF node. /// Get the PSHUF-style mask from PSHUF node.
/// ///
/// This is a very minor wrapper around getTargetShuffleMask to easy forming v4 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
/// PSHUF-style masks that can be reused with such instructions. /// PSHUF-style masks that can be reused with such instructions.
▲ Show 20 Lines • Show All 275 Lines • ▼ Show 20 Lines
VT.getScalarSizeInBits() % BCVT.getScalarSizeInBits() == 0) { VT.getScalarSizeInBits() % BCVT.getScalarSizeInBits() == 0) {
unsigned Scale = VT.getScalarSizeInBits() / BCVT.getScalarSizeInBits(); unsigned Scale = VT.getScalarSizeInBits() / BCVT.getScalarSizeInBits();
SmallVector<int, 16> DemandedMask(BCVT.getVectorNumElements(), SmallVector<int, 16> DemandedMask(BCVT.getVectorNumElements(),
SM_SentinelUndef); SM_SentinelUndef);
for (unsigned i = 0; i != Scale; ++i) for (unsigned i = 0; i != Scale; ++i)
DemandedMask[i] = i; DemandedMask[i] = i;
if (SDValue Res = combineX86ShufflesRecursively( if (SDValue Res = combineX86ShufflesRecursively(
{BC}, 0, BC, DemandedMask, {}, /*Depth*/ 0, {BC}, 0, BC, DemandedMask, {}, /*Depth*/ 0,
X86::MaxShuffleCombineDepth,
/*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget)) /*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget))
return DAG.getNode(X86ISD::VBROADCAST, DL, VT, return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
DAG.getBitcast(SrcVT, Res)); DAG.getBitcast(SrcVT, Res));
} }
// broadcast(bitcast(src)) -> bitcast(broadcast(src)) // broadcast(bitcast(src)) -> bitcast(broadcast(src))
// 32-bit targets have to bitcast i64 to f64, so better to bitcast upward. // 32-bit targets have to bitcast i64 to f64, so better to bitcast upward.
if (Src.getOpcode() == ISD::BITCAST && if (Src.getOpcode() == ISD::BITCAST &&
▲ Show 20 Lines • Show All 1,248 Lines • ▼ Show 20 Lines
APInt SrcUndef, SrcZero; APInt SrcUndef, SrcZero;
if (SimplifyDemandedVectorElts(OpInputs[Src], SrcElts, SrcUndef, SrcZero, if (SimplifyDemandedVectorElts(OpInputs[Src], SrcElts, SrcUndef, SrcZero,
TLO, Depth + 1)) TLO, Depth + 1))
return true; return true;
} }
// If we don't demand all elements, then attempt to combine to a simpler // If we don't demand all elements, then attempt to combine to a simpler
// shuffle. // shuffle.
// TODO: Handle other depths, but first we need to handle the fact that // We need to convert the depth to something combineX86ShufflesRecursively
// it might combine to the same shuffle. // can handle - so pretend its Depth == 0 again, and reduce the max depth
if (!DemandedElts.isAllOnesValue() && Depth == 0) { // to match. This prevents combineX86ShuffleChain from returning a
// combined shuffle that's the same as the original root, causing an
// infinite loop.
if (!DemandedElts.isAllOnesValue()) {
assert(Depth < X86::MaxShuffleCombineDepth && "Depth out of range");
SmallVector<int, 64> DemandedMask(NumElts, SM_SentinelUndef); SmallVector<int, 64> DemandedMask(NumElts, SM_SentinelUndef);
for (int i = 0; i != NumElts; ++i) for (int i = 0; i != NumElts; ++i)
if (DemandedElts[i]) if (DemandedElts[i])
DemandedMask[i] = i; DemandedMask[i] = i;
SDValue NewShuffle = combineX86ShufflesRecursively( SDValue NewShuffle = combineX86ShufflesRecursively(
{Op}, 0, Op, DemandedMask, {}, Depth, /*HasVarMask*/ false, {Op}, 0, Op, DemandedMask, {}, 0, X86::MaxShuffleCombineDepth - Depth,
/*HasVarMask*/ false,
/*AllowVarMask*/ true, TLO.DAG, Subtarget); /*AllowVarMask*/ true, TLO.DAG, Subtarget);
if (NewShuffle) if (NewShuffle)
return TLO.CombineTo(Op, NewShuffle); return TLO.CombineTo(Op, NewShuffle);
} }
return false; return false;
} }
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continue; continue;
int VecIdx = Scale * Idx + i; int VecIdx = Scale * Idx + i;
ShuffleMask[VecIdx] = ShuffleMask[VecIdx] =
EltBits[i].isNullValue() ? SM_SentinelZero : VecIdx; EltBits[i].isNullValue() ? SM_SentinelZero : VecIdx;
} }
if (SDValue Shuffle = combineX86ShufflesRecursively( if (SDValue Shuffle = combineX86ShufflesRecursively(
{SrcVec}, 0, SrcVec, ShuffleMask, {}, /*Depth*/ 1, {SrcVec}, 0, SrcVec, ShuffleMask, {}, /*Depth*/ 1,
X86::MaxShuffleCombineDepth,
/*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget)) /*HasVarMask*/ false, /*AllowVarMask*/ true, DAG, Subtarget))
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), VT, Shuffle, return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), VT, Shuffle,
N->getOperand(0).getOperand(1)); N->getOperand(0).getOperand(1));
} }
} }
return SDValue(); return SDValue();
} }
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llvm/test/CodeGen/X86/avg.ll

Show First 20 Lines • Show All 1,903 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movaps (%rsi), %xmm0 ; SSE2-NEXT: movaps (%rsi), %xmm0
; SSE2-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r11d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r13d ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r13d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r12d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r15d ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r15d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r11d ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r14d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r10d ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebp
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r12d
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebp
; SSE2-NEXT: addq %r11, %rbp
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r14d
; SSE2-NEXT: addq %r10, %r14
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebx
; SSE2-NEXT: addq %r9, %rbx ; SSE2-NEXT: addq %rbp, %rbx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r11d
; SSE2-NEXT: addq %r8, %r11
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r10d ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r10d
; SSE2-NEXT: addq %rdx, %r10 ; SSE2-NEXT: addq %rdi, %r10
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ebp
; SSE2-NEXT: addq %rcx, %r8 ; SSE2-NEXT: addq %rcx, %rbp
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi
; SSE2-NEXT: addq %rax, %rdi ; SSE2-NEXT: addq %rax, %rdi
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; SSE2-NEXT: addq %r8, %rcx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; SSE2-NEXT: addq %r12, %rax
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: addq %rsi, %rdx ; SSE2-NEXT: leaq -1(%r14,%rdx), %r12
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: leaq -1(%r15,%rsi), %rax ; SSE2-NEXT: leaq -1(%r15,%rdx), %r15
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: leaq -1(%r13,%rdx), %r13
; SSE2-NEXT: leaq -1(%r12,%rsi), %rax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: leaq -1(%rsi,%rdx), %rdx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: leaq -1(%r13,%rsi), %rax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: leaq -1(%rsi,%rdx), %rdx
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; SSE2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: leaq -1(%rax,%rsi), %rax ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: leaq -1(%r11,%rdx), %rdx
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: leaq -1(%rax,%rsi), %rax ; SSE2-NEXT: leaq -1(%r9,%rdx), %rdx
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; SSE2-NEXT: leaq -1(%rax,%rsi), %rax ; SSE2-NEXT: leaq -1(%rsi,%rdx), %rdx
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; SSE2-NEXT: leaq -1(%rax,%rsi), %rsi ; SSE2-NEXT: leaq -1(%rsi,%rdx), %rdx
; SSE2-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi ; SSE2-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
; SSE2-NEXT: leaq -1(%rax,%rsi), %rsi ; SSE2-NEXT: leaq -1(%rsi,%rdx), %rdx
; SSE2-NEXT: movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: addq $-1, %rbp ; SSE2-NEXT: xorl %r14d, %r14d
; SSE2-NEXT: addq $-1, %rbx
; SSE2-NEXT: movl $0, %r9d ; SSE2-NEXT: movl $0, %r9d
; SSE2-NEXT: adcq $-1, %r9 ; SSE2-NEXT: adcq $-1, %r9
; SSE2-NEXT: addq $-1, %r14 ; SSE2-NEXT: addq $-1, %r10
; SSE2-NEXT: movl $0, %esi ; SSE2-NEXT: movl $0, %esi
; SSE2-NEXT: adcq $-1, %rsi ; SSE2-NEXT: adcq $-1, %rsi
; SSE2-NEXT: addq $-1, %rbx ; SSE2-NEXT: addq $-1, %rbp
; SSE2-NEXT: movl $0, %eax ; SSE2-NEXT: movl $0, %r8d
; SSE2-NEXT: adcq $-1, %rax ; SSE2-NEXT: adcq $-1, %r8
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE2-NEXT: addq $-1, %r11
; SSE2-NEXT: movl $0, %r12d
; SSE2-NEXT: adcq $-1, %r12
; SSE2-NEXT: addq $-1, %r10
; SSE2-NEXT: movl $0, %r13d
; SSE2-NEXT: adcq $-1, %r13
; SSE2-NEXT: addq $-1, %r8
; SSE2-NEXT: movl $0, %r15d
; SSE2-NEXT: adcq $-1, %r15
; SSE2-NEXT: addq $-1, %rdi ; SSE2-NEXT: addq $-1, %rdi
; SSE2-NEXT: movl $0, %ecx ; SSE2-NEXT: movl $0, %edx
; SSE2-NEXT: adcq $-1, %rcx ; SSE2-NEXT: adcq $-1, %rdx
; SSE2-NEXT: addq $-1, %rdx ; SSE2-NEXT: addq $-1, %rcx
; SSE2-NEXT: movl $0, %eax ; SSE2-NEXT: movl $0, %r11d
; SSE2-NEXT: adcq $-1, %rax ; SSE2-NEXT: adcq $-1, %r11
; SSE2-NEXT: shldq $63, %rdx, %rax ; SSE2-NEXT: addq $-1, %rax
; SSE2-NEXT: shldq $63, %rdi, %rcx ; SSE2-NEXT: adcq $-1, %r14
; SSE2-NEXT: movq %rcx, %rdx ; SSE2-NEXT: shldq $63, %rax, %r14
; SSE2-NEXT: shldq $63, %r8, %r15 ; SSE2-NEXT: shldq $63, %rcx, %r11
; SSE2-NEXT: shldq $63, %r10, %r13 ; SSE2-NEXT: shldq $63, %rdi, %rdx
; SSE2-NEXT: shldq $63, %r11, %r12 ; SSE2-NEXT: shldq $63, %rbp, %r8
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdi # 8-byte Reload ; SSE2-NEXT: shldq $63, %r10, %rsi
; SSE2-NEXT: shldq $63, %rbx, %rdi ; SSE2-NEXT: shldq $63, %rbx, %r9
; SSE2-NEXT: shldq $63, %r14, %rsi
; SSE2-NEXT: shldq $63, %rbp, %r9
; SSE2-NEXT: movq %r9, %xmm8 ; SSE2-NEXT: movq %r9, %xmm8
; SSE2-NEXT: movq %rsi, %xmm15 ; SSE2-NEXT: movq %rsi, %xmm0
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; SSE2-NEXT: movq %r8, %xmm9
; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: movq %rdx, %xmm2
; SSE2-NEXT: movq %rcx, %xmm9 ; SSE2-NEXT: shrq %r12
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; SSE2-NEXT: movq %r12, %xmm10
; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: shrq %r15
; SSE2-NEXT: movq %rcx, %xmm2 ; SSE2-NEXT: movq %r15, %xmm5
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; SSE2-NEXT: shrq %r13
; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: movq %r13, %xmm11
; SSE2-NEXT: movq %rcx, %xmm10 ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; SSE2-NEXT: shrq %rax
; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: movq %rax, %xmm7
; SSE2-NEXT: movq %rcx, %xmm4 ; SSE2-NEXT: movq %r11, %xmm12
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; SSE2-NEXT: movq %r14, %xmm3
; SSE2-NEXT: shrq %rcx ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; SSE2-NEXT: movq %rcx, %xmm11 ; SSE2-NEXT: shrq %rax
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload ; SSE2-NEXT: movq %rax, %xmm13
; SSE2-NEXT: shrq %rcx
; SSE2-NEXT: movq %rcx, %xmm7
; SSE2-NEXT: movq %rdi, %xmm12
; SSE2-NEXT: movq %r12, %xmm0
; SSE2-NEXT: movq %r13, %xmm13
; SSE2-NEXT: movq %r15, %xmm6
; SSE2-NEXT: movq %rdx, %xmm14
; SSE2-NEXT: movq %rax, %xmm5
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; SSE2-NEXT: shrq %rax ; SSE2-NEXT: shrq %rax
; SSE2-NEXT: movq %rax, %xmm3 ; SSE2-NEXT: movq %rax, %xmm6
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; SSE2-NEXT: shrq %rax
; SSE2-NEXT: movq %rax, %xmm14
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; SSE2-NEXT: shrq %rax
; SSE2-NEXT: movq %rax, %xmm4
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; SSE2-NEXT: shrq %rax
; SSE2-NEXT: movq %rax, %xmm15
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
; SSE2-NEXT: shrq %rax ; SSE2-NEXT: shrq %rax
; SSE2-NEXT: movq %rax, %xmm1 ; SSE2-NEXT: movq %rax, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm8[0],xmm0[1],xmm8[1],xmm0[2],xmm8[2],xmm0[3],xmm8[3],xmm0[4],xmm8[4],xmm0[5],xmm8[5],xmm0[6],xmm8[6],xmm0[7],xmm8[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm9[0],xmm2[1],xmm9[1],xmm2[2],xmm9[2],xmm2[3],xmm9[3],xmm2[4],xmm9[4],xmm2[5],xmm9[5],xmm2[6],xmm9[6],xmm2[7],xmm9[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm9[0],xmm2[1],xmm9[1],xmm2[2],xmm9[2],xmm2[3],xmm9[3],xmm2[4],xmm9[4],xmm2[5],xmm9[5],xmm2[6],xmm9[6],xmm2[7],xmm9[7]
; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm15[0,1,2,0] ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [65535,0,65535,65535,65535,65535,65535,65535]
; SSE2-NEXT: pand {{.*}}(%rip), %xmm8 ; SSE2-NEXT: pand %xmm8, %xmm0
; SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1] ; SSE2-NEXT: pslld $16, %xmm2
; SSE2-NEXT: por %xmm8, %xmm2 ; SSE2-NEXT: pandn %xmm2, %xmm8
; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm10[0],xmm4[1],xmm10[1],xmm4[2],xmm10[2],xmm4[3],xmm10[3],xmm4[4],xmm10[4],xmm4[5],xmm10[5],xmm4[6],xmm10[6],xmm4[7],xmm10[7] ; SSE2-NEXT: por %xmm0, %xmm8
; SSE2-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm10[0],xmm5[1],xmm10[1],xmm5[2],xmm10[2],xmm5[3],xmm10[3],xmm5[4],xmm10[4],xmm5[5],xmm10[5],xmm5[6],xmm10[6],xmm5[7],xmm10[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3],xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3],xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7]
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [65535,65535,65535,65535,65535,0,65535,65535] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3]
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm7[0,1,0,1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1]
; SSE2-NEXT: pand %xmm8, %xmm7 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm12[0],xmm3[1],xmm12[1],xmm3[2],xmm12[2],xmm3[3],xmm12[3],xmm3[4],xmm12[4],xmm3[5],xmm12[5],xmm3[6],xmm12[6],xmm3[7],xmm12[7]
; SSE2-NEXT: pandn %xmm4, %xmm8
; SSE2-NEXT: por %xmm7, %xmm8
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm8[0,1,2,2]
; SSE2-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm12[0],xmm0[1],xmm12[1],xmm0[2],xmm12[2],xmm0[3],xmm12[3],xmm0[4],xmm12[4],xmm0[5],xmm12[5],xmm0[6],xmm12[6],xmm0[7],xmm12[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],xmm13[1],xmm6[2],xmm13[2],xmm6[3],xmm13[3],xmm6[4],xmm13[4],xmm6[5],xmm13[5],xmm6[6],xmm13[6],xmm6[7],xmm13[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],xmm13[1],xmm6[2],xmm13[2],xmm6[3],xmm13[3],xmm6[4],xmm13[4],xmm6[5],xmm13[5],xmm6[6],xmm13[6],xmm6[7],xmm13[7]
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,65535,65535,65535,65535,65535,65535] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,1,2,0]
; SSE2-NEXT: pand %xmm2, %xmm0 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: pslld $16, %xmm6 ; SSE2-NEXT: pslldq {{.*#+}} xmm6 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm6[0,1]
; SSE2-NEXT: pandn %xmm6, %xmm2 ; SSE2-NEXT: por %xmm0, %xmm6
; SSE2-NEXT: por %xmm0, %xmm2 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm14[0],xmm4[1],xmm14[1],xmm4[2],xmm14[2],xmm4[3],xmm14[3],xmm4[4],xmm14[4],xmm4[5],xmm14[5],xmm4[6],xmm14[6],xmm4[7],xmm14[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm14[0],xmm5[1],xmm14[1],xmm5[2],xmm14[2],xmm5[3],xmm14[3],xmm5[4],xmm14[4],xmm5[5],xmm14[5],xmm5[6],xmm14[6],xmm5[7],xmm14[7] ; SSE2-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5]
; SSE2-NEXT: psllq $48, %xmm5 ; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,65535,65535,65535,65535,0,65535,65535]
; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [65535,65535,65535,0,65535,65535,65535,65535] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm15[0],xmm1[1],xmm15[1],xmm1[2],xmm15[2],xmm1[3],xmm15[3],xmm1[4],xmm15[4],xmm1[5],xmm15[5],xmm1[6],xmm15[6],xmm1[7],xmm15[7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: pandn %xmm5, %xmm0 ; SSE2-NEXT: pandn %xmm4, %xmm0
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm6[2],xmm0[3],xmm6[3]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3] ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm8[0],xmm0[1]
; SSE2-NEXT: movups %xmm2, (%rax) ; SSE2-NEXT: movupd %xmm0, (%rax)
; SSE2-NEXT: popq %rbx ; SSE2-NEXT: popq %rbx
; SSE2-NEXT: popq %r12 ; SSE2-NEXT: popq %r12
; SSE2-NEXT: popq %r13 ; SSE2-NEXT: popq %r13
; SSE2-NEXT: popq %r14 ; SSE2-NEXT: popq %r14
; SSE2-NEXT: popq %r15 ; SSE2-NEXT: popq %r15
; SSE2-NEXT: popq %rbp ; SSE2-NEXT: popq %rbp
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
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; AVX2-NEXT: vmovq %r11, %xmm3 ; AVX2-NEXT: vmovq %r11, %xmm3
; AVX2-NEXT: vmovq %r9, %xmm4 ; AVX2-NEXT: vmovq %r9, %xmm4
; AVX2-NEXT: vmovq %r8, %xmm5 ; AVX2-NEXT: vmovq %r8, %xmm5
; AVX2-NEXT: vmovq %rdi, %xmm6 ; AVX2-NEXT: vmovq %rdi, %xmm6
; AVX2-NEXT: vmovq {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 8-byte Folded Reload ; AVX2-NEXT: vmovq {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 8-byte Folded Reload
; AVX2-NEXT: # xmm7 = mem[0],zero ; AVX2-NEXT: # xmm7 = mem[0],zero
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm9[0],xmm8[0],xmm9[1],xmm8[1],xmm9[2],xmm8[2],xmm9[3],xmm8[3],xmm9[4],xmm8[4],xmm9[5],xmm8[5],xmm9[6],xmm8[6],xmm9[7],xmm8[7] ; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm9[0],xmm8[0],xmm9[1],xmm8[1],xmm9[2],xmm8[2],xmm9[3],xmm8[3],xmm9[4],xmm8[4],xmm9[5],xmm8[5],xmm9[6],xmm8[6],xmm9[7],xmm8[7]
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX2-NEXT: vpslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1] ; AVX2-NEXT: vpbroadcastw %xmm8, %xmm8
; AVX2-NEXT: vpbroadcastw %xmm9, %xmm0 ; AVX2-NEXT: vpbroadcastw %xmm9, %xmm0
; AVX2-NEXT: vpblendw {{.*#+}} xmm8 = xmm0[0,1,2,3,4,5,6],xmm8[7] ; AVX2-NEXT: vpblendw {{.*#+}} xmm8 = xmm0[0,1,2,3,4,5,6],xmm8[7]
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3],xmm13[4],xmm12[4],xmm13[5],xmm12[5],xmm13[6],xmm12[6],xmm13[7],xmm12[7] ; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3],xmm13[4],xmm12[4],xmm13[5],xmm12[5],xmm13[6],xmm12[6],xmm13[7],xmm12[7]
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3],xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7] ; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm9 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3],xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7]
; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5] ; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm9, %xmm1 ; AVX2-NEXT: vpbroadcastw %xmm9, %xmm1
; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4],xmm0[5],xmm1[6,7] ; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4],xmm0[5],xmm1[6,7]
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm8[3] ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm8[3]
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] ; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7]
; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] ; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3],xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
; AVX2-NEXT: vpsllq $48, %xmm1, %xmm1 ; AVX2-NEXT: vpsllq $48, %xmm1, %xmm1
; AVX2-NEXT: vpbroadcastw %xmm2, %xmm2 ; AVX2-NEXT: vpbroadcastw %xmm2, %xmm2
; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[3],xmm2[4,5,6,7] ; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[3],xmm2[4,5,6,7]
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llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 1,794 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <4 x double> %res3 ret <4 x double> %res3
} }
define <8 x float> @test_mm256_set_ps(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) nounwind { define <8 x float> @test_mm256_set_ps(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) nounwind {
; X86-LABEL: test_mm256_set_ps: ; X86-LABEL: test_mm256_set_ps:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X86-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; X86-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] ; X86-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; X86-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; X86-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm256_set_ps: ; X64-LABEL: test_mm256_set_ps:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; X64-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; X64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm7[0],xmm6[0],xmm7[2,3] ; X64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm7[0],xmm6[0],xmm7[1],xmm6[1]
; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm5[0],xmm1[3] ; X64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm5[0]
; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0] ; X64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = insertelement <8 x float> undef, float %a7, i32 0 %res0 = insertelement <8 x float> undef, float %a7, i32 0
%res1 = insertelement <8 x float> %res0, float %a6, i32 1 %res1 = insertelement <8 x float> %res0, float %a6, i32 1
%res2 = insertelement <8 x float> %res1, float %a5, i32 2 %res2 = insertelement <8 x float> %res1, float %a5, i32 2
%res3 = insertelement <8 x float> %res2, float %a4, i32 3 %res3 = insertelement <8 x float> %res2, float %a4, i32 3
%res4 = insertelement <8 x float> %res3, float %a3, i32 4 %res4 = insertelement <8 x float> %res3, float %a3, i32 4
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define <8 x float> @test_mm256_setr_ps(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) nounwind { define <8 x float> @test_mm256_setr_ps(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) nounwind {
; X86-LABEL: test_mm256_setr_ps: ; X86-LABEL: test_mm256_setr_ps:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; X86-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; X86-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; X86-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; X86-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; X86-NEXT: vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
; X86-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; X86-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; X86-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1],xmm2[0],xmm3[3] ; X86-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; X86-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0] ; X86-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; X86-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm256_setr_ps: ; X64-LABEL: test_mm256_setr_ps:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3] ; X64-NEXT: vunpcklps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; X64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3] ; X64-NEXT: vmovlhps {{.*#+}} xmm4 = xmm4[0],xmm6[0]
; X64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0] ; X64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X64-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; X64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; X64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; X64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%res0 = insertelement <8 x float> undef, float %a0, i32 0 %res0 = insertelement <8 x float> undef, float %a0, i32 0
%res1 = insertelement <8 x float> %res0, float %a1, i32 1 %res1 = insertelement <8 x float> %res0, float %a1, i32 1
%res2 = insertelement <8 x float> %res1, float %a2, i32 2 %res2 = insertelement <8 x float> %res1, float %a2, i32 2
%res3 = insertelement <8 x float> %res2, float %a3, i32 3 %res3 = insertelement <8 x float> %res2, float %a3, i32 3
%res4 = insertelement <8 x float> %res3, float %a4, i32 4 %res4 = insertelement <8 x float> %res3, float %a4, i32 4
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llvm/test/CodeGen/X86/avx-trunc.ll

Show All 10 Lines; CHECK-NEXT: retq
%B = trunc <4 x i64> %A to <4 x i32> %B = trunc <4 x i64> %A to <4 x i32>
ret <4 x i32>%B ret <4 x i32>%B
} }
define <8 x i16> @trunc_32_16(<8 x i32> %A) nounwind uwtable readnone ssp{ define <8 x i16> @trunc_32_16(<8 x i32> %A) nounwind uwtable readnone ssp{
; CHECK-LABEL: trunc_32_16: ; CHECK-LABEL: trunc_32_16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; CHECK-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%B = trunc <8 x i32> %A to <8 x i16> %B = trunc <8 x i32> %A to <8 x i16>
ret <8 x i16>%B ret <8 x i16>%B
} }
define <16 x i8> @trunc_16_8(<16 x i16> %A) nounwind uwtable readnone ssp{ define <16 x i8> @trunc_16_8(<16 x i16> %A) nounwind uwtable readnone ssp{
Show All 12 Lines

llvm/test/CodeGen/X86/avx512-cvt.ll

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; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; DQNOVL-NEXT: vzeroupper ; DQNOVL-NEXT: vzeroupper
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = sitofp <2 x i64> %a to <2 x float> %b = sitofp <2 x i64> %a to <2 x float>
ret <2 x float>%b ret <2 x float>%b
} }
define <4 x float> @slto4f32_mem(<4 x i64>* %a) { define <4 x float> @slto4f32_mem(<4 x i64>* %a) {
; NODQ-LABEL: slto4f32_mem: ; NOVLDQ-LABEL: slto4f32_mem:
; NODQ: # %bb.0: ; NOVLDQ: # %bb.0:
; NODQ-NEXT: vmovdqu (%rdi), %xmm0 ; NOVLDQ-NEXT: vmovdqu (%rdi), %xmm0
; NODQ-NEXT: vmovdqu 16(%rdi), %xmm1 ; NOVLDQ-NEXT: vmovdqu 16(%rdi), %xmm1
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; NODQ-NEXT: vmovq %xmm1, %rax ; NOVLDQ-NEXT: vmovq %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; NODQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: slto4f32_mem: ; VLDQ-LABEL: slto4f32_mem:
; VLDQ: # %bb.0: ; VLDQ: # %bb.0:
; VLDQ-NEXT: vcvtqq2psy (%rdi), %xmm0 ; VLDQ-NEXT: vcvtqq2psy (%rdi), %xmm0
; VLDQ-NEXT: retq ; VLDQ-NEXT: retq
; ;
; VLNODQ-LABEL: slto4f32_mem:
; VLNODQ: # %bb.0:
; VLNODQ-NEXT: vmovdqu (%rdi), %xmm0
; VLNODQ-NEXT: vmovdqu 16(%rdi), %xmm1
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; VLNODQ-NEXT: vmovq %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; VLNODQ-NEXT: vpextrq $1, %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; VLNODQ-NEXT: retq
;
; DQNOVL-LABEL: slto4f32_mem: ; DQNOVL-LABEL: slto4f32_mem:
; DQNOVL: # %bb.0: ; DQNOVL: # %bb.0:
; DQNOVL-NEXT: vmovups (%rdi), %ymm0 ; DQNOVL-NEXT: vmovups (%rdi), %ymm0
; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0 ; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0
; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; DQNOVL-NEXT: vzeroupper ; DQNOVL-NEXT: vzeroupper
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%a1 = load <4 x i64>, <4 x i64>* %a, align 8 %a1 = load <4 x i64>, <4 x i64>* %a, align 8
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; DQNOVL-NEXT: vcvttps2qq %ymm0, %zmm0 ; DQNOVL-NEXT: vcvttps2qq %ymm0, %zmm0
; DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = fptosi <4 x float> %a to <4 x i64> %b = fptosi <4 x float> %a to <4 x i64>
ret <4 x i64> %b ret <4 x i64> %b
} }
define <4 x float> @slto4f32(<4 x i64> %a) { define <4 x float> @slto4f32(<4 x i64> %a) {
; NODQ-LABEL: slto4f32: ; NOVLDQ-LABEL: slto4f32:
; NODQ: # %bb.0: ; NOVLDQ: # %bb.0:
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NOVLDQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; NODQ-NEXT: vzeroupper ; NOVLDQ-NEXT: vzeroupper
; NODQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: slto4f32: ; VLDQ-LABEL: slto4f32:
; VLDQ: # %bb.0: ; VLDQ: # %bb.0:
; VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0 ; VLDQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; VLDQ-NEXT: vzeroupper ; VLDQ-NEXT: vzeroupper
; VLDQ-NEXT: retq ; VLDQ-NEXT: retq
; ;
; VLNODQ-LABEL: slto4f32:
; VLNODQ: # %bb.0:
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; VLNODQ-NEXT: vzeroupper
; VLNODQ-NEXT: retq
;
; DQNOVL-LABEL: slto4f32: ; DQNOVL-LABEL: slto4f32:
; DQNOVL: # %bb.0: ; DQNOVL: # %bb.0:
; DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0 ; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0
; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; DQNOVL-NEXT: vzeroupper ; DQNOVL-NEXT: vzeroupper
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = sitofp <4 x i64> %a to <4 x float> %b = sitofp <4 x i64> %a to <4 x float>
ret <4 x float> %b ret <4 x float> %b
} }
define <4 x float> @ulto4f32(<4 x i64> %a) { define <4 x float> @ulto4f32(<4 x i64> %a) {
; NODQ-LABEL: ulto4f32: ; NOVLDQ-LABEL: ulto4f32:
; NODQ: # %bb.0: ; NOVLDQ: # %bb.0:
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NOVLDQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; NODQ-NEXT: vzeroupper ; NOVLDQ-NEXT: vzeroupper
; NODQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: ulto4f32: ; VLDQ-LABEL: ulto4f32:
; VLDQ: # %bb.0: ; VLDQ: # %bb.0:
; VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0 ; VLDQ-NEXT: vcvtuqq2ps %ymm0, %xmm0
; VLDQ-NEXT: vzeroupper ; VLDQ-NEXT: vzeroupper
; VLDQ-NEXT: retq ; VLDQ-NEXT: retq
; ;
; VLNODQ-LABEL: ulto4f32:
; VLNODQ: # %bb.0:
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; VLNODQ-NEXT: vzeroupper
; VLNODQ-NEXT: retq
;
; DQNOVL-LABEL: ulto4f32: ; DQNOVL-LABEL: ulto4f32:
; DQNOVL: # %bb.0: ; DQNOVL: # %bb.0:
; DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; DQNOVL-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; DQNOVL-NEXT: vcvtuqq2ps %zmm0, %ymm0 ; DQNOVL-NEXT: vcvtuqq2ps %zmm0, %ymm0
; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; DQNOVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; DQNOVL-NEXT: vzeroupper ; DQNOVL-NEXT: vzeroupper
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = uitofp <4 x i64> %a to <4 x float> %b = uitofp <4 x i64> %a to <4 x float>
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; ALL-NEXT: vcvtudq2pd %ymm0, %zmm1 ; ALL-NEXT: vcvtudq2pd %ymm0, %zmm1
; ALL-NEXT: vmovaps %zmm2, %zmm0 ; ALL-NEXT: vmovaps %zmm2, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%b = uitofp <16 x i32> %a to <16 x double> %b = uitofp <16 x i32> %a to <16 x double>
ret <16 x double> %b ret <16 x double> %b
} }
define <8 x float> @slto8f32(<8 x i64> %a) { define <8 x float> @slto8f32(<8 x i64> %a) {
; NODQ-LABEL: slto8f32: ; NOVLDQ-LABEL: slto8f32:
; NODQ: # %bb.0: ; NOVLDQ: # %bb.0:
; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm1 ; NOVLDQ-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; NODQ-NEXT: vmovq %xmm1, %rax ; NOVLDQ-NEXT: vmovq %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; NODQ-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NOVLDQ-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NODQ-NEXT: vmovq %xmm2, %rax ; NOVLDQ-NEXT: vmovq %xmm2, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm2, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NOVLDQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm0 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm0
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; NODQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NOVLDQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NODQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: slto8f32: ; VLDQ-LABEL: slto8f32:
; VLDQ: # %bb.0: ; VLDQ: # %bb.0:
; VLDQ-NEXT: vcvtqq2ps %zmm0, %ymm0 ; VLDQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; VLDQ-NEXT: retq ; VLDQ-NEXT: retq
; ;
; VLNODQ-LABEL: slto8f32:
; VLNODQ: # %bb.0:
; VLNODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; VLNODQ-NEXT: vpextrq $1, %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; VLNODQ-NEXT: vmovq %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; VLNODQ-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; VLNODQ-NEXT: vmovq %xmm2, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
; VLNODQ-NEXT: vpextrq $1, %xmm2, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm0
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; VLNODQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; VLNODQ-NEXT: retq
;
; DQNOVL-LABEL: slto8f32: ; DQNOVL-LABEL: slto8f32:
; DQNOVL: # %bb.0: ; DQNOVL: # %bb.0:
; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0 ; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = sitofp <8 x i64> %a to <8 x float> %b = sitofp <8 x i64> %a to <8 x float>
ret <8 x float> %b ret <8 x float> %b
} }
define <16 x float> @slto16f32(<16 x i64> %a) { define <16 x float> @slto16f32(<16 x i64> %a) {
; NODQ-LABEL: slto16f32: ; NOVLDQ-LABEL: slto16f32:
; NODQ: # %bb.0: ; NOVLDQ: # %bb.0:
; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm2 ; NOVLDQ-NEXT: vextracti32x4 $2, %zmm1, %xmm2
; NODQ-NEXT: vpextrq $1, %xmm2, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; NODQ-NEXT: vmovq %xmm2, %rax ; NOVLDQ-NEXT: vmovq %xmm2, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; NODQ-NEXT: vextracti32x4 $3, %zmm1, %xmm3 ; NOVLDQ-NEXT: vextracti32x4 $3, %zmm1, %xmm3
; NODQ-NEXT: vmovq %xmm3, %rax ; NOVLDQ-NEXT: vmovq %xmm3, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm3, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm3, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vmovq %xmm1, %rax ; NOVLDQ-NEXT: vmovq %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm1 ; NOVLDQ-NEXT: vextracti128 $1, %ymm1, %xmm1
; NODQ-NEXT: vmovq %xmm1, %rax ; NOVLDQ-NEXT: vmovq %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; NODQ-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; NOVLDQ-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; NODQ-NEXT: vextractf32x4 $2, %zmm0, %xmm2 ; NOVLDQ-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; NODQ-NEXT: vpextrq $1, %xmm2, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vmovq %xmm2, %rax ; NOVLDQ-NEXT: vmovq %xmm2, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; NODQ-NEXT: vextractf32x4 $3, %zmm0, %xmm3 ; NOVLDQ-NEXT: vextractf32x4 $3, %zmm0, %xmm3
; NODQ-NEXT: vmovq %xmm3, %rax ; NOVLDQ-NEXT: vmovq %xmm3, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm3, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm3, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NOVLDQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 ; NOVLDQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
; NODQ-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; NOVLDQ-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; NODQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; NOVLDQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; NODQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: slto16f32: ; VLDQ-LABEL: slto16f32:
; VLDQ: # %bb.0: ; VLDQ: # %bb.0:
; VLDQ-NEXT: vcvtqq2ps %zmm0, %ymm0 ; VLDQ-NEXT: vcvtqq2ps %zmm0, %ymm0
; VLDQ-NEXT: vcvtqq2ps %zmm1, %ymm1 ; VLDQ-NEXT: vcvtqq2ps %zmm1, %ymm1
; VLDQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; VLDQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; VLDQ-NEXT: retq ; VLDQ-NEXT: retq
; ;
; VLNODQ-LABEL: slto16f32:
; VLNODQ: # %bb.0:
; VLNODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm2
; VLNODQ-NEXT: vpextrq $1, %xmm2, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; VLNODQ-NEXT: vmovq %xmm2, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; VLNODQ-NEXT: vextracti32x4 $3, %zmm1, %xmm3
; VLNODQ-NEXT: vmovq %xmm3, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3]
; VLNODQ-NEXT: vpextrq $1, %xmm3, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; VLNODQ-NEXT: vpextrq $1, %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vmovq %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm1, %xmm1
; VLNODQ-NEXT: vmovq %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3]
; VLNODQ-NEXT: vpextrq $1, %xmm1, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; VLNODQ-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; VLNODQ-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; VLNODQ-NEXT: vpextrq $1, %xmm2, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vmovq %xmm2, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; VLNODQ-NEXT: vextractf32x4 $3, %zmm0, %xmm3
; VLNODQ-NEXT: vmovq %xmm3, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3]
; VLNODQ-NEXT: vpextrq $1, %xmm3, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
; VLNODQ-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; VLNODQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; VLNODQ-NEXT: retq
;
; DQNOVL-LABEL: slto16f32: ; DQNOVL-LABEL: slto16f32:
; DQNOVL: # %bb.0: ; DQNOVL: # %bb.0:
; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0 ; DQNOVL-NEXT: vcvtqq2ps %zmm0, %ymm0
; DQNOVL-NEXT: vcvtqq2ps %zmm1, %ymm1 ; DQNOVL-NEXT: vcvtqq2ps %zmm1, %ymm1
; DQNOVL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; DQNOVL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = sitofp <16 x i64> %a to <16 x float> %b = sitofp <16 x i64> %a to <16 x float>
ret <16 x float> %b ret <16 x float> %b
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; DQNOVL-NEXT: vcvtqq2pd %zmm0, %zmm0 ; DQNOVL-NEXT: vcvtqq2pd %zmm0, %zmm0
; DQNOVL-NEXT: vcvtqq2pd %zmm1, %zmm1 ; DQNOVL-NEXT: vcvtqq2pd %zmm1, %zmm1
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = sitofp <16 x i64> %a to <16 x double> %b = sitofp <16 x i64> %a to <16 x double>
ret <16 x double> %b ret <16 x double> %b
} }
define <8 x float> @ulto8f32(<8 x i64> %a) { define <8 x float> @ulto8f32(<8 x i64> %a) {
; NODQ-LABEL: ulto8f32: ; NOVLDQ-LABEL: ulto8f32:
; NODQ: # %bb.0: ; NOVLDQ: # %bb.0:
; NODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm1 ; NOVLDQ-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; NODQ-NEXT: vmovq %xmm1, %rax ; NOVLDQ-NEXT: vmovq %xmm1, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; NODQ-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NOVLDQ-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NODQ-NEXT: vmovq %xmm2, %rax ; NOVLDQ-NEXT: vmovq %xmm2, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm2, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NOVLDQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm0 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm0
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; NODQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NOVLDQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NODQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: ulto8f32: ; VLDQ-LABEL: ulto8f32:
; VLDQ: # %bb.0: ; VLDQ: # %bb.0:
; VLDQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 ; VLDQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; VLDQ-NEXT: retq ; VLDQ-NEXT: retq
; ;
; VLNODQ-LABEL: ulto8f32:
; VLNODQ: # %bb.0:
; VLNODQ-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; VLNODQ-NEXT: vpextrq $1, %xmm1, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; VLNODQ-NEXT: vmovq %xmm1, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; VLNODQ-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; VLNODQ-NEXT: vmovq %xmm2, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3]
; VLNODQ-NEXT: vpextrq $1, %xmm2, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm0
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; VLNODQ-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; VLNODQ-NEXT: retq
;
; DQNOVL-LABEL: ulto8f32: ; DQNOVL-LABEL: ulto8f32:
; DQNOVL: # %bb.0: ; DQNOVL: # %bb.0:
; DQNOVL-NEXT: vcvtuqq2ps %zmm0, %ymm0 ; DQNOVL-NEXT: vcvtuqq2ps %zmm0, %ymm0
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = uitofp <8 x i64> %a to <8 x float> %b = uitofp <8 x i64> %a to <8 x float>
ret <8 x float> %b ret <8 x float> %b
} }
define <16 x float> @ulto16f32(<16 x i64> %a) { define <16 x float> @ulto16f32(<16 x i64> %a) {
; NODQ-LABEL: ulto16f32: ; NOVLDQ-LABEL: ulto16f32:
; NODQ: # %bb.0: ; NOVLDQ: # %bb.0:
; NODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm2 ; NOVLDQ-NEXT: vextracti32x4 $2, %zmm1, %xmm2
; NODQ-NEXT: vpextrq $1, %xmm2, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3
; NODQ-NEXT: vmovq %xmm2, %rax ; NOVLDQ-NEXT: vmovq %xmm2, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; NODQ-NEXT: vextracti32x4 $3, %zmm1, %xmm3 ; NOVLDQ-NEXT: vextracti32x4 $3, %zmm1, %xmm3
; NODQ-NEXT: vmovq %xmm3, %rax ; NOVLDQ-NEXT: vmovq %xmm3, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm3, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm3, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vmovq %xmm1, %rax ; NOVLDQ-NEXT: vmovq %xmm1, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; NODQ-NEXT: vextracti128 $1, %ymm1, %xmm1 ; NOVLDQ-NEXT: vextracti128 $1, %ymm1, %xmm1
; NODQ-NEXT: vmovq %xmm1, %rax ; NOVLDQ-NEXT: vmovq %xmm1, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm1, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1
; NODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; NODQ-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; NOVLDQ-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; NODQ-NEXT: vextractf32x4 $2, %zmm0, %xmm2 ; NOVLDQ-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; NODQ-NEXT: vpextrq $1, %xmm2, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vmovq %xmm2, %rax ; NOVLDQ-NEXT: vmovq %xmm2, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; NODQ-NEXT: vextractf32x4 $3, %zmm0, %xmm3 ; NOVLDQ-NEXT: vextractf32x4 $3, %zmm0, %xmm3
; NODQ-NEXT: vmovq %xmm3, %rax ; NOVLDQ-NEXT: vmovq %xmm3, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm3, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm3, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; NOVLDQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; NODQ-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NOVLDQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-NEXT: vmovq %xmm0, %rax ; NOVLDQ-NEXT: vmovq %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; NODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; NOVLDQ-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; NODQ-NEXT: vpextrq $1, %xmm0, %rax ; NOVLDQ-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0 ; NOVLDQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0
; NODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0] ; NOVLDQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
; NODQ-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; NOVLDQ-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; NODQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; NOVLDQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; NODQ-NEXT: retq ; NOVLDQ-NEXT: retq
; ;
; VLDQ-LABEL: ulto16f32: ; VLDQ-LABEL: ulto16f32:
; VLDQ: # %bb.0: ; VLDQ: # %bb.0:
; VLDQ-NEXT: vcvtuqq2ps %zmm0, %ymm0 ; VLDQ-NEXT: vcvtuqq2ps %zmm0, %ymm0
; VLDQ-NEXT: vcvtuqq2ps %zmm1, %ymm1 ; VLDQ-NEXT: vcvtuqq2ps %zmm1, %ymm1
; VLDQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; VLDQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; VLDQ-NEXT: retq ; VLDQ-NEXT: retq
; ;
; VLNODQ-LABEL: ulto16f32:
; VLNODQ: # %bb.0:
; VLNODQ-NEXT: vextracti32x4 $2, %zmm1, %xmm2
; VLNODQ-NEXT: vpextrq $1, %xmm2, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3
; VLNODQ-NEXT: vmovq %xmm2, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; VLNODQ-NEXT: vextracti32x4 $3, %zmm1, %xmm3
; VLNODQ-NEXT: vmovq %xmm3, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3]
; VLNODQ-NEXT: vpextrq $1, %xmm3, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; VLNODQ-NEXT: vpextrq $1, %xmm1, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vmovq %xmm1, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm1, %xmm1
; VLNODQ-NEXT: vmovq %xmm1, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3]
; VLNODQ-NEXT: vpextrq $1, %xmm1, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; VLNODQ-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; VLNODQ-NEXT: vextractf32x4 $2, %zmm0, %xmm2
; VLNODQ-NEXT: vpextrq $1, %xmm2, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vmovq %xmm2, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; VLNODQ-NEXT: vextractf32x4 $3, %zmm0, %xmm3
; VLNODQ-NEXT: vmovq %xmm3, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3]
; VLNODQ-NEXT: vpextrq $1, %xmm3, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; VLNODQ-NEXT: vextracti128 $1, %ymm0, %xmm0
; VLNODQ-NEXT: vmovq %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3]
; VLNODQ-NEXT: vpextrq $1, %xmm0, %rax
; VLNODQ-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0
; VLNODQ-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
; VLNODQ-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; VLNODQ-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; VLNODQ-NEXT: retq
;
; DQNOVL-LABEL: ulto16f32: ; DQNOVL-LABEL: ulto16f32:
; DQNOVL: # %bb.0: ; DQNOVL: # %bb.0:
; DQNOVL-NEXT: vcvtuqq2ps %zmm0, %ymm0 ; DQNOVL-NEXT: vcvtuqq2ps %zmm0, %ymm0
; DQNOVL-NEXT: vcvtuqq2ps %zmm1, %ymm1 ; DQNOVL-NEXT: vcvtuqq2ps %zmm1, %ymm1
; DQNOVL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; DQNOVL-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; DQNOVL-NEXT: retq ; DQNOVL-NEXT: retq
%b = uitofp <16 x i64> %a to <16 x float> %b = uitofp <16 x i64> %a to <16 x float>
ret <16 x float> %b ret <16 x float> %b
▲ Show 20 Lines • Show All 1,349 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll

Show First 20 Lines • Show All 1,785 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%cmp = icmp eq <4 x i32> %mask, zeroinitializer %cmp = icmp eq <4 x i32> %mask, zeroinitializer
%res = select <4 x i1> %cmp, <4 x i32> %shuf, <4 x i32> zeroinitializer %res = select <4 x i1> %cmp, <4 x i32> %shuf, <4 x i32> zeroinitializer
ret <4 x i32> %res ret <4 x i32> %res
} }
define <4 x i32> @test_16xi32_to_4xi32_perm_mask9(<16 x i32> %vec) { define <4 x i32> @test_16xi32_to_4xi32_perm_mask9(<16 x i32> %vec) {
; CHECK-LABEL: test_16xi32_to_4xi32_perm_mask9: ; CHECK-LABEL: test_16xi32_to_4xi32_perm_mask9:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [12,9,4,10] ; CHECK-NEXT: vmovaps {{.*#+}} xmm1 = [4,1,0,2]
; CHECK-NEXT: vpermps %zmm0, %zmm1, %zmm0 ; CHECK-NEXT: vextractf64x4 $1, %zmm0, %ymm2
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; CHECK-NEXT: vpermps %ymm2, %ymm1, %ymm1
; CHECK-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[2,2,2,3]
; CHECK-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3]
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = shufflevector <16 x i32> %vec, <16 x i32> undef, <4 x i32> <i32 12, i32 9, i32 4, i32 10> %res = shufflevector <16 x i32> %vec, <16 x i32> undef, <4 x i32> <i32 12, i32 9, i32 4, i32 10>
ret <4 x i32> %res ret <4 x i32> %res
} }
define <2 x i64> @test_4xi64_to_2xi64_perm_mask0(<4 x i64> %vec) { define <2 x i64> @test_4xi64_to_2xi64_perm_mask0(<4 x i64> %vec) {
; CHECK-LABEL: test_4xi64_to_2xi64_perm_mask0: ; CHECK-LABEL: test_4xi64_to_2xi64_perm_mask0:
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llvm/test/CodeGen/X86/bitcast-and-setcc-128.ll

Show First 20 Lines • Show All 176 Lines • ▼ Show 20 Lines; AVX512BW-NEXT: retq
ret i16 %res ret i16 %res
} }
define i2 @v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) { define i2 @v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i8> %d) {
; SSE2-LABEL: v2i8: ; SSE2-LABEL: v2i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2-NEXT: pcmpgtb %xmm3, %xmm2 ; SSE2-NEXT: pcmpgtb %xmm3, %xmm2
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,2,1,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; SSE2-NEXT: pand %xmm0, %xmm1 ; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: movmskpd %xmm1, %eax ; SSE2-NEXT: movmskpd %xmm1, %eax
; SSE2-NEXT: # kill: def $al killed $al killed $eax ; SSE2-NEXT: # kill: def $al killed $al killed $eax
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: v2i8: ; SSSE3-LABEL: v2i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; AVX512BW-NEXT: retq
%res = bitcast <2 x i1> %y to i2 %res = bitcast <2 x i1> %y to i2
ret i2 %res ret i2 %res
} }
define i2 @v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d) { define i2 @v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d) {
; SSE2-SSSE3-LABEL: v2i16: ; SSE2-SSSE3-LABEL: v2i16:
; SSE2-SSSE3: # %bb.0: ; SSE2-SSSE3: # %bb.0:
; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2-SSSE3-NEXT: pcmpgtw %xmm3, %xmm2 ; SSE2-SSSE3-NEXT: pcmpgtw %xmm3, %xmm2
; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] ; SSE2-SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,0,2,1,4,5,6,7]
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; SSE2-SSSE3-NEXT: pand %xmm0, %xmm1 ; SSE2-SSSE3-NEXT: pand %xmm0, %xmm1
; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax ; SSE2-SSSE3-NEXT: movmskpd %xmm1, %eax
; SSE2-SSSE3-NEXT: # kill: def $al killed $al killed $eax ; SSE2-SSSE3-NEXT: # kill: def $al killed $al killed $eax
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX12-LABEL: v2i16: ; AVX12-LABEL: v2i16:
; AVX12: # %bb.0: ; AVX12: # %bb.0:
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llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
define i8 @v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> %d) { define i8 @v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x double> %d) {
; SSE-LABEL: v8f64: ; SSE-LABEL: v8f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm8 ; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm9 ; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm10 ; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm11 ; SSE-NEXT: movapd {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: cmpltpd %xmm3, %xmm7 ; SSE-NEXT: cmpltpd %xmm3, %xmm7
; SSE-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm7[0,1,0,2,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm7[0,1,0,2,4,5,6,7]
; SSE-NEXT: cmpltpd %xmm2, %xmm6 ; SSE-NEXT: cmpltpd %xmm2, %xmm6
; SSE-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm6[0,1,0,2,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm6[0,1,0,2,4,5,6,7]
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE-NEXT: cmpltpd %xmm1, %xmm5 ; SSE-NEXT: cmpltpd %xmm1, %xmm5
; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm5[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm5[0,2,2,3,4,5,6,7]
; SSE-NEXT: cmpltpd %xmm0, %xmm4 ; SSE-NEXT: cmpltpd %xmm0, %xmm4
; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm4[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm4[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm11 ; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm11[0,1,0,2,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm11[0,1,0,2,4,5,6,7]
; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm10 ; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm10 = xmm10[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm10[0,1,0,2,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm10[0,1,0,2,4,5,6,7]
; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm9 ; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm9[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm9[0,2,2,3,4,5,6,7]
; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm8 ; SSE-NEXT: cmpltpd {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,2,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,2],xmm0[2,3]
; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm8[0,2,2,3,4,5,6,7] ; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm8[0,2,2,3,4,5,6,7]
; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: packsswb %xmm0, %xmm3 ; SSE-NEXT: packsswb %xmm0, %xmm3
; SSE-NEXT: pmovmskb %xmm3, %eax ; SSE-NEXT: pmovmskb %xmm3, %eax
; SSE-NEXT: # kill: def $al killed $al killed $eax ; SSE-NEXT: # kill: def $al killed $al killed $eax
; SSE-NEXT: retq ; SSE-NEXT: retq
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llvm/test/CodeGen/X86/bitcast-setcc-128.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines; AVX512BW-NEXT: retq
ret i16 %res ret i16 %res
} }
define i2 @v2i8(<2 x i8> %a, <2 x i8> %b) { define i2 @v2i8(<2 x i8> %a, <2 x i8> %b) {
; SSE2-LABEL: v2i8: ; SSE2-LABEL: v2i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pcmpgtb %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2-NEXT: movmskpd %xmm0, %eax ; SSE2-NEXT: movmskpd %xmm0, %eax
; SSE2-NEXT: # kill: def $al killed $al killed $eax ; SSE2-NEXT: # kill: def $al killed $al killed $eax
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: v2i8: ; SSSE3-LABEL: v2i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pcmpgtb %xmm1, %xmm0 ; SSSE3-NEXT: pcmpgtb %xmm1, %xmm0
Show All 30 Lines; AVX512BW-NEXT: retq
%res = bitcast <2 x i1> %x to i2 %res = bitcast <2 x i1> %x to i2
ret i2 %res ret i2 %res
} }
define i2 @v2i16(<2 x i16> %a, <2 x i16> %b) { define i2 @v2i16(<2 x i16> %a, <2 x i16> %b) {
; SSE2-SSSE3-LABEL: v2i16: ; SSE2-SSSE3-LABEL: v2i16:
; SSE2-SSSE3: # %bb.0: ; SSE2-SSSE3: # %bb.0:
; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 ; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0
; SSE2-SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] ; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax ; SSE2-SSSE3-NEXT: movmskpd %xmm0, %eax
; SSE2-SSSE3-NEXT: # kill: def $al killed $al killed $eax ; SSE2-SSSE3-NEXT: # kill: def $al killed $al killed $eax
; SSE2-SSSE3-NEXT: retq ; SSE2-SSSE3-NEXT: retq
; ;
; AVX12-LABEL: v2i16: ; AVX12-LABEL: v2i16:
; AVX12: # %bb.0: ; AVX12: # %bb.0:
; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0
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llvm/test/CodeGen/X86/build-vector-128.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; SSE2-64: # %bb.0: ; SSE2-64: # %bb.0:
; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-64-NEXT: retq ; SSE2-64-NEXT: retq
; ;
; SSE41-64-LABEL: test_buildvector_v4f32: ; SSE41-64-LABEL: test_buildvector_v4f32:
; SSE41-64: # %bb.0: ; SSE41-64: # %bb.0:
; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; SSE41-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; SSE41-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; SSE41-64-NEXT: retq ; SSE41-64-NEXT: retq
; ;
; AVX-32-LABEL: test_buildvector_v4f32: ; AVX-32-LABEL: test_buildvector_v4f32:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0 ; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0
; AVX-32-NEXT: retl ; AVX-32-NEXT: retl
; ;
; AVX-64-LABEL: test_buildvector_v4f32: ; AVX-64-LABEL: test_buildvector_v4f32:
; AVX-64: # %bb.0: ; AVX-64: # %bb.0:
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-64-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; AVX-64-NEXT: retq ; AVX-64-NEXT: retq
%ins0 = insertelement <4 x float> undef, float %a0, i32 0 %ins0 = insertelement <4 x float> undef, float %a0, i32 0
%ins1 = insertelement <4 x float> %ins0, float %a1, i32 1 %ins1 = insertelement <4 x float> %ins0, float %a1, i32 1
%ins2 = insertelement <4 x float> %ins1, float %a2, i32 2 %ins2 = insertelement <4 x float> %ins1, float %a2, i32 2
%ins3 = insertelement <4 x float> %ins2, float %a3, i32 3 %ins3 = insertelement <4 x float> %ins2, float %a3, i32 3
ret <4 x float> %ins3 ret <4 x float> %ins3
} }
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; ;
; SSE41-32-LABEL: PR37502: ; SSE41-32-LABEL: PR37502:
; SSE41-32: # %bb.0: ; SSE41-32: # %bb.0:
; SSE41-32-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] ; SSE41-32-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
; SSE41-32-NEXT: retl ; SSE41-32-NEXT: retl
; ;
; SSE41-64-LABEL: PR37502: ; SSE41-64-LABEL: PR37502:
; SSE41-64: # %bb.0: ; SSE41-64: # %bb.0:
; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; SSE41-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-64-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0] ; SSE41-64-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
; SSE41-64-NEXT: retq ; SSE41-64-NEXT: retq
; ;
; AVX-32-LABEL: PR37502: ; AVX-32-LABEL: PR37502:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0] ; AVX-32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
; AVX-32-NEXT: retl ; AVX-32-NEXT: retl
; ;
; AVX1-64-LABEL: PR37502: ; AVX-64-LABEL: PR37502:
; AVX1-64: # %bb.0: ; AVX-64: # %bb.0:
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-64-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX1-64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] ; AVX-64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; AVX1-64-NEXT: retq ; AVX-64-NEXT: retq
;
; AVX2-64-LABEL: PR37502:
; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
; AVX2-64-NEXT: retq
%i0 = insertelement <4 x float> undef, float %x, i32 0 %i0 = insertelement <4 x float> undef, float %x, i32 0
%i1 = insertelement <4 x float> %i0, float %y, i32 1 %i1 = insertelement <4 x float> %i0, float %y, i32 1
%i2 = insertelement <4 x float> %i1, float %x, i32 2 %i2 = insertelement <4 x float> %i1, float %x, i32 2
%i3 = insertelement <4 x float> %i2, float %y, i32 3 %i3 = insertelement <4 x float> %i2, float %y, i32 3
ret <4 x float> %i3 ret <4 x float> %i3
} }

llvm/test/CodeGen/X86/build-vector-256.ll

Show All 25 Lines
define <8 x float> @test_buildvector_v8f32(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) { define <8 x float> @test_buildvector_v8f32(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7) {
; AVX-32-LABEL: test_buildvector_v8f32: ; AVX-32-LABEL: test_buildvector_v8f32:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %ymm0 ; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %ymm0
; AVX-32-NEXT: retl ; AVX-32-NEXT: retl
; ;
; AVX-64-LABEL: test_buildvector_v8f32: ; AVX-64-LABEL: test_buildvector_v8f32:
; AVX-64: # %bb.0: ; AVX-64: # %bb.0:
; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3] ; AVX-64-NEXT: vunpcklps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3] ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm4 = xmm4[0],xmm6[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0] ; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-64-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; AVX-64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX-64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX-64-NEXT: retq ; AVX-64-NEXT: retq
%ins0 = insertelement <8 x float> undef, float %a0, i32 0 %ins0 = insertelement <8 x float> undef, float %a0, i32 0
%ins1 = insertelement <8 x float> %ins0, float %a1, i32 1 %ins1 = insertelement <8 x float> %ins0, float %a1, i32 1
%ins2 = insertelement <8 x float> %ins1, float %a2, i32 2 %ins2 = insertelement <8 x float> %ins1, float %a2, i32 2
%ins3 = insertelement <8 x float> %ins2, float %a3, i32 3 %ins3 = insertelement <8 x float> %ins2, float %a3, i32 3
%ins4 = insertelement <8 x float> %ins3, float %a4, i32 4 %ins4 = insertelement <8 x float> %ins3, float %a4, i32 4
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llvm/test/CodeGen/X86/build-vector-512.ll

Show All 33 Lines
define <16 x float> @test_buildvector_v16f32(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15) { define <16 x float> @test_buildvector_v16f32(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15) {
; AVX-32-LABEL: test_buildvector_v16f32: ; AVX-32-LABEL: test_buildvector_v16f32:
; AVX-32: # %bb.0: ; AVX-32: # %bb.0:
; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm0 ; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %zmm0
; AVX-32-NEXT: retl ; AVX-32-NEXT: retl
; ;
; AVX-64-LABEL: test_buildvector_v16f32: ; AVX-64-LABEL: test_buildvector_v16f32:
; AVX-64: # %bb.0: ; AVX-64: # %bb.0:
; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3] ; AVX-64-NEXT: vmovss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3] ; AVX-64-NEXT: vmovss {{.*#+}} xmm9 = mem[0],zero,zero,zero
; AVX-64-NEXT: vunpcklps {{.*#+}} xmm8 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
; AVX-64-NEXT: vmovss {{.*#+}} xmm9 = mem[0],zero,zero,zero
; AVX-64-NEXT: vmovlhps {{.*#+}} xmm8 = xmm8[0],xmm9[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm8 = xmm8[0,1,2],mem[0]
; AVX-64-NEXT: vmovss {{.*#+}} xmm9 = mem[0],zero,zero,zero
; AVX-64-NEXT: vmovss {{.*#+}} xmm10 = mem[0],zero,zero,zero
; AVX-64-NEXT: vunpcklps {{.*#+}} xmm9 = xmm10[0],xmm9[0],xmm10[1],xmm9[1]
; AVX-64-NEXT: vmovss {{.*#+}} xmm10 = mem[0],zero,zero,zero
; AVX-64-NEXT: vmovlhps {{.*#+}} xmm9 = xmm9[0],xmm10[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm9 = xmm9[0,1,2],mem[0]
; AVX-64-NEXT: vinsertf128 $1, %xmm9, %ymm8, %ymm8
; AVX-64-NEXT: vunpcklps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; AVX-64-NEXT: vmovlhps {{.*#+}} xmm4 = xmm4[0],xmm6[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0] ; AVX-64-NEXT: vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; AVX-64-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; AVX-64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX-64-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX-64-NEXT: vinsertf64x4 $1, %ymm8, %zmm0, %zmm0
; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX-64-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-64-NEXT: retq ; AVX-64-NEXT: retq
%ins0 = insertelement <16 x float> undef, float %a0, i32 0 %ins0 = insertelement <16 x float> undef, float %a0, i32 0
%ins1 = insertelement <16 x float> %ins0, float %a1, i32 1 %ins1 = insertelement <16 x float> %ins0, float %a1, i32 1
%ins2 = insertelement <16 x float> %ins1, float %a2, i32 2 %ins2 = insertelement <16 x float> %ins1, float %a2, i32 2
%ins3 = insertelement <16 x float> %ins2, float %a3, i32 3 %ins3 = insertelement <16 x float> %ins2, float %a3, i32 3
%ins4 = insertelement <16 x float> %ins3, float %a4, i32 4 %ins4 = insertelement <16 x float> %ins3, float %a4, i32 4
%ins5 = insertelement <16 x float> %ins4, float %a5, i32 5 %ins5 = insertelement <16 x float> %ins4, float %a5, i32 5
%ins6 = insertelement <16 x float> %ins5, float %a6, i32 6 %ins6 = insertelement <16 x float> %ins5, float %a6, i32 6
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llvm/test/CodeGen/X86/buildvec-extract.ll

Show First 20 Lines • Show All 398 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; SSE-LABEL: extract1_i16_zext_insert0_i64_undef: ; SSE-LABEL: extract1_i16_zext_insert0_i64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,0]
; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: extract1_i16_zext_insert0_i64_undef: ; AVX-LABEL: extract1_i16_zext_insert0_i64_undef:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,0]
; AVX-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX-NEXT: retq ; AVX-NEXT: retq
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
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%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; SSE2-LABEL: extract3_i16_zext_insert1_i64_undef: ; SSE2-LABEL: extract3_i16_zext_insert1_i64_undef:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] ; SSE2-NEXT: psrlq $48, %xmm0
; SSE2-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] ; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: extract3_i16_zext_insert1_i64_undef: ; SSE41-LABEL: extract3_i16_zext_insert1_i64_undef:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13] ; SSE41-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
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llvm/test/CodeGen/X86/buildvec-insertvec.ll

Show All 38 Lines
} }
; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a ; Verify that the DAGCombiner doesn't wrongly fold a build_vector into a
; blend with a zero vector if the build_vector contains negative zero. ; blend with a zero vector if the build_vector contains negative zero.
define <4 x float> @test_negative_zero_1(<4 x float> %A) { define <4 x float> @test_negative_zero_1(<4 x float> %A) {
; SSE2-LABEL: test_negative_zero_1: ; SSE2-LABEL: test_negative_zero_1:
; SSE2: # %bb.0: # %entry ; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_negative_zero_1: ; SSE41-LABEL: test_negative_zero_1:
; SSE41: # %bb.0: # %entry ; SSE41: # %bb.0: # %entry
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero
; SSE41-NEXT: retq ; SSE41-NEXT: retq
entry: entry:
Show All 30 Lines
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_buildvector_v4f32_register: ; SSE41-LABEL: test_buildvector_v4f32_register:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
%ins0 = insertelement <4 x float> undef, float %f0, i32 0 %ins0 = insertelement <4 x float> undef, float %f0, i32 0
%ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1
%ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2
%ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3
ret <4 x float> %ins3 ret <4 x float> %ins3
} }
define <4 x float> @test_buildvector_v4f32_load(float* %p0, float* %p1, float* %p2, float* %p3) { define <4 x float> @test_buildvector_v4f32_load(float* %p0, float* %p1, float* %p2, float* %p3) {
; SSE2-LABEL: test_buildvector_v4f32_load: ; SSE2-LABEL: test_buildvector_v4f32_load:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_buildvector_v4f32_load: ; SSE41-LABEL: test_buildvector_v4f32_load:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
%f0 = load float, float* %p0, align 4 %f0 = load float, float* %p0, align 4
%f1 = load float, float* %p1, align 4 %f1 = load float, float* %p1, align 4
%f2 = load float, float* %p2, align 4 %f2 = load float, float* %p2, align 4
%f3 = load float, float* %p3, align 4 %f3 = load float, float* %p3, align 4
%ins0 = insertelement <4 x float> undef, float %f0, i32 0 %ins0 = insertelement <4 x float> undef, float %f0, i32 0
%ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1
%ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2
%ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3
ret <4 x float> %ins3 ret <4 x float> %ins3
} }
define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, float %f2, float* %p3) { define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, float %f2, float* %p3) {
; SSE2-LABEL: test_buildvector_v4f32_partial_load: ; SSE2-LABEL: test_buildvector_v4f32_partial_load:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: test_buildvector_v4f32_partial_load: ; SSE41-LABEL: test_buildvector_v4f32_partial_load:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
%f3 = load float, float* %p3, align 4 %f3 = load float, float* %p3, align 4
%ins0 = insertelement <4 x float> undef, float %f0, i32 0 %ins0 = insertelement <4 x float> undef, float %f0, i32 0
%ins1 = insertelement <4 x float> %ins0, float %f1, i32 1 %ins1 = insertelement <4 x float> %ins0, float %f1, i32 1
%ins2 = insertelement <4 x float> %ins1, float %f2, i32 2 %ins2 = insertelement <4 x float> %ins1, float %f2, i32 2
%ins3 = insertelement <4 x float> %ins2, float %f3, i32 3 %ins3 = insertelement <4 x float> %ins2, float %f3, i32 3
ret <4 x float> %ins3 ret <4 x float> %ins3
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4 %ins4 = insertelement <8 x i16> %ins3, i16 %a4, i32 4
%ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5 %ins5 = insertelement <8 x i16> %ins4, i16 %a5, i32 5
%ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6 %ins6 = insertelement <8 x i16> %ins5, i16 0, i32 6
%ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7 %ins7 = insertelement <8 x i16> %ins6, i16 0, i32 7
ret <8 x i16> %ins7 ret <8 x i16> %ins7
} }
define <8 x i16> @test_buildvector_v8i16_register_zero_2(i16 %a1, i16 %a3, i16 %a4, i16 %a5) { define <8 x i16> @test_buildvector_v8i16_register_zero_2(i16 %a1, i16 %a3, i16 %a4, i16 %a5) {
; CHECK-LABEL: test_buildvector_v8i16_register_zero_2: ; CHECK-LABEL: test_buildvector_v8i16_register_zero_2:
xbolva00Unsubmitted
Not Done
ReplyInline Actions

Extra instructio (vs sse2)

xbolva00: Extra instructio (vs sse2)
RKSimonAuthorUnsubmitted
Not Done
ReplyInline Actions

The original vzext_movl (which isel would consume into the movd) has been replaced with a zero_extend_vector_inreg.

RKSimon: The original vzext_movl (which isel would consume into the movd) has been replaced with a…
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pxor %xmm0, %xmm0 ; CHECK-NEXT: pxor %xmm0, %xmm0
; CHECK-NEXT: pinsrw $1, %edi, %xmm0 ; CHECK-NEXT: pinsrw $1, %edi, %xmm0
; CHECK-NEXT: pinsrw $3, %esi, %xmm0 ; CHECK-NEXT: pinsrw $3, %esi, %xmm0
; CHECK-NEXT: pinsrw $4, %edx, %xmm0 ; CHECK-NEXT: pinsrw $4, %edx, %xmm0
; CHECK-NEXT: pinsrw $5, %ecx, %xmm0 ; CHECK-NEXT: pinsrw $5, %ecx, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ins0 = insertelement <8 x i16> undef, i16 0, i32 0 %ins0 = insertelement <8 x i16> undef, i16 0, i32 0
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llvm/test/CodeGen/X86/combine-fcopysign.ll

Show First 20 Lines • Show All 260 Lines • ▼ Show 20 Lines
; SSE-NEXT: orps %xmm7, %xmm3 ; SSE-NEXT: orps %xmm7, %xmm3
; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm0[1,1,3,3] ; SSE-NEXT: movshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
; SSE-NEXT: andps %xmm4, %xmm5 ; SSE-NEXT: andps %xmm4, %xmm5
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: cvtsd2ss %xmm1, %xmm1 ; SSE-NEXT: cvtsd2ss %xmm1, %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: orps %xmm5, %xmm1 ; SSE-NEXT: orps %xmm5, %xmm1
; SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; SSE-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm6[0],xmm3[3] ; SSE-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm6[0]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3] ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE-NEXT: andps %xmm4, %xmm0 ; SSE-NEXT: andps %xmm4, %xmm0
; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1] ; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
; SSE-NEXT: xorps %xmm1, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cvtsd2ss %xmm2, %xmm1 ; SSE-NEXT: cvtsd2ss %xmm2, %xmm1
; SSE-NEXT: andnps %xmm1, %xmm4 ; SSE-NEXT: andnps %xmm1, %xmm4
; SSE-NEXT: orps %xmm0, %xmm4 ; SSE-NEXT: orps %xmm0, %xmm4
; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0] ; SSE-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
Show All 21 Lines

llvm/test/CodeGen/X86/combine-sdiv.ll

Show First 20 Lines • Show All 1,975 Lines • ▼ Show 20 Lines; XOP-NEXT: retq
%1 = sdiv <8 x i64> %x, <i64 1, i64 4, i64 8, i64 16, i64 1, i64 4, i64 8, i64 16> %1 = sdiv <8 x i64> %x, <i64 1, i64 4, i64 8, i64 16, i64 1, i64 4, i64 8, i64 16>
ret <8 x i64> %1 ret <8 x i64> %1
} }
define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) { define <4 x i32> @combine_vec_sdiv_by_pow2b_PosAndNeg(<4 x i32> %x) {
; SSE2-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg: ; SSE2-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $31, %xmm0 ; SSE2-NEXT: psrad $31, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrld $28, %xmm2 ; SSE2-NEXT: psrld $28, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: psrld $29, %xmm3 ; SSE2-NEXT: psrld $29, %xmm3
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1] ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1]
; SSE2-NEXT: psrld $30, %xmm0 ; SSE2-NEXT: psrld $30, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0,3]
; SSE2-NEXT: paddd %xmm1, %xmm0 ; SSE2-NEXT: paddd %xmm0, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm1, %xmm2
; SSE2-NEXT: psrad $4, %xmm2 ; SSE2-NEXT: psrad $2, %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: movdqa %xmm1, %xmm3
; SSE2-NEXT: psrad $3, %xmm3 ; SSE2-NEXT: psrad $4, %xmm3
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1] ; SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm2[0],xmm3[1]
; SSE2-NEXT: psrad $2, %xmm0 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0,3] ; SSE2-NEXT: psubd %xmm3, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: psrad $3, %xmm1
; SSE2-NEXT: psubd %xmm0, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg: ; SSE41-LABEL: combine_vec_sdiv_by_pow2b_PosAndNeg:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa %xmm0, %xmm1 ; SSE41-NEXT: movdqa %xmm0, %xmm1
; SSE41-NEXT: psrad $31, %xmm1 ; SSE41-NEXT: psrad $31, %xmm1
; SSE41-NEXT: movdqa %xmm1, %xmm2 ; SSE41-NEXT: movdqa %xmm1, %xmm2
; SSE41-NEXT: psrld $28, %xmm2 ; SSE41-NEXT: psrld $28, %xmm2
▲ Show 20 Lines • Show All 1,221 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/combine-shl.ll

Show First 20 Lines • Show All 408 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5> %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
ret <4 x i32> %2 ret <4 x i32> %2
} }
define <4 x i32> @combine_vec_shl_ge_ashr_extact1(<4 x i32> %x) { define <4 x i32> @combine_vec_shl_ge_ashr_extact1(<4 x i32> %x) {
; SSE2-LABEL: combine_vec_shl_ge_ashr_extact1: ; SSE2-LABEL: combine_vec_shl_ge_ashr_extact1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $5, %xmm1 ; SSE2-NEXT: psrad $3, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrad $3, %xmm2 ; SSE2-NEXT: psrad $5, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[2,3] ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $8, %xmm1 ; SSE2-NEXT: psrad $8, %xmm1
; SSE2-NEXT: psrad $4, %xmm0 ; SSE2-NEXT: psrad $4, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [32,64,128,256] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [32,64,128,256]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm0, %xmm3 ; SSE2-NEXT: pmuludq %xmm0, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3> %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
ret <4 x i32> %2 ret <4 x i32> %2
} }
define <4 x i32> @combine_vec_shl_lt_ashr_extact1(<4 x i32> %x) { define <4 x i32> @combine_vec_shl_lt_ashr_extact1(<4 x i32> %x) {
; SSE2-LABEL: combine_vec_shl_lt_ashr_extact1: ; SSE2-LABEL: combine_vec_shl_lt_ashr_extact1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $7, %xmm1 ; SSE2-NEXT: psrad $5, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrad $5, %xmm2 ; SSE2-NEXT: psrad $7, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[2,3] ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrad $8, %xmm1 ; SSE2-NEXT: psrad $8, %xmm1
; SSE2-NEXT: psrad $6, %xmm0 ; SSE2-NEXT: psrad $6, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8,16,32,256] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8,16,32,256]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm0, %xmm3 ; SSE2-NEXT: pmuludq %xmm0, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5> %2 = shl <4 x i32> %1, <i32 5, i32 5, i32 5, i32 5>
ret <4 x i32> %2 ret <4 x i32> %2
} }
define <4 x i32> @combine_vec_shl_gt_lshr1(<4 x i32> %x) { define <4 x i32> @combine_vec_shl_gt_lshr1(<4 x i32> %x) {
; SSE2-LABEL: combine_vec_shl_gt_lshr1: ; SSE2-LABEL: combine_vec_shl_gt_lshr1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $5, %xmm1 ; SSE2-NEXT: psrld $3, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrld $3, %xmm2 ; SSE2-NEXT: psrld $5, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[2,3] ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $8, %xmm1 ; SSE2-NEXT: psrld $8, %xmm1
; SSE2-NEXT: psrld $4, %xmm0 ; SSE2-NEXT: psrld $4, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [32,64,128,256] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [32,64,128,256]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm0, %xmm3 ; SSE2-NEXT: pmuludq %xmm0, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3> %2 = shl <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
ret <4 x i32> %2 ret <4 x i32> %2
} }
define <4 x i32> @combine_vec_shl_le_lshr1(<4 x i32> %x) { define <4 x i32> @combine_vec_shl_le_lshr1(<4 x i32> %x) {
; SSE2-LABEL: combine_vec_shl_le_lshr1: ; SSE2-LABEL: combine_vec_shl_le_lshr1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $7, %xmm1 ; SSE2-NEXT: psrld $5, %xmm1
; SSE2-NEXT: movdqa %xmm0, %xmm2 ; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: psrld $5, %xmm2 ; SSE2-NEXT: psrld $7, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[2,3] ; SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrld $8, %xmm1 ; SSE2-NEXT: psrld $8, %xmm1
; SSE2-NEXT: psrld $6, %xmm0 ; SSE2-NEXT: psrld $6, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[3,3]
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8,16,32,256] ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8,16,32,256]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE2-NEXT: pmuludq %xmm0, %xmm3 ; SSE2-NEXT: pmuludq %xmm0, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
▲ Show 20 Lines • Show All 317 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/combine-sra.ll

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; AVX2-SLOW-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-SLOW-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-SLOW-NEXT: vzeroupper ; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: combine_vec_ashr_trunc_lshr: ; AVX2-FAST-LABEL: combine_vec_ashr_trunc_lshr:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpsrlq $32, %ymm0, %ymm0 ; AVX2-FAST-NEXT: vmovdqa {{.*#+}} xmm1 = [1,3,5,7]
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm1 = [0,2,4,6,4,6,6,7]
; AVX2-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm0 ; AVX2-FAST-NEXT: vpermd %ymm0, %ymm1, %ymm0
; AVX2-FAST-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-FAST-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-FAST-NEXT: vzeroupper ; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
%1 = lshr <4 x i64> %x, <i64 32, i64 32, i64 32, i64 32> %1 = lshr <4 x i64> %x, <i64 32, i64 32, i64 32, i64 32>
%2 = trunc <4 x i64> %1 to <4 x i32> %2 = trunc <4 x i64> %1 to <4 x i32>
%3 = ashr <4 x i32> %2, <i32 0, i32 1, i32 2, i32 3> %3 = ashr <4 x i32> %2, <i32 0, i32 1, i32 2, i32 3>
ret <4 x i32> %3 ret <4 x i32> %3
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll

Show First 20 Lines • Show All 584 Lines • ▼ Show 20 Lines
; X86-NEXT: cltd ; X86-NEXT: cltd
; X86-NEXT: idivl %esi ; X86-NEXT: idivl %esi
; X86-NEXT: movd %eax, %xmm5 ; X86-NEXT: movd %eax, %xmm5
; X86-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; X86-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; X86-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0] ; X86-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
; X86-NEXT: movdqa %xmm4, (%ecx) ; X86-NEXT: movdqa %xmm4, (%ecx)
; X86-NEXT: pmuludq %xmm1, %xmm4 ; X86-NEXT: pmuludq %xmm1, %xmm4
; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3]
; X86-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm2[0,0] ; X86-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-NEXT: pmuludq %xmm5, %xmm1 ; X86-NEXT: pmuludq %xmm5, %xmm1
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; X86-NEXT: psubd %xmm3, %xmm0 ; X86-NEXT: psubd %xmm3, %xmm0
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
Show All 26 Lines
; X64-NEXT: cltd ; X64-NEXT: cltd
; X64-NEXT: idivl %ecx ; X64-NEXT: idivl %ecx
; X64-NEXT: movd %eax, %xmm5 ; X64-NEXT: movd %eax, %xmm5
; X64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; X64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; X64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0] ; X64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
; X64-NEXT: movdqa %xmm4, (%rdi) ; X64-NEXT: movdqa %xmm4, (%rdi)
; X64-NEXT: pmuludq %xmm1, %xmm4 ; X64-NEXT: pmuludq %xmm1, %xmm4
; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3]
; X64-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm2[0,0] ; X64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X64-NEXT: pmuludq %xmm5, %xmm1 ; X64-NEXT: pmuludq %xmm5, %xmm1
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; X64-NEXT: psubd %xmm3, %xmm0 ; X64-NEXT: psubd %xmm3, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%div = sdiv <4 x i32> %x, %y %div = sdiv <4 x i32> %x, %y
store <4 x i32> %div, <4 x i32>* %divdst, align 16 store <4 x i32> %div, <4 x i32>* %divdst, align 16
▲ Show 20 Lines • Show All 272 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll

Show First 20 Lines • Show All 584 Lines • ▼ Show 20 Lines
; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edx, %edx
; X86-NEXT: divl %esi ; X86-NEXT: divl %esi
; X86-NEXT: movd %eax, %xmm5 ; X86-NEXT: movd %eax, %xmm5
; X86-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; X86-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; X86-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0] ; X86-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
; X86-NEXT: movdqa %xmm4, (%ecx) ; X86-NEXT: movdqa %xmm4, (%ecx)
; X86-NEXT: pmuludq %xmm1, %xmm4 ; X86-NEXT: pmuludq %xmm1, %xmm4
; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; X86-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3]
; X86-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm2[0,0] ; X86-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-NEXT: pmuludq %xmm5, %xmm1 ; X86-NEXT: pmuludq %xmm5, %xmm1
; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; X86-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; X86-NEXT: psubd %xmm3, %xmm0 ; X86-NEXT: psubd %xmm3, %xmm0
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
Show All 26 Lines
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divl %ecx ; X64-NEXT: divl %ecx
; X64-NEXT: movd %eax, %xmm5 ; X64-NEXT: movd %eax, %xmm5
; X64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] ; X64-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
; X64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0] ; X64-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm3[0]
; X64-NEXT: movdqa %xmm4, (%rdi) ; X64-NEXT: movdqa %xmm4, (%rdi)
; X64-NEXT: pmuludq %xmm1, %xmm4 ; X64-NEXT: pmuludq %xmm1, %xmm4
; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3]
; X64-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm2[0,0] ; X64-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X64-NEXT: pmuludq %xmm5, %xmm1 ; X64-NEXT: pmuludq %xmm5, %xmm1
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; X64-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; X64-NEXT: psubd %xmm3, %xmm0 ; X64-NEXT: psubd %xmm3, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%div = udiv <4 x i32> %x, %y %div = udiv <4 x i32> %x, %y
store <4 x i32> %div, <4 x i32>* %divdst, align 16 store <4 x i32> %div, <4 x i32>* %divdst, align 16
▲ Show 20 Lines • Show All 272 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fma.ll

Show First 20 Lines • Show All 350 Lines • ▼ Show 20 Lines
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x4c,0x24,0x04,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x4c,0x24,0x04,0x02]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x30]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x54]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x30] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x30]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x20] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x20]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x54]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x30]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x30] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x30]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x20]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x1c] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x18]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x54] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x54]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x18] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x1c]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x60]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x14] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x14]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x10] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x10]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfa,0x10,0x44,0x24,0x1c] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfa,0x10,0x44,0x24,0x18]
; FMACALL32_BDVER2-NEXT: ## xmm0 = mem[0],zero,zero,zero ; FMACALL32_BDVER2-NEXT: ## xmm0 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $16, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x18,0x10] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x1c]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[2,3] ; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $32, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x14,0x20] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x14]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1],mem[0],xmm0[3] ; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vunpcklps %xmm0, %xmm1, %xmm0 ## encoding: [0xc5,0xf0,0x14,0xc0]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL32_BDVER2-NEXT: vmovlhps %xmm2, %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x16,0xc2]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0],xmm2[0]
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x10,0x30] ; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x10,0x30]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1,2],mem[0] ; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1,2],mem[0]
; FMACALL32_BDVER2-NEXT: addl $108, %esp ## encoding: [0x83,0xc4,0x6c] ; FMACALL32_BDVER2-NEXT: addl $108, %esp ## encoding: [0x83,0xc4,0x6c]
; FMACALL32_BDVER2-NEXT: retl ## encoding: [0xc3] ; FMACALL32_BDVER2-NEXT: retl ## encoding: [0xc3]
entry: entry:
%call = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) %call = call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
ret <4 x float> %call ret <4 x float> %call
} }
▲ Show 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xb4,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xb4,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x50]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xa8,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x50] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x50]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xa8,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x50]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x9c,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x9c,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0x00,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0x00,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xe0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xe0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
Show All 15 Lines
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x84,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x84,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0x00,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0x00,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xe0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xe0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x01] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x78] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x78]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0x00,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0x00,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xe0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xe0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x10,0x84,0x24,0xc0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x01]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x50] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x54,0x24,0x50]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x78] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x78]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x84,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x84,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x90,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x90,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x30] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x30]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x9c,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x9c,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x2c] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x28]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xa8,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xa8,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x28] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x2c]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xb4,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xb4,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x24] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x24]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x20] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x20]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfa,0x10,0x44,0x24,0x3c] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfa,0x10,0x44,0x24,0x38]
; FMACALL32_BDVER2-NEXT: ## xmm0 = mem[0],zero,zero,zero ; FMACALL32_BDVER2-NEXT: ## xmm0 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $16, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x38,0x10] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x3c]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[2,3] ; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x2c] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x2c]
; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm3 ## encoding: [0xc5,0xfa,0x10,0x5c,0x24,0x24]
; FMACALL32_BDVER2-NEXT: ## xmm3 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vunpcklps %xmm0, %xmm1, %xmm0 ## encoding: [0xc5,0xf0,0x14,0xc0]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x34]
; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vmovlhps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x16,0xc1]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0],xmm1[0]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x28]
; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero ; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $16, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x28,0x10]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0],mem[0],xmm1[2,3]
; FMACALL32_BDVER2-NEXT: vinsertps $32, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x34,0x20]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1],mem[0],xmm0[3]
; FMACALL32_BDVER2-NEXT: vinsertps $32, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x24,0x20]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1],mem[0],xmm1[3]
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x30,0x30] ; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x30,0x30]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1,2],mem[0] ; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1,2],mem[0]
; FMACALL32_BDVER2-NEXT: vunpcklps %xmm1, %xmm2, %xmm1 ## encoding: [0xc5,0xe8,0x14,0xc9]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; FMACALL32_BDVER2-NEXT: vmovlhps %xmm3, %xmm1, %xmm1 ## encoding: [0xc5,0xf0,0x16,0xcb]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0],xmm3[0]
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x20,0x30] ; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x20,0x30]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1,2],mem[0] ; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1,2],mem[0]
; FMACALL32_BDVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x18,0xc1,0x01] ; FMACALL32_BDVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x18,0xc1,0x01]
; FMACALL32_BDVER2-NEXT: addl $316, %esp ## encoding: [0x81,0xc4,0x3c,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: addl $316, %esp ## encoding: [0x81,0xc4,0x3c,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: ## imm = 0x13C ; FMACALL32_BDVER2-NEXT: ## imm = 0x13C
; FMACALL32_BDVER2-NEXT: retl ## encoding: [0xc3] ; FMACALL32_BDVER2-NEXT: retl ## encoding: [0xc3]
entry: entry:
%call = call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c) %call = call <8 x float> @llvm.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c)
▲ Show 20 Lines • Show All 318 Lines • ▼ Show 20 Lines
; FMACALL32_BDVER2: ## %bb.0: ## %entry ; FMACALL32_BDVER2: ## %bb.0: ## %entry
; FMACALL32_BDVER2-NEXT: pushl %ebp ## encoding: [0x55] ; FMACALL32_BDVER2-NEXT: pushl %ebp ## encoding: [0x55]
; FMACALL32_BDVER2-NEXT: movl %esp, %ebp ## encoding: [0x89,0xe5] ; FMACALL32_BDVER2-NEXT: movl %esp, %ebp ## encoding: [0x89,0xe5]
; FMACALL32_BDVER2-NEXT: andl $-32, %esp ## encoding: [0x83,0xe4,0xe0] ; FMACALL32_BDVER2-NEXT: andl $-32, %esp ## encoding: [0x83,0xe4,0xe0]
; FMACALL32_BDVER2-NEXT: subl $448, %esp ## encoding: [0x81,0xec,0xc0,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: subl $448, %esp ## encoding: [0x81,0xec,0xc0,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: ## imm = 0x1C0 ; FMACALL32_BDVER2-NEXT: ## imm = 0x1C0
; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm4 ## encoding: [0xc5,0xf8,0x28,0x65,0x38] ; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm4 ## encoding: [0xc5,0xf8,0x28,0x65,0x38]
; FMACALL32_BDVER2-NEXT: vmovaps %ymm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %ymm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x94,0x24,0x60,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x94,0x24,0x80,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm3, %xmm2 ## encoding: [0xc4,0xe3,0x7d,0x19,0xda,0x01] ; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm3, %xmm2 ## encoding: [0xc4,0xe3,0x7d,0x19,0xda,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps %ymm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %ymm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x8c,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x4c,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm1, %xmm1 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc9,0x01] ; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm1, %xmm1 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc9,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps %ymm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %ymm3, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x5c,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x9c,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 32-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x84,0x24,0x80,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x29,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x02]
; FMACALL32_BDVER2-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x8c,0x24,0xb0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x8c,0x24,0xb0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm4, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x64,0x24,0x08,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm4, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x64,0x24,0x08,0x02]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x54,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x54,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xc0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xb0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x48,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38] ; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x48,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xc0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0xb0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28] ; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x3c,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x3c,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28] ; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x30,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x30,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x02]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28] ; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x24,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x24,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x01] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28] ; FMACALL32_BDVER2-NEXT: vmovaps 40(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x28]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x18,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x18,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x01]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18] ; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x0c,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x0c,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc0,0x01] ; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc0,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x84,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc0,0x01] ; FMACALL32_BDVER2-NEXT: vextractf128 $1, %ymm0, %xmm0 ## encoding: [0xc4,0xe3,0x7d,0x19,0xc0,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; FMACALL32_BDVER2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x44,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x29,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x00,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x00,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18] ; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x02]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x02]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xf4,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xf4,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xe8,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18] ; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x4c,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x01]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 24(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x18]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xe8,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x84,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x44,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08] ; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x03]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x03]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08] ; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x7c,0x24,0x60]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x02]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x02]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02] ; FMACALL32_BDVER2-NEXT: vextractps $2, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x02]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08] ; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xdc,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xdc,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x01] ; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08] ; FMACALL32_BDVER2-NEXT: vmovaps 8(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x08]
; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill ; FMACALL32_BDVER2-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Spill
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xd0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xbc,0x24,0xd0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x08] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc5,0xfa,0x11,0x44,0x24,0x04]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x80,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovss %xmm0, (%esp) ## encoding: [0xc5,0xfa,0x11,0x04,0x24] ; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x04,0x01]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 ## 32-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x84,0x24,0x60,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $1, %xmm0, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x04,0x24,0x01]
; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77] ; FMACALL32_BDVER2-NEXT: vzeroupper ## encoding: [0xc5,0xf8,0x77]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38] ; FMACALL32_BDVER2-NEXT: vmovaps 56(%ebp), %xmm0 ## encoding: [0xc5,0xf8,0x28,0x45,0x38]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0xc0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x94,0x24,0xc0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload ; FMACALL32_BDVER2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x8c,0x24,0xb0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x44,0x24,0x08,0x03]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm2, {{[0-9]+}}(%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x54,0x24,0x04,0x03]
; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03] ; FMACALL32_BDVER2-NEXT: vextractps $3, %xmm1, (%esp) ## encoding: [0xc4,0xe3,0x79,0x17,0x0c,0x24,0x03]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xd0,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xd0,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x38] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x3c]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xdc,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xdc,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x34]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x60] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0x6c,0x24,0x60]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x30] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x30]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x80,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x80,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x2c] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x28]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xe8,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xe8,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x28] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x2c]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xf4,0x00,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0xf4,0x00,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x24] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x24]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x00,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x00,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x20] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x20]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x0c,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x0c,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x5c] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x58]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x18,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x18,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x58] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x5c]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x24,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x24,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x54] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x54]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x30,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x30,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x50] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x50]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x3c,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x3c,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x4c] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x48]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x48,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x48,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x48] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x4c]
; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload ; FMACALL32_BDVER2-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) ## 10-byte Folded Reload
; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x54,0x01,0x00,0x00] ; FMACALL32_BDVER2-NEXT: ## encoding: [0xdb,0xac,0x24,0x54,0x01,0x00,0x00]
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x44] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x44]
; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A] ; FMACALL32_BDVER2-NEXT: calll _fmaf ## encoding: [0xe8,A,A,A,A]
; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4 ; FMACALL32_BDVER2-NEXT: ## fixup A - offset: 1, value: _fmaf-4, kind: FK_PCRel_4
; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x40] ; FMACALL32_BDVER2-NEXT: fstps {{[0-9]+}}(%esp) ## encoding: [0xd9,0x5c,0x24,0x40]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfa,0x10,0x44,0x24,0x3c] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 ## encoding: [0xc5,0xfa,0x10,0x44,0x24,0x38]
; FMACALL32_BDVER2-NEXT: ## xmm0 = mem[0],zero,zero,zero ; FMACALL32_BDVER2-NEXT: ## xmm0 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $16, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x38,0x10] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x3c]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0],mem[0],xmm0[2,3]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x2c]
; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero ; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $16, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x28,0x10] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x2c]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0],mem[0],xmm1[2,3]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x4c]
; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero ; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $16, {{[0-9]+}}(%esp), %xmm2, %xmm2 ## encoding: [0xc4,0xe3,0x69,0x21,0x54,0x24,0x48,0x10] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm3 ## encoding: [0xc5,0xfa,0x10,0x5c,0x24,0x4c]
; FMACALL32_BDVER2-NEXT: ## xmm2 = xmm2[0],mem[0],xmm2[2,3] ; FMACALL32_BDVER2-NEXT: ## xmm3 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $32, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x34,0x20] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm4 ## encoding: [0xc5,0xfa,0x10,0x64,0x24,0x44]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1],mem[0],xmm0[3] ; FMACALL32_BDVER2-NEXT: ## xmm4 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $32, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x24,0x20] ; FMACALL32_BDVER2-NEXT: vunpcklps %xmm0, %xmm1, %xmm0 ## encoding: [0xc5,0xf0,0x14,0xc0]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1],mem[0],xmm1[3] ; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; FMACALL32_BDVER2-NEXT: vinsertps $32, {{[0-9]+}}(%esp), %xmm2, %xmm2 ## encoding: [0xc4,0xe3,0x69,0x21,0x54,0x24,0x44,0x20] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x34]
; FMACALL32_BDVER2-NEXT: ## xmm2 = xmm2[0,1],mem[0],xmm2[3] ; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vmovlhps %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x16,0xc1]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0],xmm1[0]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x28]
; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x30,0x30] ; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0x44,0x24,0x30,0x30]
; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1,2],mem[0] ; FMACALL32_BDVER2-NEXT: ## xmm0 = xmm0[0,1,2],mem[0]
; FMACALL32_BDVER2-NEXT: vunpcklps %xmm1, %xmm2, %xmm1 ## encoding: [0xc5,0xe8,0x14,0xc9]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x24]
; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vmovlhps %xmm2, %xmm1, %xmm1 ## encoding: [0xc5,0xf0,0x16,0xca]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0],xmm2[0]
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x20,0x30] ; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x20,0x30]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1,2],mem[0] ; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1,2],mem[0]
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm2, %xmm2 ## encoding: [0xc4,0xe3,0x69,0x21,0x54,0x24,0x40,0x30] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x5c]
; FMACALL32_BDVER2-NEXT: ## xmm2 = xmm2[0,1,2],mem[0] ; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x18,0xc1,0x01] ; FMACALL32_BDVER2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe3,0x7d,0x18,0xc1,0x01]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x5c] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 ## encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x58]
; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero ; FMACALL32_BDVER2-NEXT: ## xmm1 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $16, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x58,0x10] ; FMACALL32_BDVER2-NEXT: vunpcklps %xmm1, %xmm2, %xmm1 ## encoding: [0xc5,0xe8,0x14,0xc9]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0],mem[0],xmm1[2,3] ; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; FMACALL32_BDVER2-NEXT: vinsertps $32, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x54,0x20] ; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x54]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1],mem[0],xmm1[3] ; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vmovlhps %xmm2, %xmm1, %xmm1 ## encoding: [0xc5,0xf0,0x16,0xca]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0],xmm2[0]
; FMACALL32_BDVER2-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 ## encoding: [0xc5,0xfa,0x10,0x54,0x24,0x48]
; FMACALL32_BDVER2-NEXT: ## xmm2 = mem[0],zero,zero,zero
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x50,0x30] ; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm1, %xmm1 ## encoding: [0xc4,0xe3,0x71,0x21,0x4c,0x24,0x50,0x30]
; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1,2],mem[0] ; FMACALL32_BDVER2-NEXT: ## xmm1 = xmm1[0,1,2],mem[0]
; FMACALL32_BDVER2-NEXT: vunpcklps %xmm2, %xmm3, %xmm2 ## encoding: [0xc5,0xe0,0x14,0xd2]
; FMACALL32_BDVER2-NEXT: ## xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; FMACALL32_BDVER2-NEXT: vmovlhps %xmm4, %xmm2, %xmm2 ## encoding: [0xc5,0xe8,0x16,0xd4]
; FMACALL32_BDVER2-NEXT: ## xmm2 = xmm2[0],xmm4[0]
; FMACALL32_BDVER2-NEXT: vinsertps $48, {{[0-9]+}}(%esp), %xmm2, %xmm2 ## encoding: [0xc4,0xe3,0x69,0x21,0x54,0x24,0x40,0x30]
; FMACALL32_BDVER2-NEXT: ## xmm2 = xmm2[0,1,2],mem[0]
; FMACALL32_BDVER2-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ## encoding: [0xc4,0xe3,0x75,0x18,0xca,0x01] ; FMACALL32_BDVER2-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ## encoding: [0xc4,0xe3,0x75,0x18,0xca,0x01]
; FMACALL32_BDVER2-NEXT: movl %ebp, %esp ## encoding: [0x89,0xec] ; FMACALL32_BDVER2-NEXT: movl %ebp, %esp ## encoding: [0x89,0xec]
; FMACALL32_BDVER2-NEXT: popl %ebp ## encoding: [0x5d] ; FMACALL32_BDVER2-NEXT: popl %ebp ## encoding: [0x5d]
; FMACALL32_BDVER2-NEXT: retl ## encoding: [0xc3] ; FMACALL32_BDVER2-NEXT: retl ## encoding: [0xc3]
entry: entry:
%call = call <16 x float> @llvm.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c) %call = call <16 x float> @llvm.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c)
ret <16 x float> %call ret <16 x float> %call
} }
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llvm/test/CodeGen/X86/haddsub-2.ll

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; ;
; AVX-LABEL: not_a_hsub_2: ; AVX-LABEL: not_a_hsub_2:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3] ; AVX-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3]
; AVX-NEXT: vsubss %xmm3, %xmm2, %xmm2 ; AVX-NEXT: vsubss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm0[1,1,3,3]
; AVX-NEXT: vsubss %xmm3, %xmm0, %xmm0 ; AVX-NEXT: vsubss %xmm3, %xmm0, %xmm0
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[3,1,2,3] ; AVX-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[3,1,2,3]
; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm3 = xmm1[1,0]
; AVX-NEXT: vsubss %xmm3, %xmm2, %xmm2 ; AVX-NEXT: vsubss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm1[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
; AVX-NEXT: vsubss %xmm3, %xmm1, %xmm1 ; AVX-NEXT: vsubss %xmm3, %xmm1, %xmm1
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%vecext = extractelement <4 x float> %A, i32 2 %vecext = extractelement <4 x float> %A, i32 2
%vecext1 = extractelement <4 x float> %A, i32 3 %vecext1 = extractelement <4 x float> %A, i32 3
%sub = fsub float %vecext, %vecext1 %sub = fsub float %vecext, %vecext1
%vecinit = insertelement <4 x float> undef, float %sub, i32 1 %vecinit = insertelement <4 x float> undef, float %sub, i32 1
%vecext2 = extractelement <4 x float> %A, i32 0 %vecext2 = extractelement <4 x float> %A, i32 0
%vecext3 = extractelement <4 x float> %A, i32 1 %vecext3 = extractelement <4 x float> %A, i32 1
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llvm/test/CodeGen/X86/haddsub-undef.ll

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; ;
; AVX512-SLOW-LABEL: test13_v16f32_undef: ; AVX512-SLOW-LABEL: test13_v16f32_undef:
; AVX512-SLOW: # %bb.0: ; AVX512-SLOW: # %bb.0:
; AVX512-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; AVX512-SLOW-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX512-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm1 ; AVX512-SLOW-NEXT: vaddss %xmm1, %xmm0, %xmm1
; AVX512-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX512-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-SLOW-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3] ; AVX512-SLOW-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3]
; AVX512-SLOW-NEXT: vaddss %xmm3, %xmm2, %xmm2 ; AVX512-SLOW-NEXT: vaddss %xmm3, %xmm2, %xmm2
; AVX512-SLOW-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] ; AVX512-SLOW-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; AVX512-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512-SLOW-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-SLOW-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] ; AVX512-SLOW-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]
; AVX512-SLOW-NEXT: vaddss %xmm2, %xmm0, %xmm2 ; AVX512-SLOW-NEXT: vaddss %xmm2, %xmm0, %xmm2
; AVX512-SLOW-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512-SLOW-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] ; AVX512-SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX512-SLOW-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] ; AVX512-SLOW-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; AVX512-SLOW-NEXT: vaddss %xmm0, %xmm2, %xmm0 ; AVX512-SLOW-NEXT: vaddss %xmm0, %xmm2, %xmm0
; AVX512-SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512-SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512-SLOW-NEXT: retq ; AVX512-SLOW-NEXT: retq
%vecext = extractelement <16 x float> %a, i32 0 %vecext = extractelement <16 x float> %a, i32 0
%vecext1 = extractelement <16 x float> %a, i32 1 %vecext1 = extractelement <16 x float> %a, i32 1
%add1 = fadd float %vecext, %vecext1 %add1 = fadd float %vecext, %vecext1
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llvm/test/CodeGen/X86/half.ll

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; BWON-F16C-NEXT: vmovd %eax, %xmm1 ; BWON-F16C-NEXT: vmovd %eax, %xmm1
; BWON-F16C-NEXT: vcvtph2ps %xmm1, %xmm1 ; BWON-F16C-NEXT: vcvtph2ps %xmm1, %xmm1
; BWON-F16C-NEXT: movswl (%rdi), %eax ; BWON-F16C-NEXT: movswl (%rdi), %eax
; BWON-F16C-NEXT: vmovd %eax, %xmm2 ; BWON-F16C-NEXT: vmovd %eax, %xmm2
; BWON-F16C-NEXT: vcvtph2ps %xmm2, %xmm2 ; BWON-F16C-NEXT: vcvtph2ps %xmm2, %xmm2
; BWON-F16C-NEXT: movswl 2(%rdi), %eax ; BWON-F16C-NEXT: movswl 2(%rdi), %eax
; BWON-F16C-NEXT: vmovd %eax, %xmm3 ; BWON-F16C-NEXT: vmovd %eax, %xmm3
; BWON-F16C-NEXT: vcvtph2ps %xmm3, %xmm3 ; BWON-F16C-NEXT: vcvtph2ps %xmm3, %xmm3
; BWON-F16C-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; BWON-F16C-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; BWON-F16C-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; BWON-F16C-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; BWON-F16C-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; BWON-F16C-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; BWON-F16C-NEXT: retq ; BWON-F16C-NEXT: retq
; ;
; CHECK-I686-LABEL: test_extend32_vec4: ; CHECK-I686-LABEL: test_extend32_vec4:
; CHECK-I686: # %bb.0: ; CHECK-I686: # %bb.0:
; CHECK-I686-NEXT: pushl %esi ; CHECK-I686-NEXT: pushl %esi
; CHECK-I686-NEXT: subl $56, %esp ; CHECK-I686-NEXT: subl $56, %esp
; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %esi
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llvm/test/CodeGen/X86/insert-into-constant-vector.ll

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; X64AVX-NEXT: retq ; X64AVX-NEXT: retq
%ins = insertelement <8 x i16> <i16 42, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 %x, i32 5 %ins = insertelement <8 x i16> <i16 42, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 %x, i32 5
ret <8 x i16> %ins ret <8 x i16> %ins
} }
define <4 x i32> @elt3_v4i32(i32 %x) { define <4 x i32> @elt3_v4i32(i32 %x) {
; X32SSE2-LABEL: elt3_v4i32: ; X32SSE2-LABEL: elt3_v4i32:
; X32SSE2: # %bb.0: ; X32SSE2: # %bb.0:
; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = <42,1,2,u>
; X32SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = <42,1,2,u>
; X32SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; X32SSE2-NEXT: retl ; X32SSE2-NEXT: retl
; ;
; X64SSE2-LABEL: elt3_v4i32: ; X64SSE2-LABEL: elt3_v4i32:
; X64SSE2: # %bb.0: ; X64SSE2: # %bb.0:
; X64SSE2-NEXT: movd %edi, %xmm1 ; X64SSE2-NEXT: movd %edi, %xmm1
; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = <42,1,2,u> ; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = <42,1,2,u>
; X64SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; X64SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; X64SSE2-NEXT: retq ; X64SSE2-NEXT: retq
; ;
; X32SSE4-LABEL: elt3_v4i32: ; X32SSE4-LABEL: elt3_v4i32:
; X32SSE4: # %bb.0: ; X32SSE4: # %bb.0:
; X32SSE4-NEXT: movdqa {{.*#+}} xmm0 = <42,1,2,u> ; X32SSE4-NEXT: movdqa {{.*#+}} xmm0 = <42,1,2,u>
; X32SSE4-NEXT: pinsrd $3, {{[0-9]+}}(%esp), %xmm0 ; X32SSE4-NEXT: pinsrd $3, {{[0-9]+}}(%esp), %xmm0
; X32SSE4-NEXT: retl ; X32SSE4-NEXT: retl
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ret <2 x i64> %ins ret <2 x i64> %ins
} }
define <4 x float> @elt1_v4f32(float %x) { define <4 x float> @elt1_v4f32(float %x) {
; X32SSE2-LABEL: elt1_v4f32: ; X32SSE2-LABEL: elt1_v4f32:
; X32SSE2: # %bb.0: ; X32SSE2: # %bb.0:
; X32SSE2-NEXT: movaps {{.*#+}} xmm1 = <4.2E+1,u,2.0E+0,3.0E+0> ; X32SSE2-NEXT: movaps {{.*#+}} xmm1 = <4.2E+1,u,2.0E+0,3.0E+0>
; X32SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; X32SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; X32SSE2-NEXT: retl ; X32SSE2-NEXT: retl
; ;
; X64SSE2-LABEL: elt1_v4f32: ; X64SSE2-LABEL: elt1_v4f32:
; X64SSE2: # %bb.0: ; X64SSE2: # %bb.0:
; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = <4.2E+1,u,2.0E+0,3.0E+0> ; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = <4.2E+1,u,2.0E+0,3.0E+0>
; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; X64SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; X64SSE2-NEXT: retq ; X64SSE2-NEXT: retq
; ;
; X32SSE4-LABEL: elt1_v4f32: ; X32SSE4-LABEL: elt1_v4f32:
; X32SSE4: # %bb.0: ; X32SSE4: # %bb.0:
; X32SSE4-NEXT: movaps {{.*#+}} xmm0 = <4.2E+1,u,2.0E+0,3.0E+0> ; X32SSE4-NEXT: movaps {{.*#+}} xmm0 = <4.2E+1,u,2.0E+0,3.0E+0>
; X32SSE4-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; X32SSE4-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
; X32SSE4-NEXT: retl ; X32SSE4-NEXT: retl
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; X64AVX-NEXT: retq ; X64AVX-NEXT: retq
%ins = insertelement <2 x double> <double 42.0, double 1.0>, double %x, i32 1 %ins = insertelement <2 x double> <double 42.0, double 1.0>, double %x, i32 1
ret <2 x double> %ins ret <2 x double> %ins
} }
define <8 x i32> @elt7_v8i32(i32 %x) { define <8 x i32> @elt7_v8i32(i32 %x) {
; X32SSE2-LABEL: elt7_v8i32: ; X32SSE2-LABEL: elt7_v8i32:
; X32SSE2: # %bb.0: ; X32SSE2: # %bb.0:
; X32SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,6,u>
; X32SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] ; X32SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,6,u>
; X32SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; X32SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; X32SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3] ; X32SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3]
; X32SSE2-NEXT: retl ; X32SSE2-NEXT: retl
; ;
; X64SSE2-LABEL: elt7_v8i32: ; X64SSE2-LABEL: elt7_v8i32:
; X64SSE2: # %bb.0: ; X64SSE2: # %bb.0:
; X64SSE2-NEXT: movd %edi, %xmm0 ; X64SSE2-NEXT: movd %edi, %xmm0
; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,6,u> ; X64SSE2-NEXT: movaps {{.*#+}} xmm1 = <4,5,6,u>
; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] ; X64SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; X64SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; X64SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3] ; X64SSE2-NEXT: movaps {{.*#+}} xmm0 = [42,1,2,3]
; X64SSE2-NEXT: retq ; X64SSE2-NEXT: retq
; ;
; X32SSE4-LABEL: elt7_v8i32: ; X32SSE4-LABEL: elt7_v8i32:
; X32SSE4: # %bb.0: ; X32SSE4: # %bb.0:
; X32SSE4-NEXT: movdqa {{.*#+}} xmm1 = <4,5,6,u> ; X32SSE4-NEXT: movdqa {{.*#+}} xmm1 = <4,5,6,u>
; X32SSE4-NEXT: pinsrd $3, {{[0-9]+}}(%esp), %xmm1 ; X32SSE4-NEXT: pinsrd $3, {{[0-9]+}}(%esp), %xmm1
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llvm/test/CodeGen/X86/insertelement-shuffle.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X86,X86_AVX256 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X86,X86_AVX256
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64_AVX256 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64_AVX256
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86_AVX512 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86_AVX512
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64_AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64_AVX512
define <8 x float> @insert_subvector_256(i16 %x0, i16 %x1, <8 x float> %v) nounwind { define <8 x float> @insert_subvector_256(i16 %x0, i16 %x1, <8 x float> %v) nounwind {
; X86-LABEL: insert_subvector_256: ; X86-LABEL: insert_subvector_256:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1 ; X86-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; X86-NEXT: vpbroadcastd %xmm1, %xmm1
; X86-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7] ; X86-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: insert_subvector_256: ; X64-LABEL: insert_subvector_256:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovd %edi, %xmm1 ; X64-NEXT: vmovd %edi, %xmm1
; X64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1 ; X64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; X64-NEXT: vpbroadcastd %xmm1, %xmm1
; X64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7] ; X64-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
; X64-NEXT: retq ; X64-NEXT: retq
%ins1 = insertelement <2 x i16> undef, i16 %x0, i32 0 %ins1 = insertelement <2 x i16> undef, i16 %x0, i32 0
%ins2 = insertelement <2 x i16> %ins1, i16 %x1, i32 1 %ins2 = insertelement <2 x i16> %ins1, i16 %x1, i32 1
%bc = bitcast <2 x i16> %ins2 to float %bc = bitcast <2 x i16> %ins2 to float
%ins3 = insertelement <8 x float> %v, float %bc, i32 1 %ins3 = insertelement <8 x float> %v, float %bc, i32 1
ret <8 x float> %ins3 ret <8 x float> %ins3
} }
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llvm/test/CodeGen/X86/known-signbits-vector.ll

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; X64-AVX2-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X64-AVX2-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%1 = sext <2 x i16> %a0 to <2 x i64> %1 = sext <2 x i16> %a0 to <2 x i64>
%2 = shl <2 x i64> %1, <i64 11, i64 5> %2 = shl <2 x i64> %1, <i64 11, i64 5>
%3 = sitofp <2 x i64> %2 to <2 x double> %3 = sitofp <2 x i64> %2 to <2 x double>
ret <2 x double> %3 ret <2 x double> %3
} }
; TODO: Fix vpshufd+vpsrlq -> vpshufd/vpermilps
define <2 x double> @signbits_ashr_concat_ashr_extract_sitofp(<2 x i64> %a0, <4 x i64> %a1) nounwind { define <2 x double> @signbits_ashr_concat_ashr_extract_sitofp(<2 x i64> %a0, <4 x i64> %a1) nounwind {
; X86-LABEL: signbits_ashr_concat_ashr_extract_sitofp: ; X86-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3] ; X86-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3]
; X86-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X86-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: signbits_ashr_concat_ashr_extract_sitofp: ; X64-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpsrlq $32, %xmm0, %xmm0 ; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3]
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X64-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = ashr <2 x i64> %a0, <i64 16, i64 16> %1 = ashr <2 x i64> %a0, <i64 16, i64 16>
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%3 = shufflevector <4 x i64> %a1, <4 x i64> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %3 = shufflevector <4 x i64> %a1, <4 x i64> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%4 = ashr <4 x i64> %3, <i64 16, i64 16, i64 16, i64 16> %4 = ashr <4 x i64> %3, <i64 16, i64 16, i64 16, i64 16>
%5 = shufflevector <4 x i64> %4, <4 x i64> undef, <2 x i32> <i32 2, i32 3> %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
%6 = sitofp <2 x i64> %5 to <2 x double> %6 = sitofp <2 x i64> %5 to <2 x double>
▲ Show 20 Lines • Show All 468 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/load-partial.ll

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Lines
; SSSE3-LABEL: load_float4_float3_trunc_0123: ; SSSE3-LABEL: load_float4_float3_trunc_0123:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movaps (%rdi), %xmm0 ; SSSE3-NEXT: movaps (%rdi), %xmm0
; SSSE3-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSSE3-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: load_float4_float3_trunc_0123: ; SSE41-LABEL: load_float4_float3_trunc_0123:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: movaps (%rdi), %xmm0 ; SSE41-NEXT: movaps (%rdi), %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: load_float4_float3_trunc_0123: ; AVX-LABEL: load_float4_float3_trunc_0123:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm0 ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX-NEXT: vmovaps (%rdi), %xmm1
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%2 = bitcast <4 x float>* %0 to i64* %2 = bitcast <4 x float>* %0 to i64*
%3 = load i64, i64* %2, align 16 %3 = load i64, i64* %2, align 16
%4 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2 %4 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%5 = bitcast float* %4 to i64* %5 = bitcast float* %4 to i64*
%6 = load i64, i64* %5, align 8 %6 = load i64, i64* %5, align 8
%7 = trunc i64 %3 to i32 %7 = trunc i64 %3 to i32
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%1 = load <2 x i8>, <2 x i8>* bitcast (i8* @h to <2 x i8>*), align 1 %1 = load <2 x i8>, <2 x i8>* bitcast (i8* @h to <2 x i8>*), align 1
%2 = shufflevector <2 x i8> %1, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %2 = shufflevector <2 x i8> %1, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%3 = insertelement <4 x i8> %2, i8 2, i32 2 %3 = insertelement <4 x i8> %2, i8 2, i32 2
%4 = bitcast <4 x i8> %3 to i32 %4 = bitcast <4 x i8> %3 to i32
ret i32 %4 ret i32 %4
} }
define void @PR43227(i32* %explicit_0, <8 x i32>* %explicit_1) { define void @PR43227(i32* %explicit_0, <8 x i32>* %explicit_1) {
; SSE2-LABEL: PR43227: ; SSE-LABEL: PR43227:
; SSE2: # %bb.0: ; SSE: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] ; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE-NEXT: psrlq $32, %xmm0
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSE-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-NEXT: movdqa %xmm1, 672(%rsi)
; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; SSE-NEXT: movdqa %xmm0, 688(%rsi)
; SSE2-NEXT: movaps %xmm1, 672(%rsi) ; SSE-NEXT: retq
; SSE2-NEXT: movaps %xmm2, 688(%rsi)
; SSE2-NEXT: retq
;
; SSSE3-LABEL: PR43227:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSSE3-NEXT: xorps %xmm1, %xmm1
; SSSE3-NEXT: xorps %xmm2, %xmm2
; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSSE3-NEXT: movaps %xmm1, 672(%rsi)
; SSSE3-NEXT: movaps %xmm2, 688(%rsi)
; SSSE3-NEXT: retq
;
; SSE41-LABEL: PR43227:
; SSE41: # %bb.0:
; SSE41-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
; SSE41-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE41-NEXT: movdqa %xmm1, 672(%rsi)
; SSE41-NEXT: movdqa %xmm0, 688(%rsi)
; SSE41-NEXT: retq
; ;
; AVX-LABEL: PR43227: ; AVX1-LABEL: PR43227:
; AVX: # %bb.0: ; AVX1: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,2,3] ; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vmovaps %ymm0, 672(%rsi)
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vzeroupper
; AVX-NEXT: vmovaps %ymm0, 672(%rsi) ; AVX1-NEXT: retq
; AVX-NEXT: vzeroupper ;
; AVX-NEXT: retq ; AVX2-LABEL: PR43227:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX2-NEXT: vmovdqa %ymm0, 672(%rsi)
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
%1 = getelementptr i32, i32* %explicit_0, i64 63 %1 = getelementptr i32, i32* %explicit_0, i64 63
%2 = bitcast i32* %1 to <3 x i32>* %2 = bitcast i32* %1 to <3 x i32>*
%3 = load <3 x i32>, <3 x i32>* %2, align 1 %3 = load <3 x i32>, <3 x i32>* %2, align 1
%4 = shufflevector <3 x i32> %3, <3 x i32> undef, <2 x i32> <i32 1, i32 2> %4 = shufflevector <3 x i32> %3, <3 x i32> undef, <2 x i32> <i32 1, i32 2>
%5 = shufflevector <2 x i32> %4, <2 x i32> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %5 = shufflevector <2 x i32> %4, <2 x i32> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%6 = shufflevector <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 undef, i32 0>, <8 x i32> %5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 9, i32 7> %6 = shufflevector <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 undef, i32 0>, <8 x i32> %5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 9, i32 7>
%7 = getelementptr inbounds <8 x i32>, <8 x i32>* %explicit_1, i64 21 %7 = getelementptr inbounds <8 x i32>, <8 x i32>* %explicit_1, i64 21
store <8 x i32> %6, <8 x i32>* %7, align 32 store <8 x i32> %6, <8 x i32>* %7, align 32
ret void ret void
} }

llvm/test/CodeGen/X86/load-slice.ll

Show All 20 Lines
; STRESS: vmovss 64([[BASE:[^(]+]]), [[OUT_Real:%xmm[0-9]+]] ; STRESS: vmovss 64([[BASE:[^(]+]]), [[OUT_Real:%xmm[0-9]+]]
; Load out[out_start + 8].imm, this is base + 8 * 8 + 4. ; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
; STRESS-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]] ; STRESS-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
; Add low slice: out[out_start].real, this is base + 0. ; Add low slice: out[out_start].real, this is base + 0.
; STRESS-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]] ; STRESS-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
; Add high slice: out[out_start].imm, this is base + 4. ; Add high slice: out[out_start].imm, this is base + 4.
; STRESS-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]] ; STRESS-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
; Swap Imm and Real. ; Swap Imm and Real.
; STRESS-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]] ; STRESS-NEXT: vunpcklps [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
; Put the results back into out[out_start]. ; Put the results back into out[out_start].
; STRESS-NEXT: vmovlps [[RES_Vec]], ([[BASE]]) ; STRESS-NEXT: vmovlps [[RES_Vec]], ([[BASE]])
; ;
; Same for REGULAR, we eliminate register bank copy with each slices. ; Same for REGULAR, we eliminate register bank copy with each slices.
; REGULAR-LABEL: t1: ; REGULAR-LABEL: t1:
; Load out[out_start + 8].real, this is base + 8 * 8 + 0. ; Load out[out_start + 8].real, this is base + 8 * 8 + 0.
; REGULAR: vmovss 64([[BASE:[^)]+]]), [[OUT_Real:%xmm[0-9]+]] ; REGULAR: vmovss 64([[BASE:[^)]+]]), [[OUT_Real:%xmm[0-9]+]]
; Load out[out_start + 8].imm, this is base + 8 * 8 + 4. ; Load out[out_start + 8].imm, this is base + 8 * 8 + 4.
; REGULAR-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]] ; REGULAR-NEXT: vmovss 68([[BASE]]), [[OUT_Imm:%xmm[0-9]+]]
; Add low slice: out[out_start].real, this is base + 0. ; Add low slice: out[out_start].real, this is base + 0.
; REGULAR-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]] ; REGULAR-NEXT: vaddss ([[BASE]]), [[OUT_Real]], [[RES_Real:%xmm[0-9]+]]
; Add high slice: out[out_start].imm, this is base + 4. ; Add high slice: out[out_start].imm, this is base + 4.
; REGULAR-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]] ; REGULAR-NEXT: vaddss 4([[BASE]]), [[OUT_Imm]], [[RES_Imm:%xmm[0-9]+]]
; Swap Imm and Real. ; Swap Imm and Real.
; REGULAR-NEXT: vinsertps $16, [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]] ; REGULAR-NEXT: vunpcklps [[RES_Imm]], [[RES_Real]], [[RES_Vec:%xmm[0-9]+]]
; Put the results back into out[out_start]. ; Put the results back into out[out_start].
; REGULAR-NEXT: vmovlps [[RES_Vec]], ([[BASE]]) ; REGULAR-NEXT: vmovlps [[RES_Vec]], ([[BASE]])
define void @t1(%class.Complex* nocapture %out, i64 %out_start) { define void @t1(%class.Complex* nocapture %out, i64 %out_start) {
entry: entry:
%arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start %arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start
%tmp = bitcast %class.Complex* %arrayidx to i64* %tmp = bitcast %class.Complex* %arrayidx to i64*
%tmp1 = load i64, i64* %tmp, align 8 %tmp1 = load i64, i64* %tmp, align 8
%t0.sroa.0.0.extract.trunc = trunc i64 %tmp1 to i32 %t0.sroa.0.0.extract.trunc = trunc i64 %tmp1 to i32
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/masked_expandload.ll

Show First 20 Lines • Show All 1,130 Lines • ▼ Show 20 Lines
; SSE2-NEXT: LBB4_1: ## %cond.load ; SSE2-NEXT: LBB4_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB4_4 ; SSE2-NEXT: je LBB4_4
; SSE2-NEXT: LBB4_3: ## %cond.load1 ; SSE2-NEXT: LBB4_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: expandload_v2f32_v2i1: ; SSE42-LABEL: expandload_v2f32_v2i1:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pxor %xmm2, %xmm2 ; SSE42-NEXT: pxor %xmm2, %xmm2
; SSE42-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE42-NEXT: pcmpeqd %xmm1, %xmm2
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines; AVX512VLBW-NEXT: retq
ret <2 x float> %res ret <2 x float> %res
} }
define <4 x float> @expandload_v4f32_const(float* %base, <4 x float> %src0) { define <4 x float> @expandload_v4f32_const(float* %base, <4 x float> %src0) {
; SSE2-LABEL: expandload_v4f32_const: ; SSE2-LABEL: expandload_v4f32_const:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm2[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[0,2]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: expandload_v4f32_const: ; SSE42-LABEL: expandload_v4f32_const:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE42-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE42-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1OR2-LABEL: expandload_v4f32_const: ; AVX1OR2-LABEL: expandload_v4f32_const:
; AVX1OR2: ## %bb.0: ; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; AVX1OR2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; AVX1OR2-NEXT: retq ; AVX1OR2-NEXT: retq
; ;
; AVX512F-LABEL: expandload_v4f32_const: ; AVX512F-LABEL: expandload_v4f32_const:
; AVX512F: ## %bb.0: ; AVX512F: ## %bb.0:
; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-NEXT: ## kill: def $xmm0 killed $xmm0 def $zmm0
; AVX512F-NEXT: movw $7, %ax ; AVX512F-NEXT: movw $7, %ax
Show All 22 Lines
define <16 x float> @expandload_v16f32_const(float* %base, <16 x float> %src0) { define <16 x float> @expandload_v16f32_const(float* %base, <16 x float> %src0) {
; SSE2-LABEL: expandload_v16f32_const: ; SSE2-LABEL: expandload_v16f32_const:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: movups (%rdi), %xmm0 ; SSE2-NEXT: movups (%rdi), %xmm0
; SSE2-NEXT: movups 16(%rdi), %xmm1 ; SSE2-NEXT: movups 16(%rdi), %xmm1
; SSE2-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,0],xmm5[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm4 = xmm4[0],xmm5[0]
; SSE2-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm2[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm2[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0],xmm5[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0],xmm5[0,2]
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm2[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm3[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm3[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[2,0],xmm2[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[2,0],xmm2[0,2]
; SSE2-NEXT: movaps %xmm4, %xmm2 ; SSE2-NEXT: movaps %xmm4, %xmm2
; SSE2-NEXT: movaps %xmm5, %xmm3 ; SSE2-NEXT: movaps %xmm5, %xmm3
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: expandload_v16f32_const: ; SSE42-LABEL: expandload_v16f32_const:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: movups (%rdi), %xmm0 ; SSE42-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE42-NEXT: movups 16(%rdi), %xmm1 ; SSE42-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE42-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
xbolva00Unsubmitted
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Regression

xbolva00: Regression
RKSimonAuthorUnsubmitted
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We've managed to change the order of load combines and we prematurely end up with different element sizes which we then can't combine together later. This is an existing problem, we've just exposed it more.

RKSimon: We've managed to change the order of load combines and we prematurely end up with different…
; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE42-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; SSE42-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
; SSE42-NEXT: blendps {{.*#+}} xmm2 = xmm4[0],xmm2[1,2,3] ; SSE42-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm4[0]
; SSE42-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
; SSE42-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
; SSE42-NEXT: blendps {{.*#+}} xmm2 = xmm4[0,1],xmm2[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3] ; SSE42-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; SSE42-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
; SSE42-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
; SSE42-NEXT: blendps {{.*#+}} xmm3 = xmm4[0],xmm3[1,2,3] ; SSE42-NEXT: blendps {{.*#+}} xmm3 = xmm4[0,1],xmm3[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3] ; SSE42-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3] ; SSE42-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3]
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1OR2-LABEL: expandload_v16f32_const: ; AVX1OR2-LABEL: expandload_v16f32_const:
; AVX1OR2: ## %bb.0: ; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; AVX1OR2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; AVX1OR2-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; AVX1OR2-NEXT: vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
; AVX1OR2-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0],ymm0[1,2,3,4,5,6,7] ; AVX1OR2-NEXT: vblendps {{.*#+}} ymm0 = ymm2[0],ymm0[1,2,3,4,5,6,7]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX1OR2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX1OR2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm4[0]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX1OR2-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero ; AVX1OR2-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX1OR2-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; AVX1OR2-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
; AVX1OR2-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1OR2-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1OR2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; AVX1OR2-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; AVX1OR2-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0],ymm1[1,2,3,4,5,6,7] ; AVX1OR2-NEXT: vblendps {{.*#+}} ymm1 = ymm2[0],ymm1[1,2,3,4,5,6,7]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0],mem[0],xmm1[2,3] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0],mem[0],xmm1[2,3]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
; AVX1OR2-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1OR2-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1OR2-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; AVX1OR2-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; AVX1OR2-NEXT: vblendps {{.*#+}} xmm1 = xmm3[0],xmm1[1,2,3] ; AVX1OR2-NEXT: vblendps {{.*#+}} xmm1 = xmm3[0,1],xmm1[2,3]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; AVX1OR2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1OR2-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1OR2-NEXT: retq ; AVX1OR2-NEXT: retq
; ;
; AVX512F-LABEL: expandload_v16f32_const: ; AVX512F-LABEL: expandload_v16f32_const:
; AVX512F: ## %bb.0: ; AVX512F: ## %bb.0:
; AVX512F-NEXT: movw $30719, %ax ## imm = 0x77FF ; AVX512F-NEXT: movw $30719, %ax ## imm = 0x77FF
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; SSE2-NEXT: LBB8_60: ## %else114 ; SSE2-NEXT: LBB8_60: ## %else114
; SSE2-NEXT: testl $1073741824, %ecx ## imm = 0x40000000 ; SSE2-NEXT: testl $1073741824, %ecx ## imm = 0x40000000
; SSE2-NEXT: jne LBB8_61 ; SSE2-NEXT: jne LBB8_61
; SSE2-NEXT: LBB8_62: ## %else118 ; SSE2-NEXT: LBB8_62: ## %else118
; SSE2-NEXT: testl $-2147483648, %ecx ## imm = 0x80000000 ; SSE2-NEXT: testl $-2147483648, %ecx ## imm = 0x80000000
; SSE2-NEXT: je LBB8_64 ; SSE2-NEXT: je LBB8_64
; SSE2-NEXT: LBB8_63: ## %cond.load121 ; SSE2-NEXT: LBB8_63: ## %cond.load121
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm7[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm7[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,1],xmm8[2,0]
; SSE2-NEXT: LBB8_64: ## %else122 ; SSE2-NEXT: LBB8_64: ## %else122
; SSE2-NEXT: movaps %xmm0, (%rax) ; SSE2-NEXT: movaps %xmm0, (%rax)
; SSE2-NEXT: movaps %xmm1, 16(%rax) ; SSE2-NEXT: movaps %xmm1, 16(%rax)
; SSE2-NEXT: movaps %xmm2, 32(%rax) ; SSE2-NEXT: movaps %xmm2, 32(%rax)
; SSE2-NEXT: movaps %xmm3, 48(%rax) ; SSE2-NEXT: movaps %xmm3, 48(%rax)
; SSE2-NEXT: movaps %xmm4, 64(%rax) ; SSE2-NEXT: movaps %xmm4, 64(%rax)
; SSE2-NEXT: movaps %xmm5, 80(%rax) ; SSE2-NEXT: movaps %xmm5, 80(%rax)
; SSE2-NEXT: movaps %xmm6, 96(%rax) ; SSE2-NEXT: movaps %xmm6, 96(%rax)
; SSE2-NEXT: movaps %xmm7, 112(%rax) ; SSE2-NEXT: movaps %xmm7, 112(%rax)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB8_1: ## %cond.load ; SSE2-NEXT: LBB8_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm8[0],xmm0[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm8[0],xmm0[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testb $2, %cl ; SSE2-NEXT: testb $2, %cl
; SSE2-NEXT: je LBB8_4 ; SSE2-NEXT: je LBB8_4
; SSE2-NEXT: LBB8_3: ## %cond.load1 ; SSE2-NEXT: LBB8_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm0[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm0 ; SSE2-NEXT: movaps %xmm8, %xmm0
; SSE2-NEXT: testb $4, %cl ; SSE2-NEXT: testb $4, %cl
; SSE2-NEXT: je LBB8_6 ; SSE2-NEXT: je LBB8_6
; SSE2-NEXT: LBB8_5: ## %cond.load5 ; SSE2-NEXT: LBB8_5: ## %cond.load5
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm0[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm8[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm8[0,2]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testb $8, %cl ; SSE2-NEXT: testb $8, %cl
; SSE2-NEXT: je LBB8_8 ; SSE2-NEXT: je LBB8_8
; SSE2-NEXT: LBB8_7: ## %cond.load9 ; SSE2-NEXT: LBB8_7: ## %cond.load9
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm8[2,0]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testb $16, %cl ; SSE2-NEXT: testb $16, %cl
; SSE2-NEXT: je LBB8_10 ; SSE2-NEXT: je LBB8_10
; SSE2-NEXT: LBB8_9: ## %cond.load13 ; SSE2-NEXT: LBB8_9: ## %cond.load13
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm8[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm8[0],xmm1[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testb $32, %cl ; SSE2-NEXT: testb $32, %cl
; SSE2-NEXT: je LBB8_12 ; SSE2-NEXT: je LBB8_12
; SSE2-NEXT: LBB8_11: ## %cond.load17 ; SSE2-NEXT: LBB8_11: ## %cond.load17
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm1[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm1 ; SSE2-NEXT: movaps %xmm8, %xmm1
; SSE2-NEXT: testb $64, %cl ; SSE2-NEXT: testb $64, %cl
; SSE2-NEXT: je LBB8_14 ; SSE2-NEXT: je LBB8_14
; SSE2-NEXT: LBB8_13: ## %cond.load21 ; SSE2-NEXT: LBB8_13: ## %cond.load21
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm1[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm8[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm8[0,2]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testb $-128, %cl ; SSE2-NEXT: testb $-128, %cl
; SSE2-NEXT: je LBB8_16 ; SSE2-NEXT: je LBB8_16
; SSE2-NEXT: LBB8_15: ## %cond.load25 ; SSE2-NEXT: LBB8_15: ## %cond.load25
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm8[2,0]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $256, %ecx ## imm = 0x100 ; SSE2-NEXT: testl $256, %ecx ## imm = 0x100
; SSE2-NEXT: je LBB8_18 ; SSE2-NEXT: je LBB8_18
; SSE2-NEXT: LBB8_17: ## %cond.load29 ; SSE2-NEXT: LBB8_17: ## %cond.load29
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm8[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm8[0],xmm2[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $512, %ecx ## imm = 0x200 ; SSE2-NEXT: testl $512, %ecx ## imm = 0x200
; SSE2-NEXT: je LBB8_20 ; SSE2-NEXT: je LBB8_20
; SSE2-NEXT: LBB8_19: ## %cond.load33 ; SSE2-NEXT: LBB8_19: ## %cond.load33
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm2[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm2[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm2[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm2 ; SSE2-NEXT: movaps %xmm8, %xmm2
; SSE2-NEXT: testl $1024, %ecx ## imm = 0x400 ; SSE2-NEXT: testl $1024, %ecx ## imm = 0x400
; SSE2-NEXT: je LBB8_22 ; SSE2-NEXT: je LBB8_22
; SSE2-NEXT: LBB8_21: ## %cond.load37 ; SSE2-NEXT: LBB8_21: ## %cond.load37
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm2[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm2[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm8[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm8[0,2]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $2048, %ecx ## imm = 0x800 ; SSE2-NEXT: testl $2048, %ecx ## imm = 0x800
; SSE2-NEXT: je LBB8_24 ; SSE2-NEXT: je LBB8_24
; SSE2-NEXT: LBB8_23: ## %cond.load41 ; SSE2-NEXT: LBB8_23: ## %cond.load41
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm2[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm2[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm8[2,0]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $4096, %ecx ## imm = 0x1000 ; SSE2-NEXT: testl $4096, %ecx ## imm = 0x1000
; SSE2-NEXT: je LBB8_26 ; SSE2-NEXT: je LBB8_26
; SSE2-NEXT: LBB8_25: ## %cond.load45 ; SSE2-NEXT: LBB8_25: ## %cond.load45
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm8[0],xmm3[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm8[0],xmm3[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $8192, %ecx ## imm = 0x2000 ; SSE2-NEXT: testl $8192, %ecx ## imm = 0x2000
; SSE2-NEXT: je LBB8_28 ; SSE2-NEXT: je LBB8_28
; SSE2-NEXT: LBB8_27: ## %cond.load49 ; SSE2-NEXT: LBB8_27: ## %cond.load49
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm3[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm3[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm3[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm3[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm3 ; SSE2-NEXT: movaps %xmm8, %xmm3
; SSE2-NEXT: testl $16384, %ecx ## imm = 0x4000 ; SSE2-NEXT: testl $16384, %ecx ## imm = 0x4000
; SSE2-NEXT: je LBB8_30 ; SSE2-NEXT: je LBB8_30
; SSE2-NEXT: LBB8_29: ## %cond.load53 ; SSE2-NEXT: LBB8_29: ## %cond.load53
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm3[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm3[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm8[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm8[0,2]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $32768, %ecx ## imm = 0x8000 ; SSE2-NEXT: testl $32768, %ecx ## imm = 0x8000
; SSE2-NEXT: je LBB8_32 ; SSE2-NEXT: je LBB8_32
; SSE2-NEXT: LBB8_31: ## %cond.load57 ; SSE2-NEXT: LBB8_31: ## %cond.load57
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm3[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm3[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm8[2,0]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $65536, %ecx ## imm = 0x10000 ; SSE2-NEXT: testl $65536, %ecx ## imm = 0x10000
; SSE2-NEXT: je LBB8_34 ; SSE2-NEXT: je LBB8_34
; SSE2-NEXT: LBB8_33: ## %cond.load61 ; SSE2-NEXT: LBB8_33: ## %cond.load61
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm4 = xmm8[0],xmm4[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm4 = xmm8[0],xmm4[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $131072, %ecx ## imm = 0x20000 ; SSE2-NEXT: testl $131072, %ecx ## imm = 0x20000
; SSE2-NEXT: je LBB8_36 ; SSE2-NEXT: je LBB8_36
; SSE2-NEXT: LBB8_35: ## %cond.load65 ; SSE2-NEXT: LBB8_35: ## %cond.load65
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm4[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm4[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm4[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm4[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm4 ; SSE2-NEXT: movaps %xmm8, %xmm4
; SSE2-NEXT: testl $262144, %ecx ## imm = 0x40000 ; SSE2-NEXT: testl $262144, %ecx ## imm = 0x40000
; SSE2-NEXT: je LBB8_38 ; SSE2-NEXT: je LBB8_38
; SSE2-NEXT: LBB8_37: ## %cond.load69 ; SSE2-NEXT: LBB8_37: ## %cond.load69
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm4[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm4[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm8[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm8[0,2]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $524288, %ecx ## imm = 0x80000 ; SSE2-NEXT: testl $524288, %ecx ## imm = 0x80000
; SSE2-NEXT: je LBB8_40 ; SSE2-NEXT: je LBB8_40
; SSE2-NEXT: LBB8_39: ## %cond.load73 ; SSE2-NEXT: LBB8_39: ## %cond.load73
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm4[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm4[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm8[2,0]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $1048576, %ecx ## imm = 0x100000 ; SSE2-NEXT: testl $1048576, %ecx ## imm = 0x100000
; SSE2-NEXT: je LBB8_42 ; SSE2-NEXT: je LBB8_42
; SSE2-NEXT: LBB8_41: ## %cond.load77 ; SSE2-NEXT: LBB8_41: ## %cond.load77
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm5 = xmm8[0],xmm5[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm5 = xmm8[0],xmm5[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $2097152, %ecx ## imm = 0x200000 ; SSE2-NEXT: testl $2097152, %ecx ## imm = 0x200000
; SSE2-NEXT: je LBB8_44 ; SSE2-NEXT: je LBB8_44
; SSE2-NEXT: LBB8_43: ## %cond.load81 ; SSE2-NEXT: LBB8_43: ## %cond.load81
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm5[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm5[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm5[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm5[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm5 ; SSE2-NEXT: movaps %xmm8, %xmm5
; SSE2-NEXT: testl $4194304, %ecx ## imm = 0x400000 ; SSE2-NEXT: testl $4194304, %ecx ## imm = 0x400000
; SSE2-NEXT: je LBB8_46 ; SSE2-NEXT: je LBB8_46
; SSE2-NEXT: LBB8_45: ## %cond.load85 ; SSE2-NEXT: LBB8_45: ## %cond.load85
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm5[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm5[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm8[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm8[0,2]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $8388608, %ecx ## imm = 0x800000 ; SSE2-NEXT: testl $8388608, %ecx ## imm = 0x800000
; SSE2-NEXT: je LBB8_48 ; SSE2-NEXT: je LBB8_48
; SSE2-NEXT: LBB8_47: ## %cond.load89 ; SSE2-NEXT: LBB8_47: ## %cond.load89
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm5[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm5[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm8[2,0]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $16777216, %ecx ## imm = 0x1000000 ; SSE2-NEXT: testl $16777216, %ecx ## imm = 0x1000000
; SSE2-NEXT: je LBB8_50 ; SSE2-NEXT: je LBB8_50
; SSE2-NEXT: LBB8_49: ## %cond.load93 ; SSE2-NEXT: LBB8_49: ## %cond.load93
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm6 = xmm8[0],xmm6[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm6 = xmm8[0],xmm6[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $33554432, %ecx ## imm = 0x2000000 ; SSE2-NEXT: testl $33554432, %ecx ## imm = 0x2000000
; SSE2-NEXT: je LBB8_52 ; SSE2-NEXT: je LBB8_52
; SSE2-NEXT: LBB8_51: ## %cond.load97 ; SSE2-NEXT: LBB8_51: ## %cond.load97
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm6[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm6[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm6[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm6[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm6 ; SSE2-NEXT: movaps %xmm8, %xmm6
; SSE2-NEXT: testl $67108864, %ecx ## imm = 0x4000000 ; SSE2-NEXT: testl $67108864, %ecx ## imm = 0x4000000
; SSE2-NEXT: je LBB8_54 ; SSE2-NEXT: je LBB8_54
; SSE2-NEXT: LBB8_53: ## %cond.load101 ; SSE2-NEXT: LBB8_53: ## %cond.load101
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm6[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm6[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm8[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm8[0,2]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $134217728, %ecx ## imm = 0x8000000 ; SSE2-NEXT: testl $134217728, %ecx ## imm = 0x8000000
; SSE2-NEXT: je LBB8_56 ; SSE2-NEXT: je LBB8_56
; SSE2-NEXT: LBB8_55: ## %cond.load105 ; SSE2-NEXT: LBB8_55: ## %cond.load105
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm6[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,1],xmm6[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm8[2,0]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $268435456, %ecx ## imm = 0x10000000 ; SSE2-NEXT: testl $268435456, %ecx ## imm = 0x10000000
; SSE2-NEXT: je LBB8_58 ; SSE2-NEXT: je LBB8_58
; SSE2-NEXT: LBB8_57: ## %cond.load109 ; SSE2-NEXT: LBB8_57: ## %cond.load109
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm7 = xmm8[0],xmm7[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm7 = xmm8[0],xmm7[1,2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: testl $536870912, %ecx ## imm = 0x20000000 ; SSE2-NEXT: testl $536870912, %ecx ## imm = 0x20000000
; SSE2-NEXT: je LBB8_60 ; SSE2-NEXT: je LBB8_60
; SSE2-NEXT: LBB8_59: ## %cond.load113 ; SSE2-NEXT: LBB8_59: ## %cond.load113
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm7[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm8 = xmm8[0],xmm7[0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm7[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm7[2,3]
; SSE2-NEXT: addq $4, %rsi ; SSE2-NEXT: addq $4, %rsi
; SSE2-NEXT: movaps %xmm8, %xmm7 ; SSE2-NEXT: movaps %xmm8, %xmm7
; SSE2-NEXT: testl $1073741824, %ecx ## imm = 0x40000000 ; SSE2-NEXT: testl $1073741824, %ecx ## imm = 0x40000000
; SSE2-NEXT: je LBB8_62 ; SSE2-NEXT: je LBB8_62
; SSE2-NEXT: LBB8_61: ## %cond.load117 ; SSE2-NEXT: LBB8_61: ## %cond.load117
; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm8 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm7[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[0,0],xmm7[3,0]
▲ Show 20 Lines • Show All 1,061 Lines • ▼ Show 20 Lines
; SSE2-NEXT: LBB10_1: ## %cond.load ; SSE2-NEXT: LBB10_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB10_4 ; SSE2-NEXT: je LBB10_4
; SSE2-NEXT: LBB10_3: ## %cond.load1 ; SSE2-NEXT: LBB10_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB10_6 ; SSE2-NEXT: je LBB10_6
; SSE2-NEXT: LBB10_5: ## %cond.load5 ; SSE2-NEXT: LBB10_5: ## %cond.load5
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSE2-NEXT: addq $4, %rdi ; SSE2-NEXT: addq $4, %rdi
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB10_8 ; SSE2-NEXT: je LBB10_8
; SSE2-NEXT: LBB10_7: ## %cond.load9 ; SSE2-NEXT: LBB10_7: ## %cond.load9
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: expandload_v4i32_v4i32: ; SSE42-LABEL: expandload_v4i32_v4i32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pxor %xmm2, %xmm2 ; SSE42-NEXT: pxor %xmm2, %xmm2
; SSE42-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE42-NEXT: pcmpeqd %xmm1, %xmm2
; SSE42-NEXT: movmskps %xmm2, %eax ; SSE42-NEXT: movmskps %xmm2, %eax
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llvm/test/CodeGen/X86/masked_load.ll

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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB7_1: ## %cond.load ; SSE2-NEXT: LBB7_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB7_4 ; SSE2-NEXT: je LBB7_4
; SSE2-NEXT: LBB7_3: ## %cond.load1 ; SSE2-NEXT: LBB7_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: load_v2f32_v2i32: ; SSE42-LABEL: load_v2f32_v2i32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pxor %xmm2, %xmm2 ; SSE42-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: LBB8_4: ## %else2 ; SSE2-NEXT: LBB8_4: ## %else2
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB8_1: ## %cond.load ; SSE2-NEXT: LBB8_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB8_4 ; SSE2-NEXT: je LBB8_4
; SSE2-NEXT: LBB8_3: ## %cond.load1 ; SSE2-NEXT: LBB8_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: load_v2f32_v2i32_undef: ; SSE42-LABEL: load_v2f32_v2i32_undef:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pxor %xmm1, %xmm1 ; SSE42-NEXT: pxor %xmm1, %xmm1
; SSE42-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE42-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB9_1: ## %cond.load ; SSE2-NEXT: LBB9_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB9_4 ; SSE2-NEXT: je LBB9_4
; SSE2-NEXT: LBB9_3: ## %cond.load1 ; SSE2-NEXT: LBB9_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB9_6 ; SSE2-NEXT: je LBB9_6
; SSE2-NEXT: LBB9_5: ## %cond.load4 ; SSE2-NEXT: LBB9_5: ## %cond.load4
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB9_8 ; SSE2-NEXT: je LBB9_8
; SSE2-NEXT: LBB9_7: ## %cond.load7 ; SSE2-NEXT: LBB9_7: ## %cond.load7
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: load_v4f32_v4i32: ; SSE42-LABEL: load_v4f32_v4i32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pxor %xmm2, %xmm2 ; SSE42-NEXT: pxor %xmm2, %xmm2
; SSE42-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE42-NEXT: pcmpeqd %xmm0, %xmm2
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; SSE2-NEXT: LBB10_16: ## %else20 ; SSE2-NEXT: LBB10_16: ## %else20
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB10_1: ## %cond.load ; SSE2-NEXT: LBB10_1: ## %cond.load
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB10_4 ; SSE2-NEXT: je LBB10_4
; SSE2-NEXT: LBB10_3: ## %cond.load1 ; SSE2-NEXT: LBB10_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB10_6 ; SSE2-NEXT: je LBB10_6
; SSE2-NEXT: LBB10_5: ## %cond.load4 ; SSE2-NEXT: LBB10_5: ## %cond.load4
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2]
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB10_8 ; SSE2-NEXT: je LBB10_8
; SSE2-NEXT: LBB10_7: ## %cond.load7 ; SSE2-NEXT: LBB10_7: ## %cond.load7
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB10_10 ; SSE2-NEXT: je LBB10_10
; SSE2-NEXT: LBB10_9: ## %cond.load10 ; SSE2-NEXT: LBB10_9: ## %cond.load10
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB10_12 ; SSE2-NEXT: je LBB10_12
; SSE2-NEXT: LBB10_11: ## %cond.load13 ; SSE2-NEXT: LBB10_11: ## %cond.load13
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB10_14 ; SSE2-NEXT: je LBB10_14
; SSE2-NEXT: LBB10_13: ## %cond.load16 ; SSE2-NEXT: LBB10_13: ## %cond.load16
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB10_16 ; SSE2-NEXT: je LBB10_16
; SSE2-NEXT: LBB10_15: ## %cond.load19 ; SSE2-NEXT: LBB10_15: ## %cond.load19
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: load_v8f32_v8i1_zero: ; SSE42-LABEL: load_v8f32_v8i1_zero:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: psllw $15, %xmm0 ; SSE42-NEXT: psllw $15, %xmm0
; SSE42-NEXT: packsswb %xmm0, %xmm0 ; SSE42-NEXT: packsswb %xmm0, %xmm0
; SSE42-NEXT: pmovmskb %xmm0, %eax ; SSE42-NEXT: pmovmskb %xmm0, %eax
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; SSE2-NEXT: LBB11_12: ## %else14 ; SSE2-NEXT: LBB11_12: ## %else14
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB11_13 ; SSE2-NEXT: jne LBB11_13
; SSE2-NEXT: LBB11_14: ## %else17 ; SSE2-NEXT: LBB11_14: ## %else17
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB11_16 ; SSE2-NEXT: je LBB11_16
; SSE2-NEXT: LBB11_15: ## %cond.load19 ; SSE2-NEXT: LBB11_15: ## %cond.load19
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm3[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,0]
; SSE2-NEXT: LBB11_16: ## %else20 ; SSE2-NEXT: LBB11_16: ## %else20
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: movaps %xmm3, %xmm1 ; SSE2-NEXT: movaps %xmm3, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB11_1: ## %cond.load ; SSE2-NEXT: LBB11_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB11_4 ; SSE2-NEXT: je LBB11_4
; SSE2-NEXT: LBB11_3: ## %cond.load1 ; SSE2-NEXT: LBB11_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB11_6 ; SSE2-NEXT: je LBB11_6
; SSE2-NEXT: LBB11_5: ## %cond.load4 ; SSE2-NEXT: LBB11_5: ## %cond.load4
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2]
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB11_8 ; SSE2-NEXT: je LBB11_8
; SSE2-NEXT: LBB11_7: ## %cond.load7 ; SSE2-NEXT: LBB11_7: ## %cond.load7
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB11_10 ; SSE2-NEXT: je LBB11_10
; SSE2-NEXT: LBB11_9: ## %cond.load10 ; SSE2-NEXT: LBB11_9: ## %cond.load10
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB11_12 ; SSE2-NEXT: je LBB11_12
; SSE2-NEXT: LBB11_11: ## %cond.load13 ; SSE2-NEXT: LBB11_11: ## %cond.load13
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm3[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm3[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm3[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB11_14 ; SSE2-NEXT: je LBB11_14
; SSE2-NEXT: LBB11_13: ## %cond.load16 ; SSE2-NEXT: LBB11_13: ## %cond.load16
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm3[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm3[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0,2]
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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB17_1: ## %cond.load ; SSE2-NEXT: LBB17_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB17_4 ; SSE2-NEXT: je LBB17_4
; SSE2-NEXT: LBB17_3: ## %cond.load1 ; SSE2-NEXT: LBB17_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: load_v2i32_v2i32: ; SSE42-LABEL: load_v2i32_v2i32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pxor %xmm2, %xmm2 ; SSE42-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB18_1: ## %cond.load ; SSE2-NEXT: LBB18_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB18_4 ; SSE2-NEXT: je LBB18_4
; SSE2-NEXT: LBB18_3: ## %cond.load1 ; SSE2-NEXT: LBB18_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB18_6 ; SSE2-NEXT: je LBB18_6
; SSE2-NEXT: LBB18_5: ## %cond.load4 ; SSE2-NEXT: LBB18_5: ## %cond.load4
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB18_8 ; SSE2-NEXT: je LBB18_8
; SSE2-NEXT: LBB18_7: ## %cond.load7 ; SSE2-NEXT: LBB18_7: ## %cond.load7
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: load_v4i32_v4i32: ; SSE42-LABEL: load_v4i32_v4i32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pxor %xmm2, %xmm2 ; SSE42-NEXT: pxor %xmm2, %xmm2
; SSE42-NEXT: pcmpeqd %xmm0, %xmm2 ; SSE42-NEXT: pcmpeqd %xmm0, %xmm2
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; SSE2-NEXT: LBB19_12: ## %else14 ; SSE2-NEXT: LBB19_12: ## %else14
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: jne LBB19_13 ; SSE2-NEXT: jne LBB19_13
; SSE2-NEXT: LBB19_14: ## %else17 ; SSE2-NEXT: LBB19_14: ## %else17
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB19_16 ; SSE2-NEXT: je LBB19_16
; SSE2-NEXT: LBB19_15: ## %cond.load19 ; SSE2-NEXT: LBB19_15: ## %cond.load19
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]
; SSE2-NEXT: LBB19_16: ## %else20 ; SSE2-NEXT: LBB19_16: ## %else20
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB19_1: ## %cond.load ; SSE2-NEXT: LBB19_1: ## %cond.load
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB19_4 ; SSE2-NEXT: je LBB19_4
; SSE2-NEXT: LBB19_3: ## %cond.load1 ; SSE2-NEXT: LBB19_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB19_6 ; SSE2-NEXT: je LBB19_6
; SSE2-NEXT: LBB19_5: ## %cond.load4 ; SSE2-NEXT: LBB19_5: ## %cond.load4
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB19_8 ; SSE2-NEXT: je LBB19_8
; SSE2-NEXT: LBB19_7: ## %cond.load7 ; SSE2-NEXT: LBB19_7: ## %cond.load7
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB19_10 ; SSE2-NEXT: je LBB19_10
; SSE2-NEXT: LBB19_9: ## %cond.load10 ; SSE2-NEXT: LBB19_9: ## %cond.load10
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB19_12 ; SSE2-NEXT: je LBB19_12
; SSE2-NEXT: LBB19_11: ## %cond.load13 ; SSE2-NEXT: LBB19_11: ## %cond.load13
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
; SSE2-NEXT: movaps %xmm0, %xmm2 ; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB19_14 ; SSE2-NEXT: je LBB19_14
; SSE2-NEXT: LBB19_13: ## %cond.load16 ; SSE2-NEXT: LBB19_13: ## %cond.load16
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2]
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; SSE2-NEXT: LBB20_16: ## %else20 ; SSE2-NEXT: LBB20_16: ## %else20
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; SSE2-NEXT: LBB20_1: ## %cond.load ; SSE2-NEXT: LBB20_1: ## %cond.load
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: testb $2, %al ; SSE2-NEXT: testb $2, %al
; SSE2-NEXT: je LBB20_4 ; SSE2-NEXT: je LBB20_4
; SSE2-NEXT: LBB20_3: ## %cond.load1 ; SSE2-NEXT: LBB20_3: ## %cond.load1
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: testb $4, %al ; SSE2-NEXT: testb $4, %al
; SSE2-NEXT: je LBB20_6 ; SSE2-NEXT: je LBB20_6
; SSE2-NEXT: LBB20_5: ## %cond.load4 ; SSE2-NEXT: LBB20_5: ## %cond.load4
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0,2]
; SSE2-NEXT: testb $8, %al ; SSE2-NEXT: testb $8, %al
; SSE2-NEXT: je LBB20_8 ; SSE2-NEXT: je LBB20_8
; SSE2-NEXT: LBB20_7: ## %cond.load7 ; SSE2-NEXT: LBB20_7: ## %cond.load7
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
; SSE2-NEXT: testb $16, %al ; SSE2-NEXT: testb $16, %al
; SSE2-NEXT: je LBB20_10 ; SSE2-NEXT: je LBB20_10
; SSE2-NEXT: LBB20_9: ## %cond.load10 ; SSE2-NEXT: LBB20_9: ## %cond.load10
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSE2-NEXT: testb $32, %al ; SSE2-NEXT: testb $32, %al
; SSE2-NEXT: je LBB20_12 ; SSE2-NEXT: je LBB20_12
; SSE2-NEXT: LBB20_11: ## %cond.load13 ; SSE2-NEXT: LBB20_11: ## %cond.load13
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,3]
; SSE2-NEXT: movaps %xmm2, %xmm1 ; SSE2-NEXT: movaps %xmm2, %xmm1
; SSE2-NEXT: testb $64, %al ; SSE2-NEXT: testb $64, %al
; SSE2-NEXT: je LBB20_14 ; SSE2-NEXT: je LBB20_14
; SSE2-NEXT: LBB20_13: ## %cond.load16 ; SSE2-NEXT: LBB20_13: ## %cond.load16
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
; SSE2-NEXT: testb $-128, %al ; SSE2-NEXT: testb $-128, %al
; SSE2-NEXT: je LBB20_16 ; SSE2-NEXT: je LBB20_16
; SSE2-NEXT: LBB20_15: ## %cond.load19 ; SSE2-NEXT: LBB20_15: ## %cond.load19
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: load_v8i32_v8i1_zero: ; SSE42-LABEL: load_v8i32_v8i1_zero:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: psllw $15, %xmm0 ; SSE42-NEXT: psllw $15, %xmm0
; SSE42-NEXT: packsswb %xmm0, %xmm0 ; SSE42-NEXT: packsswb %xmm0, %xmm0
; SSE42-NEXT: pmovmskb %xmm0, %eax ; SSE42-NEXT: pmovmskb %xmm0, %eax
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; 128-bit FP vectors are supported with AVX. ; 128-bit FP vectors are supported with AVX.
define <4 x float> @mload_constmask_v4f32(<4 x float>* %addr, <4 x float> %dst) { define <4 x float> @mload_constmask_v4f32(<4 x float>* %addr, <4 x float> %dst) {
; SSE2-LABEL: mload_constmask_v4f32: ; SSE2-LABEL: mload_constmask_v4f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE2-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm2[0]
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm1[2,0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: mload_constmask_v4f32: ; SSE42-LABEL: mload_constmask_v4f32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE42-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE42-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE42-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
; SSE42-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1OR2-LABEL: mload_constmask_v4f32: ; AVX1OR2-LABEL: mload_constmask_v4f32:
; AVX1OR2: ## %bb.0: ; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = mem[0],xmm0[1],mem[2,3] ; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = mem[0],xmm0[1],mem[2,3]
; AVX1OR2-NEXT: retq ; AVX1OR2-NEXT: retq
; ;
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} }
; 128-bit integer vectors are supported with AVX2. ; 128-bit integer vectors are supported with AVX2.
define <4 x i32> @mload_constmask_v4i32(<4 x i32>* %addr, <4 x i32> %dst) { define <4 x i32> @mload_constmask_v4i32(<4 x i32>* %addr, <4 x i32> %dst) {
; SSE2-LABEL: mload_constmask_v4i32: ; SSE2-LABEL: mload_constmask_v4i32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movaps %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[0,2]
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm2[2,0] ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: mload_constmask_v4i32: ; SSE42-LABEL: mload_constmask_v4i32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm0 ; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm0
; SSE42-NEXT: pinsrd $2, 8(%rdi), %xmm0 ; SSE42-NEXT: pinsrd $2, 8(%rdi), %xmm0
; SSE42-NEXT: pinsrd $3, 12(%rdi), %xmm0 ; SSE42-NEXT: pinsrd $3, 12(%rdi), %xmm0
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; 256-bit FP vectors are supported with AVX. ; 256-bit FP vectors are supported with AVX.
define <8 x float> @mload_constmask_v8f32(<8 x float>* %addr, <8 x float> %dst) { define <8 x float> @mload_constmask_v8f32(<8 x float>* %addr, <8 x float> %dst) {
; SSE2-LABEL: mload_constmask_v8f32: ; SSE2-LABEL: mload_constmask_v8f32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm3[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm0[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm3[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm3[0,2]
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: mload_constmask_v8f32: ; SSE42-LABEL: mload_constmask_v8f32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE42-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE42-NEXT: blendps {{.*#+}} xmm0 = xmm2[0],xmm0[1,2,3] ; SSE42-NEXT: blendps {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE42-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1OR2-LABEL: mload_constmask_v8f32: ; AVX1OR2-LABEL: mload_constmask_v8f32:
; AVX1OR2: ## %bb.0: ; AVX1OR2: ## %bb.0:
; AVX1OR2-NEXT: vmovaps {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,0,0,0,0,0] ; AVX1OR2-NEXT: vmovaps {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,0,0,0,0,0]
; AVX1OR2-NEXT: vmaskmovps (%rdi), %ymm1, %ymm1 ; AVX1OR2-NEXT: vmaskmovps (%rdi), %ymm1, %ymm1
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; 256-bit integer vectors are supported with AVX2. ; 256-bit integer vectors are supported with AVX2.
define <8 x i32> @mload_constmask_v8i32(<8 x i32>* %addr, <8 x i32> %dst) { define <8 x i32> @mload_constmask_v8i32(<8 x i32>* %addr, <8 x i32> %dst) {
; SSE2-LABEL: mload_constmask_v8i32: ; SSE2-LABEL: mload_constmask_v8i32:
; SSE2: ## %bb.0: ; SSE2: ## %bb.0:
; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm3[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm0[3,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm0[3,0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm3[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm3[0,2]
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: mload_constmask_v8i32: ; SSE42-LABEL: mload_constmask_v8i32:
; SSE42: ## %bb.0: ; SSE42: ## %bb.0:
; SSE42-NEXT: pinsrd $0, (%rdi), %xmm0 ; SSE42-NEXT: pinsrd $0, (%rdi), %xmm0
; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm0 ; SSE42-NEXT: pinsrd $1, 4(%rdi), %xmm0
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llvm/test/CodeGen/X86/masked_store_trunc.ll

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; SSE4-NEXT: je .LBB11_16 ; SSE4-NEXT: je .LBB11_16
; SSE4-NEXT: .LBB11_15: # %cond.store13 ; SSE4-NEXT: .LBB11_15: # %cond.store13
; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi) ; SSE4-NEXT: pextrw $7, %xmm0, 14(%rdi)
; SSE4-NEXT: retq ; SSE4-NEXT: retq
; ;
; AVX1-LABEL: truncstore_v8i32_v8i16: ; AVX1-LABEL: truncstore_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-NEXT: vmovmskps %ymm1, %eax ; AVX1-NEXT: vmovmskps %ymm1, %eax
; AVX1-NEXT: notl %eax ; AVX1-NEXT: notl %eax
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llvm/test/CodeGen/X86/merge-consecutive-loads-128.ll

Show First 20 Lines • Show All 1,173 Lines • ▼ Show 20 Lines
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSE2-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: merge_4f32_f32_2345_volatile: ; SSE41-LABEL: merge_4f32_f32_2345_volatile:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: merge_4f32_f32_2345_volatile: ; AVX-LABEL: merge_4f32_f32_2345_volatile:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X32-SSE1-LABEL: merge_4f32_f32_2345_volatile: ; X32-SSE1-LABEL: merge_4f32_f32_2345_volatile:
; X32-SSE1: # %bb.0: ; X32-SSE1: # %bb.0:
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; X32-SSE1-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; X32-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X32-SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X32-SSE1-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; X32-SSE1-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; X32-SSE1-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X32-SSE1-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32-SSE1-NEXT: retl ; X32-SSE1-NEXT: retl
; ;
; X32-SSE41-LABEL: merge_4f32_f32_2345_volatile: ; X32-SSE41-LABEL: merge_4f32_f32_2345_volatile:
; X32-SSE41: # %bb.0: ; X32-SSE41: # %bb.0:
; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; X32-SSE41-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X32-SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; X32-SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; X32-SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32-SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; X32-SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; X32-SSE41-NEXT: retl ; X32-SSE41-NEXT: retl
%ptr0 = getelementptr inbounds float, float* %ptr, i64 2 %ptr0 = getelementptr inbounds float, float* %ptr, i64 2
%ptr1 = getelementptr inbounds float, float* %ptr, i64 3 %ptr1 = getelementptr inbounds float, float* %ptr, i64 3
%ptr2 = getelementptr inbounds float, float* %ptr, i64 4 %ptr2 = getelementptr inbounds float, float* %ptr, i64 4
%ptr3 = getelementptr inbounds float, float* %ptr, i64 5 %ptr3 = getelementptr inbounds float, float* %ptr, i64 5
%val0 = load volatile float, float* %ptr0 %val0 = load volatile float, float* %ptr0
%val1 = load float, float* %ptr1 %val1 = load float, float* %ptr1
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llvm/test/CodeGen/X86/oddshuffles.ll

Show First 20 Lines • Show All 506 Lines • ▼ Show 20 Lines; XOP-NEXT: retq
store <12 x i16> %r, <12 x i16>* %p store <12 x i16> %r, <12 x i16>* %p
ret void ret void
} }
define void @v12i32(<8 x i32> %a, <8 x i32> %b, <12 x i32>* %p) nounwind { define void @v12i32(<8 x i32> %a, <8 x i32> %b, <12 x i32>* %p) nounwind {
; SSE2-LABEL: v12i32: ; SSE2-LABEL: v12i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm2, %xmm3 ; SSE2-NEXT: movaps %xmm2, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm0[1,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[1,3]
; SSE2-NEXT: movaps %xmm0, %xmm4 ; SSE2-NEXT: movaps %xmm0, %xmm4
; SSE2-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,1],xmm3[0,2]
; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: movaps %xmm0, %xmm3
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,0],xmm1[2,1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
; SSE2-NEXT: movaps %xmm2, %xmm5 ; SSE2-NEXT: movaps %xmm2, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,0],xmm1[1,0] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[1,0],xmm1[1,0]
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[2,0],xmm3[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[2,0],xmm3[0,2]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm2[3,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,1],xmm2[3,3]
; SSE2-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: unpckhps {{.*#+}} xmm2 = xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[0,2]
; SSE2-NEXT: movaps %xmm2, 32(%rdi) ; SSE2-NEXT: movaps %xmm2, 32(%rdi)
; SSE2-NEXT: movaps %xmm5, 16(%rdi) ; SSE2-NEXT: movaps %xmm5, 16(%rdi)
; SSE2-NEXT: movaps %xmm4, (%rdi) ; SSE2-NEXT: movaps %xmm4, (%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: v12i32: ; SSE42-LABEL: v12i32:
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; SSE2-NEXT: movdqa %xmm3, %xmm4 ; SSE2-NEXT: movdqa %xmm3, %xmm4
; SSE2-NEXT: pand %xmm1, %xmm4 ; SSE2-NEXT: pand %xmm1, %xmm4
; SSE2-NEXT: pandn %xmm2, %xmm1 ; SSE2-NEXT: pandn %xmm2, %xmm1
; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: por %xmm4, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,1,3]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,6,5,6,7] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,6,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,1,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,1,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,3,2,1,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,3,2,1,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm1[0,1,2,3,4,7,6,7] ; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm2[0,1,2,3,4,7,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm8[0,1,2,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm8[0,1,2,1]
; SSE2-NEXT: pshufhw {{.*#+}} xmm5 = xmm5[0,1,2,3,4,5,6,5] ; SSE2-NEXT: pshufhw {{.*#+}} xmm5 = xmm5[0,1,2,3,4,5,6,5]
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,0],xmm4[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,0],xmm4[2,0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm5[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm5[2,0]
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [65535,65535,0,65535,65535,0,65535,65535] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [65535,65535,0,65535,65535,0,65535,65535]
; SSE2-NEXT: movdqa %xmm4, %xmm5 ; SSE2-NEXT: movdqa %xmm4, %xmm5
; SSE2-NEXT: pandn %xmm2, %xmm5 ; SSE2-NEXT: pandn %xmm2, %xmm5
; SSE2-NEXT: movdqa %xmm3, %xmm6 ; SSE2-NEXT: movdqa %xmm3, %xmm6
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; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: movdqu (%rdi), %xmm0 ; SSE42-NEXT: movdqu (%rdi), %xmm0
; SSE42-NEXT: movdqu 16(%rdi), %xmm1 ; SSE42-NEXT: movdqu 16(%rdi), %xmm1
; SSE42-NEXT: movdqu 32(%rdi), %xmm2 ; SSE42-NEXT: movdqu 32(%rdi), %xmm2
; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,1,2,1] ; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,1,2,1]
; SSE42-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6,5] ; SSE42-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6,5]
; SSE42-NEXT: movdqa %xmm0, %xmm4 ; SSE42-NEXT: movdqa %xmm0, %xmm4
; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm1[1],xmm4[2,3],xmm1[4],xmm4[5,6],xmm1[7] ; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm1[1],xmm4[2,3],xmm1[4],xmm4[5,6],xmm1[7]
; SSE42-NEXT: pshufb {{.*#+}} xmm4 = xmm4[0,1,6,7,12,13,2,3,8,9,14,15,12,13,14,15] ; SSE42-NEXT: pshufb {{.*#+}} xmm4 = xmm4[0,1,6,7,12,13,2,3,8,9,14,15,u,u,u,u]
; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5],xmm3[6,7] ; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5],xmm3[6,7]
; SSE42-NEXT: movdqa %xmm2, %xmm3 ; SSE42-NEXT: movdqa %xmm2, %xmm3
; SSE42-NEXT: pshufb {{.*#+}} xmm3 = xmm3[0,1,6,7,4,5,6,7,0,1,0,1,6,7,12,13] ; SSE42-NEXT: pshufb {{.*#+}} xmm3 = xmm3[0,1,6,7,4,5,6,7,0,1,0,1,6,7,12,13]
; SSE42-NEXT: movdqa %xmm0, %xmm5 ; SSE42-NEXT: movdqa %xmm0, %xmm5
; SSE42-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1],xmm1[2],xmm5[3,4],xmm1[5],xmm5[6,7] ; SSE42-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1],xmm1[2],xmm5[3,4],xmm1[5],xmm5[6,7]
; SSE42-NEXT: pshufb {{.*#+}} xmm5 = xmm5[2,3,8,9,14,15,4,5,10,11,10,11,8,9,14,15] ; SSE42-NEXT: pshufb {{.*#+}} xmm5 = xmm5[2,3,8,9,14,15,4,5,10,11,10,11,8,9,14,15]
; SSE42-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1,2,3,4],xmm3[5,6,7] ; SSE42-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1,2,3,4],xmm3[5,6,7]
; SSE42-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6,7,8,9,2,3,8,9,14,15] ; SSE42-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6,7,8,9,2,3,8,9,14,15]
; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2],xmm1[3,4],xmm0[5],xmm1[6,7] ; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2],xmm1[3,4],xmm0[5],xmm1[6,7]
; SSE42-NEXT: pshufb {{.*#+}} xmm1 = xmm1[4,5,10,11,0,1,6,7,12,13,14,15,0,1,2,3] ; SSE42-NEXT: pshufb {{.*#+}} xmm1 = xmm1[4,5,10,11,0,1,6,7,12,13,14,15,0,1,2,3]
; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4],xmm2[5,6,7] ; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4],xmm2[5,6,7]
; SSE42-NEXT: movdqu %xmm4, (%rsi) ; SSE42-NEXT: movdqu %xmm4, (%rsi)
; SSE42-NEXT: movdqu %xmm5, (%rdx) ; SSE42-NEXT: movdqu %xmm5, (%rdx)
; SSE42-NEXT: movdqu %xmm1, (%rcx) ; SSE42-NEXT: movdqu %xmm1, (%rcx)
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: interleave_24i16_out: ; AVX1-LABEL: interleave_24i16_out:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovdqu (%rdi), %xmm0 ; AVX1-NEXT: vmovdqu (%rdi), %xmm0
; AVX1-NEXT: vmovdqu 16(%rdi), %xmm1 ; AVX1-NEXT: vmovdqu 16(%rdi), %xmm1
; AVX1-NEXT: vmovdqu 32(%rdi), %xmm2 ; AVX1-NEXT: vmovdqu 32(%rdi), %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,1,2,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,1,2,1]
; AVX1-NEXT: vpshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6,5] ; AVX1-NEXT: vpshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6,5]
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4],xmm0[5,6],xmm1[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm0[0],xmm1[1],xmm0[2,3],xmm1[4],xmm0[5,6],xmm1[7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[0,1,6,7,12,13,2,3,8,9,14,15,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm4[0,1,6,7,12,13,2,3,8,9,14,15,u,u,u,u]
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm4[0,1,2,3,4,5],xmm3[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm4[0,1,2,3,4,5],xmm3[6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm2[0,1,6,7,4,5,6,7,0,1,0,1,6,7,12,13] ; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm2[0,1,6,7,4,5,6,7,0,1,0,1,6,7,12,13]
; AVX1-NEXT: vpblendw {{.*#+}} xmm5 = xmm0[0,1],xmm1[2],xmm0[3,4],xmm1[5],xmm0[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm5 = xmm0[0,1],xmm1[2],xmm0[3,4],xmm1[5],xmm0[6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm5 = xmm5[2,3,8,9,14,15,4,5,10,11,u,u,u,u,u,u] ; AVX1-NEXT: vpshufb {{.*#+}} xmm5 = xmm5[2,3,8,9,14,15,4,5,10,11,u,u,u,u,u,u]
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1,2,3,4],xmm4[5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1,2,3,4],xmm4[5,6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6,7,8,9,2,3,8,9,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5,6,7,8,9,2,3,8,9,14,15]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3,4],xmm0[5],xmm1[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3,4],xmm0[5],xmm1[6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,10,11,0,1,6,7,12,13,u,u,u,u,u,u] ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,10,11,0,1,6,7,12,13,u,u,u,u,u,u]
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines; XOP-NEXT: retq
store <24 x i16> %interleaved, <24 x i16>* %p, align 4 store <24 x i16> %interleaved, <24 x i16>* %p, align 4
ret void ret void
} }
define void @interleave_24i32_out(<24 x i32>* %p, <8 x i32>* %q1, <8 x i32>* %q2, <8 x i32>* %q3) nounwind { define void @interleave_24i32_out(<24 x i32>* %p, <8 x i32>* %q1, <8 x i32>* %q2, <8 x i32>* %q3) nounwind {
; SSE2-LABEL: interleave_24i32_out: ; SSE2-LABEL: interleave_24i32_out:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movups 80(%rdi), %xmm8 ; SSE2-NEXT: movups 80(%rdi), %xmm8
; SSE2-NEXT: movups 64(%rdi), %xmm4 ; SSE2-NEXT: movups 64(%rdi), %xmm3
; SSE2-NEXT: movdqu (%rdi), %xmm0 ; SSE2-NEXT: movdqu (%rdi), %xmm1
; SSE2-NEXT: movups 16(%rdi), %xmm6 ; SSE2-NEXT: movups 16(%rdi), %xmm5
; SSE2-NEXT: movups 32(%rdi), %xmm10 ; SSE2-NEXT: movups 32(%rdi), %xmm10
; SSE2-NEXT: movups 48(%rdi), %xmm12 ; SSE2-NEXT: movdqu 48(%rdi), %xmm2
; SSE2-NEXT: movdqa %xmm0, %xmm11 ; SSE2-NEXT: movdqa %xmm1, %xmm11
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm0[2,3,0,1] ; SSE2-NEXT: movaps %xmm10, %xmm7
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm6[0,0] ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[2,1],xmm5[3,3]
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,0,1]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm6[3,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm5[0,0]
; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm6[1,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm5[1,1,2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[2,0],xmm10[1,0] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[2,3],xmm10[1,1]
; SSE2-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,3],xmm6[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm11 = xmm11[0,3],xmm5[0,2]
; SSE2-NEXT: movaps %xmm12, %xmm6 ; SSE2-NEXT: movdqa %xmm2, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,0],xmm4[0,0] ; SSE2-NEXT: movaps %xmm8, %xmm4
; SSE2-NEXT: movaps %xmm6, %xmm2 ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,1],xmm3[3,3]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm4[3,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm2[2,3,0,1]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm3[0,0]
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0],xmm8[1,0] ; SSE2-NEXT: pshufd {{.*#+}} xmm12 = xmm3[1,1,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm12[2,3,0,1] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,3],xmm8[1,1]
; SSE2-NEXT: shufps {{.*#+}} xmm12 = xmm12[0,3],xmm4[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm3[0,2]
; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[1] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm4[2,0]
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,1],xmm8[0,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm7[2,0]
; SSE2-NEXT: shufps {{.*#+}} xmm8 = xmm8[2,0],xmm2[2,0] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm9[0],xmm0[1],xmm9[1]
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm8[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm10[0,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm9[0],xmm7[1],xmm9[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm12[0],xmm6[1],xmm12[1]
; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,1],xmm10[0,3] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm8[0,3]
; SSE2-NEXT: shufps {{.*#+}} xmm10 = xmm10[2,0],xmm1[2,0] ; SSE2-NEXT: movups %xmm5, 16(%rsi)
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm10[2,0]
; SSE2-NEXT: movups %xmm12, 16(%rsi)
; SSE2-NEXT: movups %xmm11, (%rsi) ; SSE2-NEXT: movups %xmm11, (%rsi)
; SSE2-NEXT: movups %xmm6, 16(%rdx) ; SSE2-NEXT: movups %xmm2, 16(%rdx)
; SSE2-NEXT: movups %xmm0, (%rdx) ; SSE2-NEXT: movups %xmm1, (%rdx)
; SSE2-NEXT: movups %xmm5, 16(%rcx) ; SSE2-NEXT: movups %xmm6, 16(%rcx)
; SSE2-NEXT: movups %xmm7, (%rcx) ; SSE2-NEXT: movups %xmm0, (%rcx)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: interleave_24i32_out: ; SSE42-LABEL: interleave_24i32_out:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: movups 80(%rdi), %xmm8 ; SSE42-NEXT: movups 80(%rdi), %xmm8
; SSE42-NEXT: movdqu 64(%rdi), %xmm9 ; SSE42-NEXT: movdqu 64(%rdi), %xmm9
; SSE42-NEXT: movdqu (%rdi), %xmm4 ; SSE42-NEXT: movdqu (%rdi), %xmm4
; SSE42-NEXT: movdqu 16(%rdi), %xmm2 ; SSE42-NEXT: movdqu 16(%rdi), %xmm2
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; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movups (%rsi), %xmm1 ; SSE2-NEXT: movups (%rsi), %xmm1
; SSE2-NEXT: movups 16(%rsi), %xmm0 ; SSE2-NEXT: movups 16(%rsi), %xmm0
; SSE2-NEXT: movups (%rdx), %xmm8 ; SSE2-NEXT: movups (%rdx), %xmm8
; SSE2-NEXT: movups 16(%rdx), %xmm5 ; SSE2-NEXT: movups 16(%rdx), %xmm5
; SSE2-NEXT: movups (%rcx), %xmm3 ; SSE2-NEXT: movups (%rcx), %xmm3
; SSE2-NEXT: movups 16(%rcx), %xmm6 ; SSE2-NEXT: movups 16(%rcx), %xmm6
; SSE2-NEXT: movaps %xmm3, %xmm7 ; SSE2-NEXT: movaps %xmm3, %xmm7
; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,0],xmm1[1,0] ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,1],xmm1[1,3]
; SSE2-NEXT: movaps %xmm1, %xmm9 ; SSE2-NEXT: movaps %xmm1, %xmm9
; SSE2-NEXT: unpcklps {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
; SSE2-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,1],xmm7[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,1],xmm7[0,2]
; SSE2-NEXT: movaps %xmm5, %xmm7 ; SSE2-NEXT: movaps %xmm5, %xmm7
; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[3,2],xmm6[3,2] ; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[3,1],xmm6[3,3]
; SSE2-NEXT: movaps %xmm6, %xmm4 ; SSE2-NEXT: movaps %xmm6, %xmm4
; SSE2-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm0[2],xmm4[3],xmm0[3] ; SSE2-NEXT: unpckhps {{.*#+}} xmm4 = xmm4[2],xmm0[2],xmm4[3],xmm0[3]
; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,3],xmm7[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,3],xmm7[0,2]
; SSE2-NEXT: movaps %xmm0, %xmm7 ; SSE2-NEXT: movaps %xmm0, %xmm7
; SSE2-NEXT: shufps {{.*#+}} xmm7 = xmm7[2,0],xmm5[2,1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm7 = xmm7[1],xmm5[1]
; SSE2-NEXT: movaps %xmm6, %xmm2 ; SSE2-NEXT: movaps %xmm6, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm5[1,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm5[1,0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm7[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm7[0,2]
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,0],xmm0[1,0] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,1],xmm0[1,3]
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm6[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm6[0,2]
; SSE2-NEXT: movaps %xmm8, %xmm5 ; SSE2-NEXT: movaps %xmm8, %xmm5
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,2],xmm3[3,2] ; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[3,1],xmm3[3,3]
; SSE2-NEXT: movaps %xmm3, %xmm6 ; SSE2-NEXT: movaps %xmm3, %xmm6
; SSE2-NEXT: unpckhps {{.*#+}} xmm6 = xmm6[2],xmm1[2],xmm6[3],xmm1[3] ; SSE2-NEXT: unpckhps {{.*#+}} xmm6 = xmm6[2],xmm1[2],xmm6[3],xmm1[3]
; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,3],xmm5[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,3],xmm5[0,2]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm8[2,1] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm8[1]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm8[1,0] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,0],xmm8[1,0]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,0],xmm1[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,0],xmm1[0,2]
; SSE2-NEXT: movups %xmm3, 16(%rdi) ; SSE2-NEXT: movups %xmm3, 16(%rdi)
; SSE2-NEXT: movups %xmm6, 32(%rdi) ; SSE2-NEXT: movups %xmm6, 32(%rdi)
; SSE2-NEXT: movups %xmm0, 48(%rdi) ; SSE2-NEXT: movups %xmm0, 48(%rdi)
; SSE2-NEXT: movups %xmm2, 64(%rdi) ; SSE2-NEXT: movups %xmm2, 64(%rdi)
; SSE2-NEXT: movups %xmm4, 80(%rdi) ; SSE2-NEXT: movups %xmm4, 80(%rdi)
; SSE2-NEXT: movups %xmm9, (%rdi) ; SSE2-NEXT: movups %xmm9, (%rdi)
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; SSE42-NEXT: movdqu %xmm7, 80(%rdi) ; SSE42-NEXT: movdqu %xmm7, 80(%rdi)
; SSE42-NEXT: movdqu %xmm1, (%rdi) ; SSE42-NEXT: movdqu %xmm1, (%rdi)
; SSE42-NEXT: retq ; SSE42-NEXT: retq
; ;
; AVX1-LABEL: interleave_24i32_in: ; AVX1-LABEL: interleave_24i32_in:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovupd (%rsi), %ymm0 ; AVX1-NEXT: vmovupd (%rsi), %ymm0
; AVX1-NEXT: vmovups (%rdx), %xmm1 ; AVX1-NEXT: vmovups (%rdx), %xmm1
; AVX1-NEXT: vmovups 16(%rdx), %xmm2 ; AVX1-NEXT: vmovups (%rsi), %xmm2
; AVX1-NEXT: vmovups (%rsi), %xmm3 ; AVX1-NEXT: vunpckhpd {{.*#+}} xmm3 = xmm2[1],xmm1[1]
; AVX1-NEXT: vshufps {{.*#+}} xmm4 = xmm3[2,0],xmm1[2,0] ; AVX1-NEXT: vshufps {{.*#+}} xmm3 = xmm1[1,1],xmm3[0,2]
; AVX1-NEXT: vshufps {{.*#+}} xmm4 = xmm1[1,1],xmm4[0,2] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,0],xmm3[0,0] ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,1]
; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[2,1] ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1 ; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = mem[0,1,0,1]
; AVX1-NEXT: vpermilps {{.*#+}} xmm3 = mem[0,1,0,1] ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm3, %ymm3 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1],ymm2[2],ymm1[3,4],ymm2[5],ymm1[6,7]
; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1],ymm3[2],ymm1[3,4],ymm3[5],ymm1[6,7] ; AVX1-NEXT: vmovups 16(%rcx), %xmm2
; AVX1-NEXT: vmovups 16(%rcx), %xmm3 ; AVX1-NEXT: vmovups 16(%rdx), %xmm3
; AVX1-NEXT: vshufps {{.*#+}} xmm4 = xmm2[3,0],xmm3[3,0] ; AVX1-NEXT: vshufps {{.*#+}} xmm4 = xmm3[3,0],xmm2[3,0]
; AVX1-NEXT: vshufps {{.*#+}} xmm4 = xmm3[2,1],xmm4[0,2] ; AVX1-NEXT: vshufps {{.*#+}} xmm4 = xmm2[2,1],xmm4[0,2]
; AVX1-NEXT: vshufps {{.*#+}} xmm3 = xmm3[1,0],xmm2[1,0] ; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[1,0],xmm3[1,0]
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm3[2,0],xmm2[2,2] ; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[2,0],xmm3[2,2]
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2
; AVX1-NEXT: vpermilpd {{.*#+}} ymm3 = ymm0[1,1,3,3] ; AVX1-NEXT: vpermilpd {{.*#+}} ymm3 = ymm0[1,1,3,3]
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm3 = ymm3[2,3,2,3] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm3 = ymm3[2,3,2,3]
; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm3[2],ymm2[3,4],ymm3[5],ymm2[6,7] ; AVX1-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm3[2],ymm2[3,4],ymm3[5],ymm2[6,7]
; AVX1-NEXT: vpermilpd {{.*#+}} ymm3 = mem[1,1,2,2] ; AVX1-NEXT: vpermilpd {{.*#+}} ymm3 = mem[1,1,2,2]
; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,2] ; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,2]
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6],ymm0[7] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm3[0],ymm0[1],ymm3[2,3],ymm0[4],ymm3[5,6],ymm0[7]
; AVX1-NEXT: vpermilps {{.*#+}} ymm3 = mem[0,0,3,3,4,4,7,7] ; AVX1-NEXT: vpermilps {{.*#+}} ymm3 = mem[0,0,3,3,4,4,7,7]
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; AVX2-FAST-NEXT: vzeroupper ; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; XOP-LABEL: interleave_24i32_in: ; XOP-LABEL: interleave_24i32_in:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vmovupd (%rsi), %ymm0 ; XOP-NEXT: vmovupd (%rsi), %ymm0
; XOP-NEXT: vmovups (%rcx), %ymm1 ; XOP-NEXT: vmovups (%rcx), %ymm1
; XOP-NEXT: vmovups (%rdx), %xmm2 ; XOP-NEXT: vmovups (%rdx), %xmm2
; XOP-NEXT: vmovups 16(%rdx), %xmm3 ; XOP-NEXT: vmovups (%rsi), %xmm3
; XOP-NEXT: vmovups (%rsi), %xmm4 ; XOP-NEXT: vunpckhpd {{.*#+}} xmm4 = xmm3[1],xmm2[1]
; XOP-NEXT: vshufps {{.*#+}} xmm5 = xmm4[2,0],xmm2[2,0] ; XOP-NEXT: vshufps {{.*#+}} xmm4 = xmm2[1,1],xmm4[0,2]
; XOP-NEXT: vshufps {{.*#+}} xmm5 = xmm2[1,1],xmm5[0,2] ; XOP-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; XOP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,0],xmm4[0,0] ; XOP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[2,0],xmm3[2,1]
; XOP-NEXT: vshufps {{.*#+}} xmm2 = xmm2[2,0],xmm4[2,1] ; XOP-NEXT: vinsertf128 $1, %xmm4, %ymm2, %ymm2
; XOP-NEXT: vinsertf128 $1, %xmm5, %ymm2, %ymm2 ; XOP-NEXT: vpermilps {{.*#+}} xmm3 = mem[0,1,0,1]
; XOP-NEXT: vpermilps {{.*#+}} xmm4 = mem[0,1,0,1] ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm3, %ymm3
; XOP-NEXT: vinsertf128 $1, %xmm4, %ymm4, %ymm4 ; XOP-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm3[2],ymm2[3,4],ymm3[5],ymm2[6,7]
; XOP-NEXT: vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7] ; XOP-NEXT: vmovups 16(%rcx), %xmm3
; XOP-NEXT: vmovups 16(%rcx), %xmm4 ; XOP-NEXT: vmovups 16(%rdx), %xmm4
; XOP-NEXT: vshufps {{.*#+}} xmm5 = xmm3[3,0],xmm4[3,0] ; XOP-NEXT: vshufps {{.*#+}} xmm5 = xmm4[3,0],xmm3[3,0]
; XOP-NEXT: vshufps {{.*#+}} xmm5 = xmm4[2,1],xmm5[0,2] ; XOP-NEXT: vshufps {{.*#+}} xmm5 = xmm3[2,1],xmm5[0,2]
; XOP-NEXT: vshufps {{.*#+}} xmm4 = xmm4[1,0],xmm3[1,0] ; XOP-NEXT: vshufps {{.*#+}} xmm3 = xmm3[1,0],xmm4[1,0]
; XOP-NEXT: vshufps {{.*#+}} xmm3 = xmm4[2,0],xmm3[2,2] ; XOP-NEXT: vshufps {{.*#+}} xmm3 = xmm3[2,0],xmm4[2,2]
; XOP-NEXT: vinsertf128 $1, %xmm5, %ymm3, %ymm3 ; XOP-NEXT: vinsertf128 $1, %xmm5, %ymm3, %ymm3
; XOP-NEXT: vpermilpd {{.*#+}} ymm4 = ymm0[1,1,3,3] ; XOP-NEXT: vpermilpd {{.*#+}} ymm4 = ymm0[1,1,3,3]
; XOP-NEXT: vperm2f128 {{.*#+}} ymm4 = ymm4[2,3,2,3] ; XOP-NEXT: vperm2f128 {{.*#+}} ymm4 = ymm4[2,3,2,3]
; XOP-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7] ; XOP-NEXT: vblendps {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7]
; XOP-NEXT: vpermil2ps {{.*#+}} ymm0 = ymm1[2],ymm0[3],ymm1[2,3],ymm0[4],ymm1[5,4],ymm0[5] ; XOP-NEXT: vpermil2ps {{.*#+}} ymm0 = ymm1[2],ymm0[3],ymm1[2,3],ymm0[4],ymm1[5,4],ymm0[5]
; XOP-NEXT: vpermilps {{.*#+}} ymm1 = mem[0,0,3,3,4,4,7,7] ; XOP-NEXT: vpermilps {{.*#+}} ymm1 = mem[0,0,3,3,4,4,7,7]
; XOP-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7] ; XOP-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7]
; XOP-NEXT: vmovups %ymm0, 32(%rdi) ; XOP-NEXT: vmovups %ymm0, 32(%rdi)
▲ Show 20 Lines • Show All 459 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/oddsubvector.ll

Show All 17 Lines
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; SSE-NEXT: shrq $48, %rcx ; SSE-NEXT: shrq $48, %rcx
; SSE-NEXT: movb %cl, 6(%rdi) ; SSE-NEXT: movb %cl, 6(%rdi)
; SSE-NEXT: shrl $16, %eax ; SSE-NEXT: shrl $16, %eax
; SSE-NEXT: movw %ax, 4(%rdi) ; SSE-NEXT: movw %ax, 4(%rdi)
; SSE-NEXT: movd %xmm1, (%rdi) ; SSE-NEXT: movd %xmm1, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: insert_v7i8_v2i16_2: ; AVX-LABEL: insert_v7i8_v2i16_2:
; AVX1: # %bb.0: ; AVX: # %bb.0:
; AVX1-NEXT: movl (%rsi), %eax ; AVX-NEXT: movl (%rsi), %eax
; AVX1-NEXT: vmovd %eax, %xmm0 ; AVX-NEXT: vmovd %eax, %xmm0
; AVX1-NEXT: movq (%rdi), %rcx ; AVX-NEXT: movq (%rdi), %rcx
; AVX1-NEXT: vmovq %rcx, %xmm1 ; AVX-NEXT: vmovq %rcx, %xmm1
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; AVX-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; AVX1-NEXT: shrq $48, %rcx ; AVX-NEXT: shrq $48, %rcx
; AVX1-NEXT: movb %cl, 6(%rdi) ; AVX-NEXT: movb %cl, 6(%rdi)
; AVX1-NEXT: shrl $16, %eax ; AVX-NEXT: shrl $16, %eax
; AVX1-NEXT: movw %ax, 4(%rdi) ; AVX-NEXT: movw %ax, 4(%rdi)
; AVX1-NEXT: vmovd %xmm0, (%rdi) ; AVX-NEXT: vmovd %xmm0, (%rdi)
; AVX1-NEXT: retq ; AVX-NEXT: retq
;
; AVX2-LABEL: insert_v7i8_v2i16_2:
; AVX2: # %bb.0:
; AVX2-NEXT: movl (%rsi), %eax
; AVX2-NEXT: vmovd %eax, %xmm0
; AVX2-NEXT: movq (%rdi), %rcx
; AVX2-NEXT: vmovq %rcx, %xmm1
; AVX2-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; AVX2-NEXT: shrq $48, %rcx
; AVX2-NEXT: movb %cl, 6(%rdi)
; AVX2-NEXT: shrl $16, %eax
; AVX2-NEXT: movw %ax, 4(%rdi)
; AVX2-NEXT: vmovd %xmm0, (%rdi)
; AVX2-NEXT: retq
; ;
; AVX512-LABEL: insert_v7i8_v2i16_2: ; AVX512-LABEL: insert_v7i8_v2i16_2:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: movl (%rsi), %eax ; AVX512-NEXT: movl (%rsi), %eax
; AVX512-NEXT: vmovd %eax, %xmm0 ; AVX512-NEXT: vmovd %eax, %xmm0
; AVX512-NEXT: movq (%rdi), %rcx ; AVX512-NEXT: movq (%rdi), %rcx
; AVX512-NEXT: vmovq %rcx, %xmm1 ; AVX512-NEXT: vmovq %rcx, %xmm1
; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; AVX512-NEXT: shrq $48, %rcx ; AVX512-NEXT: shrq $48, %rcx
; AVX512-NEXT: movb %cl, 6(%rdi) ; AVX512-NEXT: movb %cl, 6(%rdi)
; AVX512-NEXT: shrl $16, %eax ; AVX512-NEXT: shrl $16, %eax
; AVX512-NEXT: movw %ax, 4(%rdi) ; AVX512-NEXT: movw %ax, 4(%rdi)
; AVX512-NEXT: vmovd %xmm0, (%rdi) ; AVX512-NEXT: vmovd %xmm0, (%rdi)
; AVX512-NEXT: retq ; AVX512-NEXT: retq
;
; XOP-LABEL: insert_v7i8_v2i16_2:
; XOP: # %bb.0:
; XOP-NEXT: movl (%rsi), %eax
; XOP-NEXT: vmovd %eax, %xmm0
; XOP-NEXT: movq (%rdi), %rcx
; XOP-NEXT: vmovq %rcx, %xmm1
; XOP-NEXT: insertq {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,1,2,3],xmm1[6,7,u,u,u,u,u,u,u,u]
; XOP-NEXT: shrq $48, %rcx
; XOP-NEXT: movb %cl, 6(%rdi)
; XOP-NEXT: shrl $16, %eax
; XOP-NEXT: movw %ax, 4(%rdi)
; XOP-NEXT: vmovd %xmm1, (%rdi)
; XOP-NEXT: retq
%1 = load <2 x i16>, <2 x i16> *%a1 %1 = load <2 x i16>, <2 x i16> *%a1
%2 = bitcast <2 x i16> %1 to <4 x i8> %2 = bitcast <2 x i16> %1 to <4 x i8>
%3 = shufflevector <4 x i8> %2, <4 x i8> undef, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef> %3 = shufflevector <4 x i8> %2, <4 x i8> undef, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef>
%4 = load <7 x i8>, <7 x i8> *%a0 %4 = load <7 x i8>, <7 x i8> *%a0
%5 = shufflevector <7 x i8> %4, <7 x i8> %3, <7 x i32> <i32 0, i32 1, i32 7, i32 8, i32 9, i32 10, i32 6> %5 = shufflevector <7 x i8> %4, <7 x i8> %3, <7 x i32> <i32 0, i32 1, i32 7, i32 8, i32 9, i32 10, i32 6>
store <7 x i8> %5, <7 x i8>* %a0 store <7 x i8> %5, <7 x i8>* %a0
ret void ret void
} }
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llvm/test/CodeGen/X86/pmul.ll

Show First 20 Lines • Show All 1,230 Lines • ▼ Show 20 Linesentry:
%rescast = bitcast <8 x i64> %res64 to <16 x i32> %rescast = bitcast <8 x i64> %res64 to <16 x i32>
%res = shufflevector <16 x i32> %rescast, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7,i32 9, i32 11, i32 13, i32 15 > %res = shufflevector <16 x i32> %rescast, <16 x i32> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7,i32 9, i32 11, i32 13, i32 15 >
ret <8 x i32> %res ret <8 x i32> %res
} }
define <8 x i64> @mul_v8i64_sext(<8 x i16> %val1, <8 x i32> %val2) { define <8 x i64> @mul_v8i64_sext(<8 x i16> %val1, <8 x i32> %val2) {
; SSE2-LABEL: mul_v8i64_sext: ; SSE2-LABEL: mul_v8i64_sext:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa %xmm1, %xmm12 ; SSE2-NEXT: movdqa %xmm1, %xmm15
; SSE2-NEXT: punpckhwd {{.*#+}} xmm10 = xmm10[4],xmm0[4],xmm10[5],xmm0[5],xmm10[6],xmm0[6],xmm10[7],xmm0[7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm14 = xmm14[4],xmm0[4],xmm14[5],xmm0[5],xmm14[6],xmm0[6],xmm14[7],xmm0[7]
; SSE2-NEXT: psrad $16, %xmm10 ; SSE2-NEXT: psrad $16, %xmm14
; SSE2-NEXT: pxor %xmm8, %xmm8
; SSE2-NEXT: pxor %xmm13, %xmm13 ; SSE2-NEXT: pxor %xmm13, %xmm13
; SSE2-NEXT: pcmpgtd %xmm10, %xmm13 ; SSE2-NEXT: pxor %xmm10, %xmm10
; SSE2-NEXT: movdqa %xmm10, %xmm9 ; SSE2-NEXT: pcmpgtd %xmm14, %xmm10
; SSE2-NEXT: punpckhdq {{.*#+}} xmm9 = xmm9[2],xmm13[2],xmm9[3],xmm13[3] ; SSE2-NEXT: movdqa %xmm14, %xmm8
; SSE2-NEXT: punpckldq {{.*#+}} xmm10 = xmm10[0],xmm13[0],xmm10[1],xmm13[1] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm8 = xmm8[2],xmm10[2],xmm8[3],xmm10[3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm14 = xmm14[0],xmm10[0],xmm14[1],xmm10[1]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; SSE2-NEXT: psrad $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0
; SSE2-NEXT: pxor %xmm15, %xmm15 ; SSE2-NEXT: pxor %xmm5, %xmm5
; SSE2-NEXT: pcmpgtd %xmm0, %xmm15 ; SSE2-NEXT: pcmpgtd %xmm0, %xmm5
; SSE2-NEXT: movdqa %xmm0, %xmm11 ; SSE2-NEXT: movdqa %xmm0, %xmm11
; SSE2-NEXT: punpckhdq {{.*#+}} xmm11 = xmm11[2],xmm15[2],xmm11[3],xmm15[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm11 = xmm11[2],xmm5[2],xmm11[3],xmm5[3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm15[0],xmm0[1],xmm15[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,0,1]
; SSE2-NEXT: pxor %xmm14, %xmm14 ; SSE2-NEXT: pxor %xmm9, %xmm9
; SSE2-NEXT: pcmpgtd %xmm3, %xmm14 ; SSE2-NEXT: pcmpgtd %xmm3, %xmm9
; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm14[0],xmm3[1],xmm14[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1]
; SSE2-NEXT: pxor %xmm5, %xmm5 ; SSE2-NEXT: pxor %xmm12, %xmm12
; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm12
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],xmm12[1]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; SSE2-NEXT: pxor %xmm6, %xmm6
; SSE2-NEXT: pcmpgtd %xmm1, %xmm6
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1]
; SSE2-NEXT: pxor %xmm7, %xmm7 ; SSE2-NEXT: pxor %xmm7, %xmm7
; SSE2-NEXT: pcmpgtd %xmm12, %xmm7 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm7
; SSE2-NEXT: punpckldq {{.*#+}} xmm12 = xmm12[0],xmm7[0],xmm12[1],xmm7[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1]
; SSE2-NEXT: movdqa %xmm15, %xmm4 ; SSE2-NEXT: pcmpgtd %xmm15, %xmm13
; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm8[0],xmm4[1],xmm8[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm15 = xmm15[0],xmm13[0],xmm15[1],xmm13[1]
; SSE2-NEXT: pmuludq %xmm12, %xmm4 ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,1,1,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm7 = xmm7[0],xmm8[0],xmm7[1],xmm8[1] ; SSE2-NEXT: pmuludq %xmm15, %xmm6
; SSE2-NEXT: pmuludq %xmm0, %xmm7 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm13[0,1,1,3]
; SSE2-NEXT: paddq %xmm4, %xmm7 ; SSE2-NEXT: pmuludq %xmm0, %xmm4
; SSE2-NEXT: psllq $32, %xmm7 ; SSE2-NEXT: paddq %xmm6, %xmm4
; SSE2-NEXT: pmuludq %xmm12, %xmm0 ; SSE2-NEXT: psllq $32, %xmm4
; SSE2-NEXT: paddq %xmm7, %xmm0 ; SSE2-NEXT: pmuludq %xmm15, %xmm0
; SSE2-NEXT: punpckhdq {{.*#+}} xmm15 = xmm15[2],xmm8[2],xmm15[3],xmm8[3] ; SSE2-NEXT: paddq %xmm4, %xmm0
; SSE2-NEXT: pmuludq %xmm1, %xmm15 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm5[2,1,3,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm8[0],xmm6[1],xmm8[1] ; SSE2-NEXT: pmuludq %xmm1, %xmm4
; SSE2-NEXT: pmuludq %xmm11, %xmm6 ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,1,1,3]
; SSE2-NEXT: paddq %xmm15, %xmm6 ; SSE2-NEXT: pmuludq %xmm11, %xmm5
; SSE2-NEXT: psllq $32, %xmm6 ; SSE2-NEXT: paddq %xmm4, %xmm5
; SSE2-NEXT: psllq $32, %xmm5
; SSE2-NEXT: pmuludq %xmm11, %xmm1 ; SSE2-NEXT: pmuludq %xmm11, %xmm1
; SSE2-NEXT: paddq %xmm6, %xmm1 ; SSE2-NEXT: paddq %xmm5, %xmm1
; SSE2-NEXT: movdqa %xmm13, %xmm4 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm10[0,1,1,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm8[0],xmm4[1],xmm8[1]
; SSE2-NEXT: pmuludq %xmm2, %xmm4 ; SSE2-NEXT: pmuludq %xmm2, %xmm4
; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm8[0],xmm5[1],xmm8[1] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm12[0,1,1,3]
; SSE2-NEXT: pmuludq %xmm10, %xmm5 ; SSE2-NEXT: pmuludq %xmm14, %xmm5
; SSE2-NEXT: paddq %xmm4, %xmm5 ; SSE2-NEXT: paddq %xmm4, %xmm5
; SSE2-NEXT: psllq $32, %xmm5 ; SSE2-NEXT: psllq $32, %xmm5
; SSE2-NEXT: pmuludq %xmm10, %xmm2 ; SSE2-NEXT: pmuludq %xmm14, %xmm2
; SSE2-NEXT: paddq %xmm5, %xmm2 ; SSE2-NEXT: paddq %xmm5, %xmm2
; SSE2-NEXT: punpckhdq {{.*#+}} xmm13 = xmm13[2],xmm8[2],xmm13[3],xmm8[3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm10[2,1,3,3]
; SSE2-NEXT: pmuludq %xmm3, %xmm13 ; SSE2-NEXT: pmuludq %xmm3, %xmm4
; SSE2-NEXT: punpckldq {{.*#+}} xmm14 = xmm14[0],xmm8[0],xmm14[1],xmm8[1] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm9[0,1,1,3]
; SSE2-NEXT: pmuludq %xmm9, %xmm14 ; SSE2-NEXT: pmuludq %xmm8, %xmm5
; SSE2-NEXT: paddq %xmm13, %xmm14 ; SSE2-NEXT: paddq %xmm4, %xmm5
; SSE2-NEXT: psllq $32, %xmm14 ; SSE2-NEXT: psllq $32, %xmm5
; SSE2-NEXT: pmuludq %xmm9, %xmm3 ; SSE2-NEXT: pmuludq %xmm8, %xmm3
; SSE2-NEXT: paddq %xmm14, %xmm3 ; SSE2-NEXT: paddq %xmm5, %xmm3
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: mul_v8i64_sext: ; SSE41-LABEL: mul_v8i64_sext:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,1,2,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[3,1,2,3]
; SSE41-NEXT: pmovsxwq %xmm3, %xmm4 ; SSE41-NEXT: pmovsxwq %xmm3, %xmm4
; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
; SSE41-NEXT: pmovsxwq %xmm3, %xmm5 ; SSE41-NEXT: pmovsxwq %xmm3, %xmm5
Show All 34 Lines; AVX512-NEXT: retq
%2 = sext <8 x i32> %val2 to <8 x i64> %2 = sext <8 x i32> %val2 to <8 x i64>
%3 = mul <8 x i64> %1, %2 %3 = mul <8 x i64> %1, %2
ret <8 x i64> %3 ret <8 x i64> %3
} }
define <2 x i64> @pmuldq_square(<2 x i64> %x) { define <2 x i64> @pmuldq_square(<2 x i64> %x) {
; SSE2-LABEL: pmuldq_square: ; SSE2-LABEL: pmuldq_square:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,2,2,3]
; SSE2-NEXT: psllq $32, %xmm0 ; SSE2-NEXT: psllq $32, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
; SSE2-NEXT: psrad $31, %xmm0 ; SSE2-NEXT: psrad $31, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,3,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE2-NEXT: psrlq $32, %xmm0 ; SSE2-NEXT: psrlq $32, %xmm0
; SSE2-NEXT: pmuludq %xmm1, %xmm0 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
; SSE2-NEXT: pmuludq %xmm1, %xmm1 ; SSE2-NEXT: pmuludq %xmm1, %xmm1
; SSE2-NEXT: paddq %xmm0, %xmm0 ; SSE2-NEXT: paddq %xmm0, %xmm0
; SSE2-NEXT: psllq $32, %xmm0 ; SSE2-NEXT: psllq $32, %xmm0
Show All 32 Lines

llvm/test/CodeGen/X86/pr29112.ll

Show All 28 Lines
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm11[0,1],xmm2[1],xmm11[3] ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm11[0,1],xmm2[1],xmm11[3]
; CHECK-NEXT: vinsertps {{.*#+}} xmm13 = xmm1[0,1,2],xmm3[1] ; CHECK-NEXT: vinsertps {{.*#+}} xmm13 = xmm1[0,1,2],xmm3[1]
; CHECK-NEXT: vinsertps {{.*#+}} xmm6 = xmm4[0,1,2],xmm3[1] ; CHECK-NEXT: vinsertps {{.*#+}} xmm6 = xmm4[0,1,2],xmm3[1]
; CHECK-NEXT: vmovaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vextractf32x4 $2, %zmm3, %xmm4 ; CHECK-NEXT: vextractf32x4 $2, %zmm3, %xmm4
; CHECK-NEXT: vblendps {{.*#+}} xmm4 = xmm1[0,1,2],xmm4[3] ; CHECK-NEXT: vblendps {{.*#+}} xmm4 = xmm1[0,1,2],xmm4[3]
; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm2[3,1,2,3] ; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm2[3,1,2,3]
; CHECK-NEXT: vunpcklps {{.*#+}} xmm5 = xmm0[0],xmm5[0],xmm0[1],xmm5[1] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm5 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
; CHECK-NEXT: vinsertps {{.*#+}} xmm5 = xmm5[0,1],xmm2[1],xmm5[3] ; CHECK-NEXT: vshufps {{.*#+}} xmm5 = xmm5[0,1],xmm2[1,3]
; CHECK-NEXT: vinsertps {{.*#+}} xmm5 = xmm5[0,1,2],xmm3[1] ; CHECK-NEXT: vinsertps {{.*#+}} xmm5 = xmm5[0,1,2],xmm3[1]
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm7[0,1],xmm2[1],xmm7[3] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm7[0,1],xmm2[1],xmm7[3]
; CHECK-NEXT: vblendps {{.*#+}} xmm7 = xmm0[0,1,2],xmm3[3] ; CHECK-NEXT: vblendps {{.*#+}} xmm7 = xmm0[0,1,2],xmm3[3]
; CHECK-NEXT: vblendps {{.*#+}} xmm12 = xmm1[0,1,2],xmm3[3] ; CHECK-NEXT: vblendps {{.*#+}} xmm12 = xmm1[0,1,2],xmm3[3]
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm8[0,1,2],xmm3[1] ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm8[0,1,2],xmm3[1]
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[1] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[1]
; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm8 ; CHECK-NEXT: vaddps %xmm1, %xmm0, %xmm8
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm11[0,1],xmm2[3],xmm11[3] ; CHECK-NEXT: vshufps {{.*#+}} xmm2 = xmm11[0,1],xmm2[3,3]
; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[2] ; CHECK-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[2]
; CHECK-NEXT: vaddps %xmm2, %xmm14, %xmm2 ; CHECK-NEXT: vaddps %xmm2, %xmm14, %xmm2
; CHECK-NEXT: vmovaps %xmm13, %xmm1 ; CHECK-NEXT: vmovaps %xmm13, %xmm1
; CHECK-NEXT: vmovaps %xmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm13, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vaddps %xmm10, %xmm13, %xmm10 ; CHECK-NEXT: vaddps %xmm10, %xmm13, %xmm10
; CHECK-NEXT: vaddps %xmm13, %xmm13, %xmm3 ; CHECK-NEXT: vaddps %xmm13, %xmm13, %xmm3
; CHECK-NEXT: vaddps %xmm12, %xmm14, %xmm0 ; CHECK-NEXT: vaddps %xmm12, %xmm14, %xmm0
; CHECK-NEXT: vaddps %xmm0, %xmm8, %xmm0 ; CHECK-NEXT: vaddps %xmm0, %xmm8, %xmm0
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/pr30430.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmovss %xmm18, {{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovss %xmm18, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovss %xmm19, {{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovss %xmm19, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovss %xmm20, {{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovss %xmm20, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovss %xmm21, {{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovss %xmm21, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovss %xmm22, {{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovss %xmm22, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovss %xmm23, {{[0-9]+}}(%rsp) ; CHECK-NEXT: vmovss %xmm23, {{[0-9]+}}(%rsp)
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; CHECK-NEXT: # implicit-def: $ymm2 ; CHECK-NEXT: # implicit-def: $ymm2
; CHECK-NEXT: vmovaps %xmm1, %xmm2 ; CHECK-NEXT: vmovaps %xmm1, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm2 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm2
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3] ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0]
; CHECK-NEXT: # implicit-def: $ymm3 ; CHECK-NEXT: # implicit-def: $ymm3
; CHECK-NEXT: vmovaps %xmm1, %xmm3 ; CHECK-NEXT: vmovaps %xmm1, %xmm3
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm3 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm3
; CHECK-NEXT: # implicit-def: $zmm24 ; CHECK-NEXT: # implicit-def: $zmm24
; CHECK-NEXT: vmovaps %zmm3, %zmm24 ; CHECK-NEXT: vmovaps %zmm3, %zmm24
; CHECK-NEXT: vinsertf64x4 $1, %ymm2, %zmm24, %zmm24 ; CHECK-NEXT: vinsertf64x4 $1, %ymm2, %zmm24, %zmm24
▲ Show 20 Lines • Show All 124 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/psubus.ll

Show First 20 Lines • Show All 555 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpcmpeqd %xmm5, %xmm5, %xmm5 ; AVX1-NEXT: vpcmpeqd %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm4 ; AVX1-NEXT: vpxor %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm6 ; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm6
; AVX1-NEXT: vpcmpeqd %xmm6, %xmm0, %xmm6 ; AVX1-NEXT: vpcmpeqd %xmm6, %xmm0, %xmm6
; AVX1-NEXT: vpxor %xmm5, %xmm6, %xmm5 ; AVX1-NEXT: vpxor %xmm5, %xmm6, %xmm5
; AVX1-NEXT: vpackssdw %xmm4, %xmm5, %xmm4 ; AVX1-NEXT: vpackssdw %xmm4, %xmm5, %xmm4
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm1 ; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpandn %xmm0, %xmm4, %xmm0 ; AVX1-NEXT: vpandn %xmm0, %xmm4, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test13: ; AVX2-LABEL: test13:
▲ Show 20 Lines • Show All 365 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpminud %xmm3, %xmm2, %xmm4 ; AVX1-NEXT: vpminud %xmm3, %xmm2, %xmm4
; AVX1-NEXT: vpcmpeqd %xmm4, %xmm2, %xmm4 ; AVX1-NEXT: vpcmpeqd %xmm4, %xmm2, %xmm4
; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm5 ; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm5
; AVX1-NEXT: vpcmpeqd %xmm5, %xmm0, %xmm5 ; AVX1-NEXT: vpcmpeqd %xmm5, %xmm0, %xmm5
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpandn %xmm0, %xmm5, %xmm0 ; AVX1-NEXT: vpandn %xmm0, %xmm5, %xmm0
; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm1 ; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm1
; AVX1-NEXT: vpandn %xmm1, %xmm4, %xmm1 ; AVX1-NEXT: vpandn %xmm1, %xmm4, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test15: ; AVX2-LABEL: test15:
; AVX2: # %bb.0: # %vector.ph ; AVX2: # %bb.0: # %vector.ph
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpminud %xmm3, %xmm2, %xmm4 ; AVX1-NEXT: vpminud %xmm3, %xmm2, %xmm4
; AVX1-NEXT: vpcmpeqd %xmm4, %xmm2, %xmm4 ; AVX1-NEXT: vpcmpeqd %xmm4, %xmm2, %xmm4
; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm5 ; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm5
; AVX1-NEXT: vpcmpeqd %xmm5, %xmm0, %xmm5 ; AVX1-NEXT: vpcmpeqd %xmm5, %xmm0, %xmm5
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpandn %xmm0, %xmm5, %xmm0 ; AVX1-NEXT: vpandn %xmm0, %xmm5, %xmm0
; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm1 ; AVX1-NEXT: vpsubd %xmm3, %xmm2, %xmm1
; AVX1-NEXT: vpandn %xmm1, %xmm4, %xmm1 ; AVX1-NEXT: vpandn %xmm1, %xmm4, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test16: ; AVX2-LABEL: test16:
; AVX2: # %bb.0: # %vector.ph ; AVX2: # %bb.0: # %vector.ph
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llvm/test/CodeGen/X86/shrink_vmul.ll

Show First 20 Lines • Show All 893 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movd %edx, %xmm0 ; X86-SSE-NEXT: movd %edx, %xmm0
; X86-SSE-NEXT: movzwl (%eax,%ecx), %eax ; X86-SSE-NEXT: movzwl (%eax,%ecx), %eax
; X86-SSE-NEXT: movd %eax, %xmm1 ; X86-SSE-NEXT: movd %eax, %xmm1
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0 ; X86-SSE-NEXT: psraw $8, %xmm0
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm1 ; X86-SSE-NEXT: psraw $8, %xmm1
; X86-SSE-NEXT: pmullw %xmm0, %xmm1 ; X86-SSE-NEXT: pmullw %xmm0, %xmm1
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,0,2,1,4,5,6,7]
; X86-SSE-NEXT: psrad $16, %xmm0 ; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%esi,%ecx,4) ; X86-SSE-NEXT: movq %xmm0, (%esi,%ecx,4)
; X86-SSE-NEXT: popl %esi ; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi8_sext: ; X86-AVX-LABEL: mul_2xi8_sext:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: pushl %esi ; X86-AVX-NEXT: pushl %esi
Show All 19 Lines
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: movzwl (%rsi,%rdx), %ecx ; X64-SSE-NEXT: movzwl (%rsi,%rdx), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm1 ; X64-SSE-NEXT: movd %ecx, %xmm1
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X64-SSE-NEXT: psraw $8, %xmm0 ; X64-SSE-NEXT: psraw $8, %xmm0
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X64-SSE-NEXT: psraw $8, %xmm1 ; X64-SSE-NEXT: psraw $8, %xmm1
; X64-SSE-NEXT: pmullw %xmm0, %xmm1 ; X64-SSE-NEXT: pmullw %xmm0, %xmm1
; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,0,2,1,4,5,6,7]
; X64-SSE-NEXT: psrad $16, %xmm0 ; X64-SSE-NEXT: psrad $16, %xmm0
; X64-SSE-NEXT: movq %xmm0, (%rax,%rdx,4) ; X64-SSE-NEXT: movq %xmm0, (%rax,%rdx,4)
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_2xi8_sext: ; X64-AVX-LABEL: mul_2xi8_sext:
; X64-AVX: # %bb.0: # %entry ; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: movq {{.*}}(%rip), %rax ; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rdx), %ecx ; X64-AVX-NEXT: movzwl (%rdi,%rdx), %ecx
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; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx ; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx
; X86-SSE-NEXT: movd %ecx, %xmm0 ; X86-SSE-NEXT: movd %ecx, %xmm0
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0 ; X86-SSE-NEXT: psraw $8, %xmm0
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X86-SSE-NEXT: psrad $16, %xmm0 ; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi8_varconst2: ; X86-AVX-LABEL: mul_2xi8_varconst2:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx ; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0 ; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0 ; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi8_varconst2: ; X64-SSE-LABEL: mul_2xi8_varconst2:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X64-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X64-SSE-NEXT: psraw $8, %xmm0 ; X64-SSE-NEXT: psraw $8, %xmm0
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; X64-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X64-SSE-NEXT: psrad $16, %xmm0 ; X64-SSE-NEXT: psrad $16, %xmm0
; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4) ; X64-SSE-NEXT: movq %xmm0, (%rax,%rsi,4)
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_2xi8_varconst2: ; X64-AVX-LABEL: mul_2xi8_varconst2:
; X64-AVX: # %bb.0: # %entry ; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: movq {{.*}}(%rip), %rax ; X64-AVX-NEXT: movq {{.*}}(%rip), %rax
; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-AVX-NEXT: movzwl (%rdi,%rsi), %ecx
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; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
; X86-SSE-NEXT: movd %xmm2, %esi ; X86-SSE-NEXT: movd %xmm2, %esi
; X86-SSE-NEXT: xorl %edx, %edx ; X86-SSE-NEXT: xorl %edx, %edx
; X86-SSE-NEXT: divl %esi ; X86-SSE-NEXT: divl %esi
; X86-SSE-NEXT: movd %edx, %xmm2 ; X86-SSE-NEXT: movd %edx, %xmm2
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1] ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0] ; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; X86-SSE-NEXT: movd %xmm0, %eax ; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,0],xmm4[0,0] ; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm4[0]
; X86-SSE-NEXT: movdqa {{.*#+}} xmm0 = [8199,8199,8199,8199] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm0 = [8199,8199,8199,8199]
; X86-SSE-NEXT: pmuludq %xmm0, %xmm7 ; X86-SSE-NEXT: pmuludq %xmm0, %xmm7
; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm7[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm7[0,2,2,3]
; X86-SSE-NEXT: pmuludq %xmm0, %xmm5 ; X86-SSE-NEXT: pmuludq %xmm0, %xmm5
; X86-SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[0,2,2,3]
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1] ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; X86-SSE-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,0],xmm1[0,0] ; X86-SSE-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm1[0]
; X86-SSE-NEXT: pmuludq %xmm0, %xmm3 ; X86-SSE-NEXT: pmuludq %xmm0, %xmm3
; X86-SSE-NEXT: pmuludq %xmm0, %xmm6 ; X86-SSE-NEXT: pmuludq %xmm0, %xmm6
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm6[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm6[0,2,2,3]
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-SSE-NEXT: xorl %edx, %edx ; X86-SSE-NEXT: xorl %edx, %edx
; X86-SSE-NEXT: divl 32(%ecx) ; X86-SSE-NEXT: divl 32(%ecx)
; X86-SSE-NEXT: movdqa %xmm0, (%eax) ; X86-SSE-NEXT: movdqa %xmm0, (%eax)
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; X64-SSE-NEXT: xorl %edx, %edx ; X64-SSE-NEXT: xorl %edx, %edx
; X64-SSE-NEXT: divl %ecx ; X64-SSE-NEXT: divl %ecx
; X64-SSE-NEXT: movd %edx, %xmm2 ; X64-SSE-NEXT: movd %edx, %xmm2
; X64-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1] ; X64-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1]
; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; X64-SSE-NEXT: movd %xmm0, %eax ; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: xorl %edx, %edx ; X64-SSE-NEXT: xorl %edx, %edx
; X64-SSE-NEXT: divl 32(%rsi) ; X64-SSE-NEXT: divl 32(%rsi)
; X64-SSE-NEXT: shufps {{.*#+}} xmm7 = xmm7[0,0],xmm5[0,0] ; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm7 = xmm7[0],xmm5[0]
; X64-SSE-NEXT: movdqa {{.*#+}} xmm0 = [8199,8199,8199,8199] ; X64-SSE-NEXT: movdqa {{.*#+}} xmm0 = [8199,8199,8199,8199]
; X64-SSE-NEXT: pmuludq %xmm0, %xmm7 ; X64-SSE-NEXT: pmuludq %xmm0, %xmm7
; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm7[0,2,2,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm7[0,2,2,3]
; X64-SSE-NEXT: pmuludq %xmm0, %xmm1 ; X64-SSE-NEXT: pmuludq %xmm0, %xmm1
; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X64-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; X64-SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; X64-SSE-NEXT: pmuludq %xmm0, %xmm4 ; X64-SSE-NEXT: pmuludq %xmm0, %xmm4
; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[0,2,2,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[0,2,2,3]
; X64-SSE-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,0],xmm8[0,0] ; X64-SSE-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm8[0]
; X64-SSE-NEXT: pmuludq %xmm0, %xmm6 ; X64-SSE-NEXT: pmuludq %xmm0, %xmm6
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,2,2,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,2,2,3]
; X64-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] ; X64-SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; X64-SSE-NEXT: imull $8199, %edx, %eax # imm = 0x2007 ; X64-SSE-NEXT: imull $8199, %edx, %eax # imm = 0x2007
; X64-SSE-NEXT: movl %eax, (%rax) ; X64-SSE-NEXT: movl %eax, (%rax)
; X64-SSE-NEXT: movdqa %xmm2, (%rax) ; X64-SSE-NEXT: movdqa %xmm2, (%rax)
; X64-SSE-NEXT: movdqa %xmm1, (%rax) ; X64-SSE-NEXT: movdqa %xmm1, (%rax)
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
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llvm/test/CodeGen/X86/shuffle-of-insert.ll

Show All 24 Lines; AVX-NEXT: retq
%shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 0, i32 5, i32 6, i32 7> %shuf = shufflevector <4 x i32> %ins, <4 x i32> %v2, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
ret <4 x i32> %shuf ret <4 x i32> %shuf
} }
define <4 x i32> @ins_elt_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) { define <4 x i32> @ins_elt_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
; SSE2-LABEL: ins_elt_1: ; SSE2-LABEL: ins_elt_1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movd %edi, %xmm0 ; SSE2-NEXT: movd %edi, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE4-LABEL: ins_elt_1: ; SSE4-LABEL: ins_elt_1:
; SSE4: # %bb.0: ; SSE4: # %bb.0:
; SSE4-NEXT: movdqa %xmm1, %xmm0 ; SSE4-NEXT: movdqa %xmm1, %xmm0
; SSE4-NEXT: pinsrd $1, %edi, %xmm0 ; SSE4-NEXT: pinsrd $1, %edi, %xmm0
; SSE4-NEXT: retq ; SSE4-NEXT: retq
Show All 33 Lines; AVX-NEXT: retq
ret <4 x i32> %shuf ret <4 x i32> %shuf
} }
define <4 x i32> @ins_elt_3_commute(i32 %x, <4 x i32> %v1, <4 x i32> %v2) { define <4 x i32> @ins_elt_3_commute(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
; SSE2-LABEL: ins_elt_3_commute: ; SSE2-LABEL: ins_elt_3_commute:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: movd %edi, %xmm1 ; SSE2-NEXT: movd %edi, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE4-LABEL: ins_elt_3_commute: ; SSE4-LABEL: ins_elt_3_commute:
; SSE4: # %bb.0: ; SSE4: # %bb.0:
; SSE4-NEXT: movdqa %xmm1, %xmm0 ; SSE4-NEXT: movdqa %xmm1, %xmm0
; SSE4-NEXT: pinsrd $3, %edi, %xmm0 ; SSE4-NEXT: pinsrd $3, %edi, %xmm0
; SSE4-NEXT: retq ; SSE4-NEXT: retq
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
ret <4 x i32> %shuf ret <4 x i32> %shuf
} }
define <4 x i32> @ins_elt_2_to_3(i32 %x, <4 x i32> %v1, <4 x i32> %v2) { define <4 x i32> @ins_elt_2_to_3(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
; SSE2-LABEL: ins_elt_2_to_3: ; SSE2-LABEL: ins_elt_2_to_3:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: movd %edi, %xmm1 ; SSE2-NEXT: movd %edi, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE4-LABEL: ins_elt_2_to_3: ; SSE4-LABEL: ins_elt_2_to_3:
; SSE4: # %bb.0: ; SSE4: # %bb.0:
; SSE4-NEXT: movdqa %xmm1, %xmm0 ; SSE4-NEXT: movdqa %xmm1, %xmm0
; SSE4-NEXT: pinsrd $3, %edi, %xmm0 ; SSE4-NEXT: pinsrd $3, %edi, %xmm0
; SSE4-NEXT: retq ; SSE4-NEXT: retq
; ;
; AVX-LABEL: ins_elt_2_to_3: ; AVX-LABEL: ins_elt_2_to_3:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpinsrd $3, %edi, %xmm1, %xmm0 ; AVX-NEXT: vpinsrd $3, %edi, %xmm1, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%ins = insertelement <4 x i32> %v1, i32 %x, i32 2 %ins = insertelement <4 x i32> %v1, i32 %x, i32 2
%shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 2, i32 6> %shuf = shufflevector <4 x i32> %v2, <4 x i32> %ins, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
ret <4 x i32> %shuf ret <4 x i32> %shuf
} }
define <4 x i32> @ins_elt_3_to_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) { define <4 x i32> @ins_elt_3_to_1(i32 %x, <4 x i32> %v1, <4 x i32> %v2) {
; SSE2-LABEL: ins_elt_3_to_1: ; SSE2-LABEL: ins_elt_3_to_1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movd %edi, %xmm0 ; SSE2-NEXT: movd %edi, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE4-LABEL: ins_elt_3_to_1: ; SSE4-LABEL: ins_elt_3_to_1:
; SSE4: # %bb.0: ; SSE4: # %bb.0:
; SSE4-NEXT: movdqa %xmm1, %xmm0 ; SSE4-NEXT: movdqa %xmm1, %xmm0
; SSE4-NEXT: pinsrd $1, %edi, %xmm0 ; SSE4-NEXT: pinsrd $1, %edi, %xmm0
; SSE4-NEXT: retq ; SSE4-NEXT: retq
Show All 10 Lines

llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX2-SLOW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX2-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX2-FAST ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX2-FAST
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512F ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX512 --check-prefix=AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512VL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512VL
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL
define void @shuffle_v16i8_to_v8i8_1(<16 x i8>* %L, <8 x i8>* %S) nounwind { define void @shuffle_v16i8_to_v8i8_1(<16 x i8>* %L, <8 x i8>* %S) nounwind {
; SSE2-LABEL: shuffle_v16i8_to_v8i8_1: ; SSE2-LABEL: shuffle_v16i8_to_v8i8_1:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rdi), %xmm0 ; SSE2-NEXT: movdqa (%rdi), %xmm0
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: psrlw $8, %xmm0
; SSE2-NEXT: movdqa %xmm0, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,1,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,1,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: packuswb %xmm0, %xmm0 ; SSE2-NEXT: packuswb %xmm0, %xmm0
; SSE2-NEXT: movq %xmm0, (%rsi) ; SSE2-NEXT: movq %xmm0, (%rsi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE42-LABEL: shuffle_v16i8_to_v8i8_1: ; SSE42-LABEL: shuffle_v16i8_to_v8i8_1:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: movdqa (%rdi), %xmm0 ; SSE42-NEXT: movdqa (%rdi), %xmm0
; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u] ; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u]
▲ Show 20 Lines • Show All 671 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines; AVX512BWVL-NEXT: retq
ret void ret void
} }
define void @shuffle_v32i16_to_v16i16_1(<32 x i16>* %L, <16 x i16>* %S) nounwind { define void @shuffle_v32i16_to_v16i16_1(<32 x i16>* %L, <16 x i16>* %S) nounwind {
; AVX512F-LABEL: shuffle_v32i16_to_v16i16_1: ; AVX512F-LABEL: shuffle_v32i16_to_v16i16_1:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %ymm0 ; AVX512F-NEXT: vmovdqa (%rdi), %ymm0
; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX512F-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX512F-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[6,7,2,3,4,5,6,7,2,3,6,7,10,11,14,15,22,23,18,19,20,21,22,23,18,19,22,23,26,27,30,31] ; AVX512F-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,2,3,6,7,10,11,14,15,u,u,u,u,u,u,u,u,18,19,22,23,26,27,30,31]
; AVX512F-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15,18,19,22,23,26,27,30,31,30,31,26,27,28,29,30,31] ; AVX512F-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,u,u,u,u,u,u,u,u,18,19,22,23,26,27,30,31,u,u,u,u,u,u,u,u]
; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] ; AVX512F-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX512F-NEXT: vmovdqa %ymm0, (%rsi) ; AVX512F-NEXT: vmovdqa %ymm0, (%rsi)
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v32i16_to_v16i16_1: ; AVX512VL-LABEL: shuffle_v32i16_to_v16i16_1:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %ymm0 ; AVX512VL-NEXT: vmovdqa (%rdi), %ymm0
; AVX512VL-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX512VL-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX512VL-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[6,7,2,3,4,5,6,7,2,3,6,7,10,11,14,15,22,23,18,19,20,21,22,23,18,19,22,23,26,27,30,31] ; AVX512VL-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,2,3,6,7,10,11,14,15,u,u,u,u,u,u,u,u,18,19,22,23,26,27,30,31]
; AVX512VL-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15,18,19,22,23,26,27,30,31,30,31,26,27,28,29,30,31] ; AVX512VL-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,u,u,u,u,u,u,u,u,18,19,22,23,26,27,30,31,u,u,u,u,u,u,u,u]
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,5,7] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,5,7]
; AVX512VL-NEXT: vpermi2q %ymm1, %ymm0, %ymm2 ; AVX512VL-NEXT: vpermi2q %ymm1, %ymm0, %ymm2
; AVX512VL-NEXT: vmovdqa %ymm2, (%rsi) ; AVX512VL-NEXT: vmovdqa %ymm2, (%rsi)
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: shuffle_v32i16_to_v16i16_1: ; AVX512BW-LABEL: shuffle_v32i16_to_v16i16_1:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa (%rdi), %ymm0 ; AVX512BW-NEXT: vmovdqa (%rdi), %ymm0
; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX512BW-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[6,7,2,3,4,5,6,7,2,3,6,7,10,11,14,15,22,23,18,19,20,21,22,23,18,19,22,23,26,27,30,31] ; AVX512BW-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,2,3,6,7,10,11,14,15,u,u,u,u,u,u,u,u,18,19,22,23,26,27,30,31]
; AVX512BW-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,14,15,10,11,12,13,14,15,18,19,22,23,26,27,30,31,30,31,26,27,28,29,30,31] ; AVX512BW-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,u,u,u,u,u,u,u,u,18,19,22,23,26,27,30,31,u,u,u,u,u,u,u,u]
; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] ; AVX512BW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
; AVX512BW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX512BW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX512BW-NEXT: vmovdqa %ymm0, (%rsi) ; AVX512BW-NEXT: vmovdqa %ymm0, (%rsi)
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512BWVL-LABEL: shuffle_v32i16_to_v16i16_1: ; AVX512BWVL-LABEL: shuffle_v32i16_to_v16i16_1:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
▲ Show 20 Lines • Show All 495 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines; AVX512VBMIVL-NEXT: retq
ret void ret void
} }
define void @trunc_v8i32_to_v8i16(<16 x i16>* %L, <8 x i16>* %S) nounwind { define void @trunc_v8i32_to_v8i16(<16 x i16>* %L, <8 x i16>* %S) nounwind {
; AVX1-LABEL: trunc_v8i32_to_v8i16: ; AVX1-LABEL: trunc_v8i32_to_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovdqa (%rdi), %xmm0 ; AVX1-NEXT: vmovdqa (%rdi), %xmm0
; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vmovdqa %xmm0, (%rsi) ; AVX1-NEXT: vmovdqa %xmm0, (%rsi)
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_v8i32_to_v8i16: ; AVX2-LABEL: trunc_v8i32_to_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
▲ Show 20 Lines • Show All 532 Lines • ▼ Show 20 Lines
; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-SLOW-NEXT: vzeroupper ; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: trunc_v4i64_to_v4i16_return_v2i64: ; AVX2-FAST-LABEL: trunc_v4i64_to_v4i16_return_v2i64:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,8,9,8,9,10,11,8,9,10,11,12,13,14,15] ; AVX2-FAST-NEXT: vmovdqa {{.*#+}} xmm2 = <0,1,8,9,u,u,u,u,u,u,u,u,u,u,u,u>
; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-FAST-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX2-FAST-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-FAST-NEXT: vzeroupper ; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512F-LABEL: trunc_v4i64_to_v4i16_return_v2i64: ; AVX512F-LABEL: trunc_v4i64_to_v4i16_return_v2i64:
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; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX2-SLOW-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-SLOW-NEXT: vzeroupper ; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: trunc_v4i64_to_v4i16_return_v8i16: ; AVX2-FAST-LABEL: trunc_v4i64_to_v4i16_return_v8i16:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,8,9,8,9,10,11,8,9,10,11,12,13,14,15] ; AVX2-FAST-NEXT: vmovdqa {{.*#+}} xmm2 = <0,1,8,9,u,u,u,u,u,u,u,u,u,u,u,u>
; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm1, %xmm1
; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX2-FAST-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-FAST-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero ; AVX2-FAST-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
; AVX2-FAST-NEXT: vzeroupper ; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512F-LABEL: trunc_v4i64_to_v4i16_return_v8i16: ; AVX512F-LABEL: trunc_v4i64_to_v4i16_return_v8i16:
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llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll

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; AVX512F-NEXT: vmovaps %ymm0, (%rsi) ; AVX512F-NEXT: vmovaps %ymm0, (%rsi)
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v32i16_to_v16i16: ; AVX512VL-LABEL: shuffle_v32i16_to_v16i16:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %ymm0 ; AVX512VL-NEXT: vmovdqa (%rdi), %ymm0
; AVX512VL-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX512VL-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,4,5,6,7,8,9,12,13,12,13,14,15,16,17,20,21,20,21,22,23,24,25,28,29,28,29,30,31] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = <0,1,4,5,u,u,u,u,8,9,12,13,u,u,u,u,16,17,20,21,u,u,u,u,24,25,28,29,u,u,u,u>
; AVX512VL-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX512VL-NEXT: vpshufb %ymm2, %ymm1, %ymm1
; AVX512VL-NEXT: vpshufb %ymm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vpshufb %ymm2, %ymm0, %ymm0
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,4,6,8,10,12,14] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,4,6,8,10,12,14]
; AVX512VL-NEXT: vpermi2d %ymm1, %ymm0, %ymm2 ; AVX512VL-NEXT: vpermi2d %ymm1, %ymm0, %ymm2
; AVX512VL-NEXT: vmovdqa %ymm2, (%rsi) ; AVX512VL-NEXT: vmovdqa %ymm2, (%rsi)
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: shuffle_v32i16_to_v16i16: ; AVX512BW-LABEL: shuffle_v32i16_to_v16i16:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqa (%rdi), %ymm0 ; AVX512BW-NEXT: vmovdqa (%rdi), %ymm0
; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,4,5,6,7,8,9,12,13,12,13,14,15,16,17,20,21,20,21,22,23,24,25,28,29,28,29,30,31] ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm2 = <0,1,4,5,u,u,u,u,8,9,12,13,u,u,u,u,16,17,20,21,u,u,u,u,24,25,28,29,u,u,u,u>
; AVX512BW-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX512BW-NEXT: vpshufb %ymm2, %ymm1, %ymm1
; AVX512BW-NEXT: vpshufb %ymm2, %ymm0, %ymm0 ; AVX512BW-NEXT: vpshufb %ymm2, %ymm0, %ymm0
; AVX512BW-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6] ; AVX512BW-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX512BW-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX512BW-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX512BW-NEXT: vmovaps %ymm0, (%rsi) ; AVX512BW-NEXT: vmovaps %ymm0, (%rsi)
; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512BWVL-LABEL: shuffle_v32i16_to_v16i16: ; AVX512BWVL-LABEL: shuffle_v32i16_to_v16i16:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vmovdqa (%rdi), %ymm0 ; AVX512BWVL-NEXT: vmovdqa (%rdi), %ymm0
; AVX512BWVL-NEXT: vmovdqa {{.*#+}} ymm1 = [0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30] ; AVX512BWVL-NEXT: vmovdqa {{.*#+}} ymm1 = [0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30]
; AVX512BWVL-NEXT: vpermi2w 32(%rdi), %ymm0, %ymm1 ; AVX512BWVL-NEXT: vpermi2w 32(%rdi), %ymm0, %ymm1
; AVX512BWVL-NEXT: vmovdqa %ymm1, (%rsi) ; AVX512BWVL-NEXT: vmovdqa %ymm1, (%rsi)
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; AVX512VBMI-LABEL: shuffle_v32i16_to_v16i16: ; AVX512VBMI-LABEL: shuffle_v32i16_to_v16i16:
; AVX512VBMI: # %bb.0: ; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: vmovdqa (%rdi), %ymm0 ; AVX512VBMI-NEXT: vmovdqa (%rdi), %ymm0
; AVX512VBMI-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX512VBMI-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX512VBMI-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,4,5,6,7,8,9,12,13,12,13,14,15,16,17,20,21,20,21,22,23,24,25,28,29,28,29,30,31] ; AVX512VBMI-NEXT: vmovdqa {{.*#+}} ymm2 = <0,1,4,5,u,u,u,u,8,9,12,13,u,u,u,u,16,17,20,21,u,u,u,u,24,25,28,29,u,u,u,u>
; AVX512VBMI-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX512VBMI-NEXT: vpshufb %ymm2, %ymm1, %ymm1
; AVX512VBMI-NEXT: vpshufb %ymm2, %ymm0, %ymm0 ; AVX512VBMI-NEXT: vpshufb %ymm2, %ymm0, %ymm0
; AVX512VBMI-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6] ; AVX512VBMI-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm1[0,2],ymm0[4,6],ymm1[4,6]
; AVX512VBMI-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3] ; AVX512VBMI-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,1,3]
; AVX512VBMI-NEXT: vmovaps %ymm0, (%rsi) ; AVX512VBMI-NEXT: vmovaps %ymm0, (%rsi)
; AVX512VBMI-NEXT: vzeroupper ; AVX512VBMI-NEXT: vzeroupper
; AVX512VBMI-NEXT: retq ; AVX512VBMI-NEXT: retq
; ;
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; AVX512BWVL-NEXT: vpshufb %xmm3, %xmm0, %xmm0 ; AVX512BWVL-NEXT: vpshufb %xmm3, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX512BWVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; AVX512BWVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_61: ; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_61:
; AVX512VBMI: # %bb.0: ; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61] ; AVX512VBMI-NEXT: vpbroadcastq {{.*#+}} zmm1 = [5569058560453190945,5569058560453190945,5569058560453190945,5569058560453190945,5569058560453190945,5569058560453190945,5569058560453190945,5569058560453190945]
; AVX512VBMI-NEXT: vpermb %zmm0, %zmm1, %zmm0 ; AVX512VBMI-NEXT: vextracti64x4 $1, %zmm0, %ymm2
; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512VBMI-NEXT: vextracti128 $1, %ymm2, %xmm2
; AVX512VBMI-NEXT: vpermi2b %zmm2, %zmm0, %zmm1
; AVX512VBMI-NEXT: vpbroadcastq {{.*#+}} zmm2 = [6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281]
; AVX512VBMI-NEXT: vpermi2b %zmm0, %zmm0, %zmm2
; AVX512VBMI-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0,1],xmm1[2,3]
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Worse

xbolva00: Worse
RKSimonAuthorUnsubmitted
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still looking at these regressions - but we've always been very weak at shuffle combining different src/dst vector widths.

RKSimon: still looking at these regressions - but we've always been very weak at shuffle combining…
; AVX512VBMI-NEXT: vzeroupper ; AVX512VBMI-NEXT: vzeroupper
; AVX512VBMI-NEXT: retq ; AVX512VBMI-NEXT: retq
; ;
; AVX512VBMIVL-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_61: ; AVX512VBMIVL-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_61:
; AVX512VBMIVL: # %bb.0: ; AVX512VBMIVL: # %bb.0:
; AVX512VBMIVL-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61] ; AVX512VBMIVL-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61]
; AVX512VBMIVL-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; AVX512VBMIVL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
; AVX512VBMIVL-NEXT: vpermt2b %ymm2, %ymm1, %ymm0 ; AVX512VBMIVL-NEXT: vpermt2b %ymm2, %ymm1, %ymm0
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; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u] ; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,1,5,9,13,u,u,u,u,u,u,u,u]
; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; AVX512BWVL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX512BWVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] ; AVX512BWVL-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62: ; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:
; AVX512VBMI: # %bb.0: ; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,62] ; AVX512VBMI-NEXT: vpbroadcastq {{.*#+}} zmm1 = [5641116154491118881,5641116154491118881,5641116154491118881,5641116154491118881,5641116154491118881,5641116154491118881,5641116154491118881,5641116154491118881]
; AVX512VBMI-NEXT: vpermb %zmm0, %zmm1, %zmm0 ; AVX512VBMI-NEXT: vextracti64x4 $1, %zmm0, %ymm2
; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512VBMI-NEXT: vextracti128 $1, %ymm2, %xmm2
; AVX512VBMI-NEXT: vpermi2b %zmm2, %zmm0, %zmm1
; AVX512VBMI-NEXT: vpbroadcastq {{.*#+}} zmm2 = [6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281,6726501325053953281]
; AVX512VBMI-NEXT: vpermi2b %zmm0, %zmm0, %zmm2
; AVX512VBMI-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0,1],xmm1[2,3]
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Ouch

xbolva00: Ouch
; AVX512VBMI-NEXT: vzeroupper ; AVX512VBMI-NEXT: vzeroupper
; AVX512VBMI-NEXT: retq ; AVX512VBMI-NEXT: retq
; ;
; AVX512VBMIVL-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62: ; AVX512VBMIVL-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:
; AVX512VBMIVL: # %bb.0: ; AVX512VBMIVL: # %bb.0:
; AVX512VBMIVL-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,62] ; AVX512VBMIVL-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,62]
; AVX512VBMIVL-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; AVX512VBMIVL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
; AVX512VBMIVL-NEXT: vpermt2b %ymm2, %ymm1, %ymm0 ; AVX512VBMIVL-NEXT: vpermt2b %ymm2, %ymm1, %ymm0
; AVX512VBMIVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512VBMIVL-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512VBMIVL-NEXT: vzeroupper ; AVX512VBMIVL-NEXT: vzeroupper
; AVX512VBMIVL-NEXT: retq ; AVX512VBMIVL-NEXT: retq
%res = shufflevector <64 x i8> %x, <64 x i8> %x, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 62> %res = shufflevector <64 x i8> %x, <64 x i8> %x, <16 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29, i32 33, i32 37, i32 41, i32 45, i32 49, i32 53, i32 57, i32 62>
ret <16 x i8> %res ret <16 x i8> %res
} }
define <4 x double> @PR34175(<32 x i16>* %p) { define <4 x double> @PR34175(<32 x i16>* %p) {
; AVX512F-LABEL: PR34175: ; AVX512F-LABEL: PR34175:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqu (%rdi), %xmm0 ; AVX512F-NEXT: vmovdqu (%rdi), %xmm0
; AVX512F-NEXT: vmovdqu 32(%rdi), %xmm1 ; AVX512F-NEXT: vmovdqu 32(%rdi), %xmm1
; AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] ; AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3]
; AVX512F-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; AVX512F-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] ; AVX512F-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512F-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX512F-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: PR34175: ; AVX512VL-LABEL: PR34175:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqu (%rdi), %xmm0 ; AVX512VL-NEXT: vmovdqu (%rdi), %xmm0
; AVX512VL-NEXT: vmovdqu 32(%rdi), %xmm1 ; AVX512VL-NEXT: vmovdqu 32(%rdi), %xmm1
; AVX512VL-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] ; AVX512VL-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3]
; AVX512VL-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3] ; AVX512VL-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [0,4,2,3] ; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512VL-NEXT: vpermi2d %xmm1, %xmm0, %xmm2 ; AVX512VL-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
; AVX512VL-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512VL-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; AVX512BW-LABEL: PR34175: ; AVX512BW-LABEL: PR34175:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vmovdqu (%rdi), %xmm0 ; AVX512BW-NEXT: vmovdqu (%rdi), %xmm0
; AVX512BW-NEXT: vmovdqu 32(%rdi), %xmm1 ; AVX512BW-NEXT: vmovdqu 32(%rdi), %xmm1
; AVX512BW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; AVX512BW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] ; AVX512BW-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3]
; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; AVX512BW-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] ; AVX512BW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512BW-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX512BW-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX512BW-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512BW-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512BW-NEXT: retq ; AVX512BW-NEXT: retq
; ;
; AVX512BWVL-LABEL: PR34175: ; AVX512BWVL-LABEL: PR34175:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vmovdqu (%rdi), %ymm0 ; AVX512BWVL-NEXT: vmovdqu (%rdi), %ymm0
; AVX512BWVL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [6755468161056768,6755468161056768,6755468161056768,6755468161056768] ; AVX512BWVL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [6755468161056768,6755468161056768,6755468161056768,6755468161056768]
; AVX512BWVL-NEXT: vpermi2w 32(%rdi), %ymm0, %ymm1 ; AVX512BWVL-NEXT: vpermi2w 32(%rdi), %ymm0, %ymm1
; AVX512BWVL-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero ; AVX512BWVL-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
; AVX512BWVL-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512BWVL-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; AVX512VBMI-LABEL: PR34175: ; AVX512VBMI-LABEL: PR34175:
; AVX512VBMI: # %bb.0: ; AVX512VBMI: # %bb.0:
; AVX512VBMI-NEXT: vmovdqu (%rdi), %xmm0 ; AVX512VBMI-NEXT: vmovdqu (%rdi), %xmm0
; AVX512VBMI-NEXT: vmovdqu 32(%rdi), %xmm1 ; AVX512VBMI-NEXT: vmovdqu 32(%rdi), %xmm1
; AVX512VBMI-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; AVX512VBMI-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3] ; AVX512VBMI-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1],xmm1[2],mem[2],xmm1[3],mem[3]
; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; AVX512VBMI-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; AVX512VBMI-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] ; AVX512VBMI-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512VBMI-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX512VBMI-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX512VBMI-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512VBMI-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512VBMI-NEXT: retq ; AVX512VBMI-NEXT: retq
; ;
; AVX512VBMIVL-LABEL: PR34175: ; AVX512VBMIVL-LABEL: PR34175:
; AVX512VBMIVL: # %bb.0: ; AVX512VBMIVL: # %bb.0:
; AVX512VBMIVL-NEXT: vmovdqu (%rdi), %ymm0 ; AVX512VBMIVL-NEXT: vmovdqu (%rdi), %ymm0
; AVX512VBMIVL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [6755468161056768,6755468161056768,6755468161056768,6755468161056768] ; AVX512VBMIVL-NEXT: vpbroadcastq {{.*#+}} ymm1 = [6755468161056768,6755468161056768,6755468161056768,6755468161056768]
Show All 22 Lines

llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll

Show First 20 Lines • Show All 1,069 Lines • ▼ Show 20 Lines; CHECK-AVX512VL-NEXT: retq
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor in odd+even divisor ; One power-of-two divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_srem_odd_even_poweroftwo: ; CHECK-SSE2-LABEL: test_srem_odd_even_poweroftwo:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1717986919,2454267027,2147483649,1374389535]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1717986919,2454267027,2147483649,1374389535]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: pmuludq %xmm5, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pxor %xmm4, %xmm4 ; CHECK-SSE2-NEXT: pxor %xmm5, %xmm5
; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm4 ; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm5
; CHECK-SSE2-NEXT: pand %xmm5, %xmm4 ; CHECK-SSE2-NEXT: pand %xmm2, %xmm5
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [0,4294967295,4294967295,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,4294967295,4294967295,0]
; CHECK-SSE2-NEXT: pand %xmm0, %xmm5 ; CHECK-SSE2-NEXT: pand %xmm0, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm4, %xmm5
; CHECK-SSE2-NEXT: psubd %xmm5, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrad $5, %xmm3
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm4
; CHECK-SSE2-NEXT: psrad $3, %xmm4
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm5
; CHECK-SSE2-NEXT: psrad $1, %xmm5
; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm4 = xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm4[0,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm5, %xmm2 ; CHECK-SSE2-NEXT: paddd %xmm5, %xmm2
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [5,14,16,100] ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: movl $1, %eax
; CHECK-SSE2-NEXT: movd %eax, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,1,1,0]
; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm4
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm2
; CHECK-SSE2-NEXT: psrad $5, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm3
; CHECK-SSE2-NEXT: psrad $3, %xmm3
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm5
; CHECK-SSE2-NEXT: psrad $1, %xmm5
; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm3[0]
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm3[0,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm4
; CHECK-SSE2-NEXT: paddd %xmm5, %xmm4
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [5,14,16,100]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm3 ; CHECK-SSE2-NEXT: psubd %xmm4, %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_srem_odd_even_poweroftwo: ; CHECK-SSE41-LABEL: test_srem_odd_even_poweroftwo:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2454267027,2147483649,1374389535] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2454267027,2147483649,1374389535]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines; CHECK-AVX512VL-NEXT: retq
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One one divisor in odd+even divisor ; One one divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_srem_odd_even_one: ; CHECK-SSE2-LABEL: test_srem_odd_even_one:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1717986919,2454267027,0,1374389535]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1717986919,2454267027,0,1374389535]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: pmuludq %xmm5, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pxor %xmm4, %xmm4 ; CHECK-SSE2-NEXT: pxor %xmm5, %xmm5
; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm4 ; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm5
; CHECK-SSE2-NEXT: pand %xmm5, %xmm4 ; CHECK-SSE2-NEXT: pand %xmm2, %xmm5
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [0,4294967295,0,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,4294967295,0,0]
; CHECK-SSE2-NEXT: pand %xmm0, %xmm5 ; CHECK-SSE2-NEXT: pand %xmm0, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm4, %xmm5
; CHECK-SSE2-NEXT: psubd %xmm5, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrad $5, %xmm3
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm4
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm4 = xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrad $3, %xmm3
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm5
; CHECK-SSE2-NEXT: psrad $1, %xmm5
; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm3[0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm4[0,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm2
; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: paddd %xmm5, %xmm2 ; CHECK-SSE2-NEXT: paddd %xmm5, %xmm2
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [5,14,1,100] ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: movl $1, %eax
; CHECK-SSE2-NEXT: movd %eax, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,1,1,0]
; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm4
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm2
; CHECK-SSE2-NEXT: psrad $5, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm3
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm2
; CHECK-SSE2-NEXT: psrad $3, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm5
; CHECK-SSE2-NEXT: psrad $1, %xmm5
; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm3[0,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm4
; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm4
; CHECK-SSE2-NEXT: paddd %xmm5, %xmm4
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [5,14,1,100]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm3 ; CHECK-SSE2-NEXT: psubd %xmm4, %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_srem_odd_even_one: ; CHECK-SSE41-LABEL: test_srem_odd_even_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2454267027,0,1374389535] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2454267027,0,1374389535]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
▲ Show 20 Lines • Show All 1,239 Lines • ▼ Show 20 Lines
} }
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; One power-of-two divisor divisor and one divisor in odd divisor ; One power-of-two divisor divisor and one divisor in odd divisor
define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_srem_odd_poweroftwo_and_one: ; CHECK-SSE2-LABEL: test_srem_odd_poweroftwo_and_one:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1717986919,2147483649,0,1717986919]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1717986919,2147483649,0,1717986919]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: pmuludq %xmm5, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pxor %xmm4, %xmm4 ; CHECK-SSE2-NEXT: pxor %xmm5, %xmm5
; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm4 ; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm5
; CHECK-SSE2-NEXT: pand %xmm5, %xmm4 ; CHECK-SSE2-NEXT: pand %xmm2, %xmm5
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [0,4294967295,0,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,4294967295,0,0]
; CHECK-SSE2-NEXT: pand %xmm0, %xmm5 ; CHECK-SSE2-NEXT: pand %xmm0, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm4, %xmm5 ; CHECK-SSE2-NEXT: paddd %xmm5, %xmm2
; CHECK-SSE2-NEXT: psubd %xmm5, %xmm2 ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm3
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm2 ; CHECK-SSE2-NEXT: movl $1, %eax
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3 ; CHECK-SSE2-NEXT: movd %eax, %xmm2
; CHECK-SSE2-NEXT: psrad $1, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm4 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm4 = xmm4[1],xmm3[1] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,1,1,0]
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm5 ; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm4
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm2
; CHECK-SSE2-NEXT: psrad $1, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm3
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm5
; CHECK-SSE2-NEXT: psrad $3, %xmm5 ; CHECK-SSE2-NEXT: psrad $3, %xmm5
; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0] ; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,3],xmm4[0,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm3[0,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm2 ; CHECK-SSE2-NEXT: psrld $31, %xmm4
; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm4
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm2 ; CHECK-SSE2-NEXT: paddd %xmm2, %xmm4
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [5,16,1,5] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [5,16,1,5]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm3 ; CHECK-SSE2-NEXT: psubd %xmm4, %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_srem_odd_poweroftwo_and_one: ; CHECK-SSE41-LABEL: test_srem_odd_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2147483649,0,1717986919] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2147483649,0,1717986919]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Lines; CHECK-AVX512VL-NEXT: retq
%ret = zext <4 x i1> %cmp to <4 x i32> %ret = zext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %ret ret <4 x i32> %ret
} }
; One power-of-two divisor divisor and one divisor in odd+even divisor ; One power-of-two divisor divisor and one divisor in odd+even divisor
define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind { define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_srem_odd_even_poweroftwo_and_one: ; CHECK-SSE2-LABEL: test_srem_odd_even_poweroftwo_and_one:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,1,1,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1717986919,2147483649,0,1374389535]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1717986919,2147483649,0,1374389535]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: pmuludq %xmm5, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pxor %xmm4, %xmm4 ; CHECK-SSE2-NEXT: pxor %xmm5, %xmm5
; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm4 ; CHECK-SSE2-NEXT: pcmpgtd %xmm0, %xmm5
; CHECK-SSE2-NEXT: pand %xmm5, %xmm4 ; CHECK-SSE2-NEXT: pand %xmm2, %xmm5
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [0,4294967295,0,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,4294967295,0,0]
; CHECK-SSE2-NEXT: pand %xmm0, %xmm5 ; CHECK-SSE2-NEXT: pand %xmm0, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm4, %xmm5
; CHECK-SSE2-NEXT: psubd %xmm5, %xmm2
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrad $5, %xmm3
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm4
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm4 = xmm4[1],xmm3[1]
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrad $3, %xmm3
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm5
; CHECK-SSE2-NEXT: psrad $1, %xmm5
; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm3[0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm4[0,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm2
; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: paddd %xmm5, %xmm2 ; CHECK-SSE2-NEXT: paddd %xmm5, %xmm2
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [5,16,1,100] ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: movl $1, %eax
; CHECK-SSE2-NEXT: movd %eax, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,1,1,0]
; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: paddd %xmm3, %xmm4
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm2
; CHECK-SSE2-NEXT: psrad $5, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm3
; CHECK-SSE2-NEXT: punpckhqdq {{.*#+}} xmm3 = xmm3[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm2
; CHECK-SSE2-NEXT: psrad $3, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm4, %xmm5
; CHECK-SSE2-NEXT: psrad $1, %xmm5
; CHECK-SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm2[0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,3],xmm3[0,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm4
; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm4
; CHECK-SSE2-NEXT: paddd %xmm5, %xmm4
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [5,16,1,100]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm3 ; CHECK-SSE2-NEXT: psubd %xmm4, %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_srem_odd_even_poweroftwo_and_one: ; CHECK-SSE41-LABEL: test_srem_odd_even_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2147483649,0,1374389535] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1717986919,2147483649,0,1374389535]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
▲ Show 20 Lines • Show All 332 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 1,997 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: retl # encoding: [0xc3] ; X86-SSE-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX1-LABEL: test_mm_set_ps: ; X86-AVX1-LABEL: test_mm_set_ps:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10]
; X86-AVX1-NEXT: # xmm0 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm0 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c]
; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x10] ; X86-AVX1-NEXT: vunpcklps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x14,0xc1]
; X86-AVX1-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X86-AVX1-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x08] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x08]
; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vinsertps $32, %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x20] ; X86-AVX1-NEXT: vmovlhps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x16,0xc1]
; X86-AVX1-NEXT: # xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; X86-AVX1-NEXT: # xmm0 = xmm0[0],xmm1[0]
; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x04] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x04]
; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vinsertps $48, %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x30] ; X86-AVX1-NEXT: vinsertps $48, %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x30]
; X86-AVX1-NEXT: # xmm0 = xmm0[0,1,2],xmm1[0] ; X86-AVX1-NEXT: # xmm0 = xmm0[0,1,2],xmm1[0]
; X86-AVX1-NEXT: retl # encoding: [0xc3] ; X86-AVX1-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512-LABEL: test_mm_set_ps: ; X86-AVX512-LABEL: test_mm_set_ps:
; X86-AVX512: # %bb.0: ; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10]
; X86-AVX512-NEXT: # xmm0 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm0 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c]
; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x10] ; X86-AVX512-NEXT: vunpcklps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x14,0xc1]
; X86-AVX512-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X86-AVX512-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x08] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x08]
; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vinsertps $32, %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x20] ; X86-AVX512-NEXT: vinsertps $32, %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x20]
; X86-AVX512-NEXT: # xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; X86-AVX512-NEXT: # xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x04] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x04]
; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vinsertps $48, %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x30] ; X86-AVX512-NEXT: vinsertps $48, %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x30]
; X86-AVX512-NEXT: # xmm0 = xmm0[0,1,2],xmm1[0] ; X86-AVX512-NEXT: # xmm0 = xmm0[0,1,2],xmm1[0]
; X86-AVX512-NEXT: retl # encoding: [0xc3] ; X86-AVX512-NEXT: retl # encoding: [0xc3]
; ;
; X64-SSE-LABEL: test_mm_set_ps: ; X64-SSE-LABEL: test_mm_set_ps:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: unpcklps %xmm0, %xmm1 # encoding: [0x0f,0x14,0xc8] ; X64-SSE-NEXT: unpcklps %xmm0, %xmm1 # encoding: [0x0f,0x14,0xc8]
; X64-SSE-NEXT: # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; X64-SSE-NEXT: # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; X64-SSE-NEXT: unpcklps %xmm2, %xmm3 # encoding: [0x0f,0x14,0xda] ; X64-SSE-NEXT: unpcklps %xmm2, %xmm3 # encoding: [0x0f,0x14,0xda]
; X64-SSE-NEXT: # xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X64-SSE-NEXT: # xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; X64-SSE-NEXT: movlhps %xmm1, %xmm3 # encoding: [0x0f,0x16,0xd9] ; X64-SSE-NEXT: movlhps %xmm1, %xmm3 # encoding: [0x0f,0x16,0xd9]
; X64-SSE-NEXT: # xmm3 = xmm3[0],xmm1[0] ; X64-SSE-NEXT: # xmm3 = xmm3[0],xmm1[0]
; X64-SSE-NEXT: movaps %xmm3, %xmm0 # encoding: [0x0f,0x28,0xc3] ; X64-SSE-NEXT: movaps %xmm3, %xmm0 # encoding: [0x0f,0x28,0xc3]
; X64-SSE-NEXT: retq # encoding: [0xc3] ; X64-SSE-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX1-LABEL: test_mm_set_ps: ; X64-AVX1-LABEL: test_mm_set_ps:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vinsertps $16, %xmm2, %xmm3, %xmm2 # encoding: [0xc4,0xe3,0x61,0x21,0xd2,0x10] ; X64-AVX1-NEXT: vunpcklps %xmm2, %xmm3, %xmm2 # encoding: [0xc5,0xe0,0x14,0xd2]
; X64-AVX1-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; X64-AVX1-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; X64-AVX1-NEXT: vinsertps $32, %xmm1, %xmm2, %xmm1 # encoding: [0xc4,0xe3,0x69,0x21,0xc9,0x20] ; X64-AVX1-NEXT: vmovlhps %xmm1, %xmm2, %xmm1 # encoding: [0xc5,0xe8,0x16,0xc9]
; X64-AVX1-NEXT: # xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; X64-AVX1-NEXT: # xmm1 = xmm2[0],xmm1[0]
; X64-AVX1-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30] ; X64-AVX1-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30]
; X64-AVX1-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0] ; X64-AVX1-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0]
; X64-AVX1-NEXT: retq # encoding: [0xc3] ; X64-AVX1-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512-LABEL: test_mm_set_ps: ; X64-AVX512-LABEL: test_mm_set_ps:
; X64-AVX512: # %bb.0: ; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vinsertps $16, %xmm2, %xmm3, %xmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x61,0x21,0xd2,0x10] ; X64-AVX512-NEXT: vunpcklps %xmm2, %xmm3, %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xe0,0x14,0xd2]
; X64-AVX512-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; X64-AVX512-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; X64-AVX512-NEXT: vinsertps $32, %xmm1, %xmm2, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x69,0x21,0xc9,0x20] ; X64-AVX512-NEXT: vinsertps $32, %xmm1, %xmm2, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x69,0x21,0xc9,0x20]
; X64-AVX512-NEXT: # xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; X64-AVX512-NEXT: # xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; X64-AVX512-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30] ; X64-AVX512-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30]
; X64-AVX512-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0] ; X64-AVX512-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0]
; X64-AVX512-NEXT: retq # encoding: [0xc3] ; X64-AVX512-NEXT: retq # encoding: [0xc3]
%res0 = insertelement <4 x float> undef, float %a3, i32 0 %res0 = insertelement <4 x float> undef, float %a3, i32 0
%res1 = insertelement <4 x float> %res0, float %a2, i32 1 %res1 = insertelement <4 x float> %res0, float %a2, i32 1
%res2 = insertelement <4 x float> %res1, float %a1, i32 2 %res2 = insertelement <4 x float> %res1, float %a1, i32 2
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; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10]
; X86-AVX1-NEXT: # xmm0 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm0 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c]
; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 # encoding: [0xc5,0xfa,0x10,0x54,0x24,0x08] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 # encoding: [0xc5,0xfa,0x10,0x54,0x24,0x08]
; X86-AVX1-NEXT: # xmm2 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm2 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm3 # encoding: [0xc5,0xfa,0x10,0x5c,0x24,0x04] ; X86-AVX1-NEXT: vmovss {{[0-9]+}}(%esp), %xmm3 # encoding: [0xc5,0xfa,0x10,0x5c,0x24,0x04]
; X86-AVX1-NEXT: # xmm3 = mem[0],zero,zero,zero ; X86-AVX1-NEXT: # xmm3 = mem[0],zero,zero,zero
; X86-AVX1-NEXT: vinsertps $16, %xmm2, %xmm3, %xmm2 # encoding: [0xc4,0xe3,0x61,0x21,0xd2,0x10] ; X86-AVX1-NEXT: vunpcklps %xmm2, %xmm3, %xmm2 # encoding: [0xc5,0xe0,0x14,0xd2]
; X86-AVX1-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; X86-AVX1-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; X86-AVX1-NEXT: vinsertps $32, %xmm1, %xmm2, %xmm1 # encoding: [0xc4,0xe3,0x69,0x21,0xc9,0x20] ; X86-AVX1-NEXT: vmovlhps %xmm1, %xmm2, %xmm1 # encoding: [0xc5,0xe8,0x16,0xc9]
; X86-AVX1-NEXT: # xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; X86-AVX1-NEXT: # xmm1 = xmm2[0],xmm1[0]
; X86-AVX1-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30] ; X86-AVX1-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30]
; X86-AVX1-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0] ; X86-AVX1-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0]
; X86-AVX1-NEXT: retl # encoding: [0xc3] ; X86-AVX1-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512-LABEL: test_mm_setr_ps: ; X86-AVX512-LABEL: test_mm_setr_ps:
; X86-AVX512: # %bb.0: ; X86-AVX512: # %bb.0:
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x44,0x24,0x10]
; X86-AVX512-NEXT: # xmm0 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm0 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x4c,0x24,0x0c]
; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm1 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x54,0x24,0x08] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x54,0x24,0x08]
; X86-AVX512-NEXT: # xmm2 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm2 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm3 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x5c,0x24,0x04] ; X86-AVX512-NEXT: vmovss {{[0-9]+}}(%esp), %xmm3 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x10,0x5c,0x24,0x04]
; X86-AVX512-NEXT: # xmm3 = mem[0],zero,zero,zero ; X86-AVX512-NEXT: # xmm3 = mem[0],zero,zero,zero
; X86-AVX512-NEXT: vinsertps $16, %xmm2, %xmm3, %xmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x61,0x21,0xd2,0x10] ; X86-AVX512-NEXT: vunpcklps %xmm2, %xmm3, %xmm2 # EVEX TO VEX Compression encoding: [0xc5,0xe0,0x14,0xd2]
; X86-AVX512-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; X86-AVX512-NEXT: # xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; X86-AVX512-NEXT: vinsertps $32, %xmm1, %xmm2, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x69,0x21,0xc9,0x20] ; X86-AVX512-NEXT: vinsertps $32, %xmm1, %xmm2, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x69,0x21,0xc9,0x20]
; X86-AVX512-NEXT: # xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; X86-AVX512-NEXT: # xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; X86-AVX512-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30] ; X86-AVX512-NEXT: vinsertps $48, %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x71,0x21,0xc0,0x30]
; X86-AVX512-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0] ; X86-AVX512-NEXT: # xmm0 = xmm1[0,1,2],xmm0[0]
; X86-AVX512-NEXT: retl # encoding: [0xc3] ; X86-AVX512-NEXT: retl # encoding: [0xc3]
; ;
; X64-SSE-LABEL: test_mm_setr_ps: ; X64-SSE-LABEL: test_mm_setr_ps:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: unpcklps %xmm3, %xmm2 # encoding: [0x0f,0x14,0xd3] ; X64-SSE-NEXT: unpcklps %xmm3, %xmm2 # encoding: [0x0f,0x14,0xd3]
; X64-SSE-NEXT: # xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; X64-SSE-NEXT: # xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; X64-SSE-NEXT: unpcklps %xmm1, %xmm0 # encoding: [0x0f,0x14,0xc1] ; X64-SSE-NEXT: unpcklps %xmm1, %xmm0 # encoding: [0x0f,0x14,0xc1]
; X64-SSE-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-SSE-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-SSE-NEXT: movlhps %xmm2, %xmm0 # encoding: [0x0f,0x16,0xc2] ; X64-SSE-NEXT: movlhps %xmm2, %xmm0 # encoding: [0x0f,0x16,0xc2]
; X64-SSE-NEXT: # xmm0 = xmm0[0],xmm2[0] ; X64-SSE-NEXT: # xmm0 = xmm0[0],xmm2[0]
; X64-SSE-NEXT: retq # encoding: [0xc3] ; X64-SSE-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX1-LABEL: test_mm_setr_ps: ; X64-AVX1-LABEL: test_mm_setr_ps:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x10] ; X64-AVX1-NEXT: vunpcklps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x14,0xc1]
; X64-AVX1-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X64-AVX1-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-AVX1-NEXT: vinsertps $32, %xmm2, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc2,0x20] ; X64-AVX1-NEXT: vmovlhps %xmm2, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x16,0xc2]
; X64-AVX1-NEXT: # xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; X64-AVX1-NEXT: # xmm0 = xmm0[0],xmm2[0]
; X64-AVX1-NEXT: vinsertps $48, %xmm3, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc3,0x30] ; X64-AVX1-NEXT: vinsertps $48, %xmm3, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x21,0xc3,0x30]
; X64-AVX1-NEXT: # xmm0 = xmm0[0,1,2],xmm3[0] ; X64-AVX1-NEXT: # xmm0 = xmm0[0,1,2],xmm3[0]
; X64-AVX1-NEXT: retq # encoding: [0xc3] ; X64-AVX1-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512-LABEL: test_mm_setr_ps: ; X64-AVX512-LABEL: test_mm_setr_ps:
; X64-AVX512: # %bb.0: ; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x10] ; X64-AVX512-NEXT: vunpcklps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x14,0xc1]
; X64-AVX512-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X64-AVX512-NEXT: # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-AVX512-NEXT: vinsertps $32, %xmm2, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc2,0x20] ; X64-AVX512-NEXT: vinsertps $32, %xmm2, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc2,0x20]
; X64-AVX512-NEXT: # xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; X64-AVX512-NEXT: # xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; X64-AVX512-NEXT: vinsertps $48, %xmm3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc3,0x30] ; X64-AVX512-NEXT: vinsertps $48, %xmm3, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc3,0x30]
; X64-AVX512-NEXT: # xmm0 = xmm0[0,1,2],xmm3[0] ; X64-AVX512-NEXT: # xmm0 = xmm0[0,1,2],xmm3[0]
; X64-AVX512-NEXT: retq # encoding: [0xc3] ; X64-AVX512-NEXT: retq # encoding: [0xc3]
%res0 = insertelement <4 x float> undef, float %a0, i32 0 %res0 = insertelement <4 x float> undef, float %a0, i32 0
%res1 = insertelement <4 x float> %res0, float %a1, i32 1 %res1 = insertelement <4 x float> %res0, float %a1, i32 1
%res2 = insertelement <4 x float> %res1, float %a2, i32 2 %res2 = insertelement <4 x float> %res1, float %a2, i32 2
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llvm/test/CodeGen/X86/sse2.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines
; ;
; X64-SSE-LABEL: test9: ; X64-SSE-LABEL: test9:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; X64-SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; X64-SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; X64-SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: test9: ; X64-AVX1-LABEL: test9:
; X64-AVX: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X64-AVX1-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; X64-AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; X64-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; X64-AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; X64-AVX-NEXT: retq ; X64-AVX1-NEXT: retq
;
; X64-AVX512-LABEL: test9:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; X64-AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; X64-AVX512-NEXT: retq
%tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1] %tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1]
%tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1] %tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1]
%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1] %tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1] %tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
ret <4 x float> %tmp13 ret <4 x float> %tmp13
} }
define <4 x float> @test10(float %a, float %b, float %c, float %d) nounwind { define <4 x float> @test10(float %a, float %b, float %c, float %d) nounwind {
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; ;
; X64-SSE-LABEL: test10: ; X64-SSE-LABEL: test10:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] ; X64-SSE-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; X64-SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-SSE-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; X64-SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: test10: ; X64-AVX1-LABEL: test10:
; X64-AVX: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; X64-AVX1-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; X64-AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; X64-AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0] ; X64-AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; X64-AVX-NEXT: retq ; X64-AVX1-NEXT: retq
;
; X64-AVX512-LABEL: test10:
; X64-AVX512: # %bb.0:
; X64-AVX512-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X64-AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; X64-AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
; X64-AVX512-NEXT: retq
%tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1] %tmp = insertelement <4 x float> undef, float %a, i32 0 ; <<4 x float>> [#uses=1]
%tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1] %tmp11 = insertelement <4 x float> %tmp, float %b, i32 1 ; <<4 x float>> [#uses=1]
%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1] %tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2 ; <<4 x float>> [#uses=1]
%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1] %tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3 ; <<4 x float>> [#uses=1]
ret <4 x float> %tmp13 ret <4 x float> %tmp13
} }
define <2 x double> @test11(double %a, double %b) nounwind { define <2 x double> @test11(double %a, double %b) nounwind {
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llvm/test/CodeGen/X86/sse3-avx-addsub-2.ll

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; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; AVX-NEXT: vsubss %xmm2, %xmm0, %xmm3 ; AVX-NEXT: vsubss %xmm2, %xmm0, %xmm3
; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
; AVX-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0] ; AVX-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0]
; AVX-NEXT: vsubss %xmm5, %xmm4, %xmm4 ; AVX-NEXT: vsubss %xmm5, %xmm4, %xmm4
; AVX-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3] ; AVX-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
; AVX-NEXT: vaddss %xmm2, %xmm5, %xmm2 ; AVX-NEXT: vaddss %xmm2, %xmm5, %xmm2
; AVX-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; AVX-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3] ; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = extractelement <4 x float> %A, i32 0 %1 = extractelement <4 x float> %A, i32 0
%2 = extractelement <4 x float> %B, i32 0 %2 = extractelement <4 x float> %B, i32 0
%sub = fsub float %1, 42.0 %sub = fsub float %1, 42.0
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; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vsubss %xmm1, %xmm0, %xmm2 ; AVX512-NEXT: vsubss %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vpermilpd {{.*#+}} xmm3 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm3 = xmm0[1,0]
; AVX512-NEXT: vpermilpd {{.*#+}} xmm4 = xmm1[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm4 = xmm1[1,0]
; AVX512-NEXT: vsubss %xmm4, %xmm3, %xmm3 ; AVX512-NEXT: vsubss %xmm4, %xmm3, %xmm3
; AVX512-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3] ; AVX512-NEXT: vmovshdup {{.*#+}} xmm4 = xmm0[1,1,3,3]
; AVX512-NEXT: vmovshdup {{.*#+}} xmm5 = xmm1[1,1,3,3] ; AVX512-NEXT: vmovshdup {{.*#+}} xmm5 = xmm1[1,1,3,3]
; AVX512-NEXT: vaddss %xmm5, %xmm4, %xmm4 ; AVX512-NEXT: vaddss %xmm5, %xmm4, %xmm4
; AVX512-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] ; AVX512-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; AVX512-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX512-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX512-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3] ; AVX512-NEXT: vpermilps {{.*#+}} xmm3 = xmm0[3,1,2,3]
; AVX512-NEXT: vpermilps {{.*#+}} xmm4 = xmm1[3,1,2,3] ; AVX512-NEXT: vpermilps {{.*#+}} xmm4 = xmm1[3,1,2,3]
; AVX512-NEXT: vaddss %xmm4, %xmm3, %xmm3 ; AVX512-NEXT: vaddss %xmm4, %xmm3, %xmm3
; AVX512-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; AVX512-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX512-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX512-NEXT: vsubss %xmm1, %xmm0, %xmm3 ; AVX512-NEXT: vsubss %xmm1, %xmm0, %xmm3
; AVX512-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm4 = xmm0[1,0]
; AVX512-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0] ; AVX512-NEXT: vpermilpd {{.*#+}} xmm5 = xmm1[1,0]
; AVX512-NEXT: vsubss %xmm5, %xmm4, %xmm4 ; AVX512-NEXT: vsubss %xmm5, %xmm4, %xmm4
; AVX512-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3] ; AVX512-NEXT: vmovshdup {{.*#+}} xmm5 = xmm0[1,1,3,3]
; AVX512-NEXT: vmovshdup {{.*#+}} xmm6 = xmm1[1,1,3,3] ; AVX512-NEXT: vmovshdup {{.*#+}} xmm6 = xmm1[1,1,3,3]
; AVX512-NEXT: vaddss %xmm6, %xmm5, %xmm5 ; AVX512-NEXT: vaddss %xmm6, %xmm5, %xmm5
; AVX512-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[2,3] ; AVX512-NEXT: vunpcklps {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1]
; AVX512-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; AVX512-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] ; AVX512-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3] ; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[3,1,2,3]
; AVX512-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0] ; AVX512-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX512-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0 ; AVX512-NEXT: vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = extractelement <16 x float> %A, i32 0 %1 = extractelement <16 x float> %A, i32 0
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llvm/test/CodeGen/X86/sse41.ll

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; X86-AVX1-NEXT: ## xmm1 = mem[0,1,2,0] ; X86-AVX1-NEXT: ## xmm1 = mem[0,1,2,0]
; X86-AVX1-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08] ; X86-AVX1-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08]
; X86-AVX1-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3] ; X86-AVX1-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3]
; X86-AVX1-NEXT: retl ## encoding: [0xc3] ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
; ;
; X86-AVX512-LABEL: pinsrd_from_shufflevector_i32: ; X86-AVX512-LABEL: pinsrd_from_shufflevector_i32:
; X86-AVX512: ## %bb.0: ## %entry ; X86-AVX512: ## %bb.0: ## %entry
; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04] ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX512-NEXT: vpermilps $36, (%eax), %xmm1 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x04,0x08,0x24] ; X86-AVX512-NEXT: vmovaps (%eax), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x08]
; X86-AVX512-NEXT: ## xmm1 = mem[0,1,2,0] ; X86-AVX512-NEXT: vbroadcastss %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x18,0xc9]
; X86-AVX512-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08] ; X86-AVX512-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08]
; X86-AVX512-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3] ; X86-AVX512-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3]
; X86-AVX512-NEXT: retl ## encoding: [0xc3] ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
; ;
; X64-SSE-LABEL: pinsrd_from_shufflevector_i32: ; X64-SSE-LABEL: pinsrd_from_shufflevector_i32:
; X64-SSE: ## %bb.0: ## %entry ; X64-SSE: ## %bb.0: ## %entry
; X64-SSE-NEXT: pshufd $36, (%rdi), %xmm1 ## encoding: [0x66,0x0f,0x70,0x0f,0x24] ; X64-SSE-NEXT: pshufd $36, (%rdi), %xmm1 ## encoding: [0x66,0x0f,0x70,0x0f,0x24]
; X64-SSE-NEXT: ## xmm1 = mem[0,1,2,0] ; X64-SSE-NEXT: ## xmm1 = mem[0,1,2,0]
; X64-SSE-NEXT: pblendw $192, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0e,0xc1,0xc0] ; X64-SSE-NEXT: pblendw $192, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x0e,0xc1,0xc0]
; X64-SSE-NEXT: ## xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7] ; X64-SSE-NEXT: ## xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
; X64-SSE-NEXT: retq ## encoding: [0xc3] ; X64-SSE-NEXT: retq ## encoding: [0xc3]
; ;
; X64-AVX1-LABEL: pinsrd_from_shufflevector_i32: ; X64-AVX1-LABEL: pinsrd_from_shufflevector_i32:
; X64-AVX1: ## %bb.0: ## %entry ; X64-AVX1: ## %bb.0: ## %entry
; X64-AVX1-NEXT: vpermilps $36, (%rdi), %xmm1 ## encoding: [0xc4,0xe3,0x79,0x04,0x0f,0x24] ; X64-AVX1-NEXT: vpermilps $36, (%rdi), %xmm1 ## encoding: [0xc4,0xe3,0x79,0x04,0x0f,0x24]
; X64-AVX1-NEXT: ## xmm1 = mem[0,1,2,0] ; X64-AVX1-NEXT: ## xmm1 = mem[0,1,2,0]
; X64-AVX1-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08] ; X64-AVX1-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08]
; X64-AVX1-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3] ; X64-AVX1-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3]
; X64-AVX1-NEXT: retq ## encoding: [0xc3] ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
; ;
; X64-AVX512-LABEL: pinsrd_from_shufflevector_i32: ; X64-AVX512-LABEL: pinsrd_from_shufflevector_i32:
; X64-AVX512: ## %bb.0: ## %entry ; X64-AVX512: ## %bb.0: ## %entry
; X64-AVX512-NEXT: vpermilps $36, (%rdi), %xmm1 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x04,0x0f,0x24] ; X64-AVX512-NEXT: vmovaps (%rdi), %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf8,0x28,0x0f]
; X64-AVX512-NEXT: ## xmm1 = mem[0,1,2,0] ; X64-AVX512-NEXT: vbroadcastss %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x18,0xc9]
; X64-AVX512-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08] ; X64-AVX512-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08]
; X64-AVX512-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3] ; X64-AVX512-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3]
; X64-AVX512-NEXT: retq ## encoding: [0xc3] ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
entry: entry:
%0 = load <4 x i32>, <4 x i32>* %pb, align 16 %0 = load <4 x i32>, <4 x i32>* %pb, align 16
%vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4> %vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
ret <4 x i32> %vecinit6 ret <4 x i32> %vecinit6
} }
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; AVX1-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3] ; AVX1-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3]
; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
; ;
; AVX512-LABEL: i32_shuf_X00A: ; AVX512-LABEL: i32_shuf_X00A:
; AVX512: ## %bb.0: ; AVX512: ## %bb.0:
; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe8,0x57,0xd2] ; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2 ## encoding: [0xc5,0xe8,0x57,0xd2]
; AVX512-NEXT: vblendps $1, %xmm0, %xmm2, %xmm0 ## encoding: [0xc4,0xe3,0x69,0x0c,0xc0,0x01] ; AVX512-NEXT: vblendps $1, %xmm0, %xmm2, %xmm0 ## encoding: [0xc4,0xe3,0x69,0x0c,0xc0,0x01]
; AVX512-NEXT: ## xmm0 = xmm0[0],xmm2[1,2,3] ; AVX512-NEXT: ## xmm0 = xmm0[0],xmm2[1,2,3]
; AVX512-NEXT: vpermilps $36, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x04,0xc9,0x24] ; AVX512-NEXT: vbroadcastss %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x18,0xc9]
; AVX512-NEXT: ## xmm1 = xmm1[0,1,2,0]
; AVX512-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08] ; AVX512-NEXT: vblendps $8, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x0c,0xc1,0x08]
; AVX512-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3] ; AVX512-NEXT: ## xmm0 = xmm0[0,1,2],xmm1[3]
; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%vecext = extractelement <4 x i32> %x, i32 0 %vecext = extractelement <4 x i32> %x, i32 0
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
%vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1 %vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
%vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4> %vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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; AVX1-LABEL: insertps_8: ; AVX1-LABEL: insertps_8:
; AVX1: ## %bb.0: ; AVX1: ## %bb.0:
; AVX1-NEXT: vinsertps $28, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x1c] ; AVX1-NEXT: vinsertps $28, %xmm1, %xmm0, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x1c]
; AVX1-NEXT: ## xmm0 = xmm0[0],xmm1[0],zero,zero ; AVX1-NEXT: ## xmm0 = xmm0[0],xmm1[0],zero,zero
; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
; ;
; AVX512-LABEL: insertps_8: ; AVX512-LABEL: insertps_8:
; AVX512: ## %bb.0: ; AVX512: ## %bb.0:
; AVX512-NEXT: vinsertps $28, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x1c] ; AVX512-NEXT: vpunpckldq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x62,0xc1]
; AVX512-NEXT: ## xmm0 = xmm0[0],xmm1[0],zero,zero ; AVX512-NEXT: ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512-NEXT: vmovq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x7e,0xc0] ; AVX512-NEXT: vmovq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x7e,0xc0]
; AVX512-NEXT: ## xmm0 = xmm0[0],zero ; AVX512-NEXT: ## xmm0 = xmm0[0],zero
; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3] ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
%vecext = extractelement <4 x float> %A, i32 0 %vecext = extractelement <4 x float> %A, i32 0
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0 %vecinit = insertelement <4 x float> undef, float %vecext, i32 0
%vecext1 = extractelement <4 x float> %B, i32 0 %vecext1 = extractelement <4 x float> %B, i32 0
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1 %vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2 %vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2
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llvm/test/CodeGen/X86/test-shrink-bug.ll

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; CHECK-X64-LABEL: fail: ; CHECK-X64-LABEL: fail:
; CHECK-X64: # %bb.0: ; CHECK-X64: # %bb.0:
; CHECK-X64-NEXT: pushq %rax ; CHECK-X64-NEXT: pushq %rax
; CHECK-X64-NEXT: .cfi_def_cfa_offset 16 ; CHECK-X64-NEXT: .cfi_def_cfa_offset 16
; CHECK-X64-NEXT: testl $263, %edi # imm = 0x107 ; CHECK-X64-NEXT: testl $263, %edi # imm = 0x107
; CHECK-X64-NEXT: je .LBB1_3 ; CHECK-X64-NEXT: je .LBB1_3
; CHECK-X64-NEXT: # %bb.1: ; CHECK-X64-NEXT: # %bb.1:
; CHECK-X64-NEXT: pcmpeqb {{.*}}(%rip), %xmm0 ; CHECK-X64-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
; CHECK-X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; CHECK-X64-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8]
; CHECK-X64-NEXT: pextrw $1, %xmm0, %eax ; CHECK-X64-NEXT: pextrw $4, %xmm0, %eax
; CHECK-X64-NEXT: testb $1, %al ; CHECK-X64-NEXT: testb $1, %al
; CHECK-X64-NEXT: jne .LBB1_3 ; CHECK-X64-NEXT: jne .LBB1_3
; CHECK-X64-NEXT: # %bb.2: # %no ; CHECK-X64-NEXT: # %bb.2: # %no
; CHECK-X64-NEXT: callq bar ; CHECK-X64-NEXT: callq bar
; CHECK-X64-NEXT: .LBB1_3: # %yes ; CHECK-X64-NEXT: .LBB1_3: # %yes
; CHECK-X64-NEXT: popq %rax ; CHECK-X64-NEXT: popq %rax
; CHECK-X64-NEXT: .cfi_def_cfa_offset 8 ; CHECK-X64-NEXT: .cfi_def_cfa_offset 8
; CHECK-X64-NEXT: retq ; CHECK-X64-NEXT: retq
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llvm/test/CodeGen/X86/trunc-subvector.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
; SSE2-LABEL: test5: ; SSE2-LABEL: test5:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,2,2]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: test5: ; AVX2-LABEL: test5:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm1 = [17179869187,17179869187,17179869187,17179869187]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7]
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [6,6,6,6]
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: test5: ; AVX512-LABEL: test5:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpmovsxdq %ymm0, %zmm0 ; AVX512-NEXT: vpmovsxdq %ymm0, %zmm0
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
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; SSE2-LABEL: test10: ; SSE2-LABEL: test10:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,2,2] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,2,2]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; AVX2-LABEL: test10: ; AVX2-LABEL: test10:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm1 = [17179869187,17179869187,17179869187,17179869187]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7]
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [6,6,6,6]
; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: test10: ; AVX512-LABEL: test10:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero ; AVX512-NEXT: vpmovzxdq {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
Show All 12 Lines

llvm/test/CodeGen/X86/udiv_fix.ll

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Lines; X86-NEXT: retl
%tmp = call i16 @llvm.udiv.fix.i16(i16 %x, i16 %y, i32 16) %tmp = call i16 @llvm.udiv.fix.i16(i16 %x, i16 %y, i32 16)
ret i16 %tmp ret i16 %tmp
} }
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; X64-LABEL: vec: ; X64-LABEL: vec:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pxor %xmm2, %xmm2 ; X64-NEXT: pxor %xmm2, %xmm2
; X64-NEXT: movdqa %xmm1, %xmm4 ; X64-NEXT: movdqa %xmm1, %xmm3
; X64-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm2[2],xmm3[3],xmm2[3]
; X64-NEXT: movq %xmm3, %rcx
; X64-NEXT: movdqa %xmm0, %xmm4
; X64-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm2[2],xmm4[3],xmm2[3] ; X64-NEXT: punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm2[2],xmm4[3],xmm2[3]
; X64-NEXT: movq %xmm4, %rcx ; X64-NEXT: psllq $31, %xmm4
; X64-NEXT: movdqa %xmm0, %xmm5 ; X64-NEXT: movq %xmm4, %rax
; X64-NEXT: punpckhdq {{.*#+}} xmm5 = xmm5[2],xmm2[2],xmm5[3],xmm2[3]
; X64-NEXT: psllq $31, %xmm5
; X64-NEXT: movq %xmm5, %rax
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx ; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm3 ; X64-NEXT: movq %rax, %xmm3
; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,0,1] ; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm4[2,3,0,1]
; X64-NEXT: movq %xmm4, %rcx
; X64-NEXT: pshufd {{.*#+}} xmm4 = xmm5[2,3,0,1]
; X64-NEXT: movq %xmm4, %rax ; X64-NEXT: movq %xmm4, %rax
; X64-NEXT: movdqa %xmm1, %xmm4
; X64-NEXT: psrldq {{.*#+}} xmm4 = xmm4[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X64-NEXT: movq %xmm4, %rcx
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx ; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm4 ; X64-NEXT: movq %rax, %xmm4
; X64-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] ; X64-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; X64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; X64-NEXT: movq %xmm1, %rcx
; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X64-NEXT: movq %xmm2, %rcx
; X64-NEXT: psllq $31, %xmm0 ; X64-NEXT: psllq $31, %xmm0
; X64-NEXT: movq %xmm0, %rax ; X64-NEXT: movq %xmm0, %rax
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx ; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm2 ; X64-NEXT: movq %rax, %xmm2
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
; X64-NEXT: movq %xmm1, %rcx
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; X64-NEXT: movq %xmm0, %rax ; X64-NEXT: movq %xmm0, %rax
; X64-NEXT: psrlq $32, %xmm1
; X64-NEXT: movq %xmm1, %rcx
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divq %rcx ; X64-NEXT: divq %rcx
; X64-NEXT: movq %rax, %xmm0 ; X64-NEXT: movq %rax, %xmm0
; X64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0] ; X64-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2] ; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2]
; X64-NEXT: movaps %xmm2, %xmm0 ; X64-NEXT: movaps %xmm2, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
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llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
; One all-ones divisor in even divisor ; One all-ones divisor in even divisor
define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_allones_eq: ; CHECK-SSE2-LABEL: test_urem_even_allones_eq:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: psrld $31, %xmm2
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: psrld $31, %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_even_allones_eq: ; CHECK-SSE41-LABEL: test_urem_even_allones_eq:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines; CHECK-AVX512VL-NEXT: retq
ret <4 x i32> %ret ret <4 x i32> %ret
} }
define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_allones_ne: ; CHECK-SSE2-LABEL: test_urem_even_allones_ne:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: psrld $31, %xmm2
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: psrld $31, %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0 ; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_even_allones_ne: ; CHECK-SSE41-LABEL: test_urem_even_allones_ne:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
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; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,0] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_poweroftwo: ; CHECK-SSE41-LABEL: test_urem_odd_poweroftwo:
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; One power-of-two divisor in even divisor ; One power-of-two divisor in even divisor
define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_poweroftwo: ; CHECK-SSE2-LABEL: test_urem_even_poweroftwo:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_even_poweroftwo: ; CHECK-SSE41-LABEL: test_urem_even_poweroftwo:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
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; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1 ; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] ; CHECK-SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,2454267027,268435456,1374389535] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,2454267027,268435456,1374389535]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm3, %xmm2
; CHECK-SSE41-NEXT: psrld $5, %xmm2 ; CHECK-SSE41-NEXT: psrld $5, %xmm2
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm3
; CHECK-SSE41-NEXT: psrld $2, %xmm3 ; CHECK-SSE41-NEXT: psrld $2, %xmm3
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm1[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3
; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] ; CHECK-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,2454267027,268435456,1374389535] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,2454267027,268435456,1374389535]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm2 ; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm3
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm3 ; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm1[0,1,2,3],xmm3[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_urem_odd_even_poweroftwo: ; CHECK-AVX2-LABEL: test_urem_odd_even_poweroftwo:
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; One one divisor in even divisor ; One one divisor in even divisor
define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_one: ; CHECK-SSE2-LABEL: test_urem_even_one:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
; CHECK-SSE2-NEXT: movl $-1840700269, %eax # imm = 0x92492493 ; CHECK-SSE2-NEXT: movl $-1840700269, %eax # imm = 0x92492493
; CHECK-SSE2-NEXT: movd %eax, %xmm2 ; CHECK-SSE2-NEXT: movd %eax, %xmm3
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: psrld $2, %xmm1 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_even_one: ; CHECK-SSE41-LABEL: test_urem_even_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
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; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm0[3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: psrld $5, %xmm1 ; CHECK-SSE2-NEXT: psrld $5, %xmm1
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3 ; CHECK-SSE2-NEXT: movaps %xmm0, %xmm3
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[3,3] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm3 = xmm2[0],xmm3[1]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,14,1,100] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,14,1,100]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0],xmm2[3,0] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0,2] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_even_one: ; CHECK-SSE41-LABEL: test_urem_odd_even_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
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; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,0] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm2[0],xmm1[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_INT_MIN: ; CHECK-SSE41-LABEL: test_urem_odd_INT_MIN:
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; One INT_MIN divisor in even divisor ; One INT_MIN divisor in even divisor
define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind { define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: test_urem_even_INT_MIN: ; CHECK-SSE2-LABEL: test_urem_even_INT_MIN:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm1[0],xmm2[1]
; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2 ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm3 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pmuludq {{.*}}(%rip), %xmm1
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_even_INT_MIN: ; CHECK-SSE41-LABEL: test_urem_even_INT_MIN:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
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; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1 ; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] ; CHECK-SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,2454267027,2,1374389535] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,2454267027,2,1374389535]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm3, %xmm2
; CHECK-SSE41-NEXT: psrld $5, %xmm2 ; CHECK-SSE41-NEXT: psrld $5, %xmm2
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm3
; CHECK-SSE41-NEXT: psrld $2, %xmm3 ; CHECK-SSE41-NEXT: psrld $2, %xmm3
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm1[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3
; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_INT_MIN: ; CHECK-AVX1-LABEL: test_urem_odd_even_INT_MIN:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] ; CHECK-AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,2454267027,2,1374389535] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,2454267027,2,1374389535]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm2 ; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm3
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm3 ; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm1[0,1,2,3],xmm3[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_urem_odd_even_INT_MIN: ; CHECK-AVX2-LABEL: test_urem_odd_even_INT_MIN:
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; CHECK-SSE2-NEXT: psrld $2, %xmm1 ; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3 ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrld $31, %xmm3 ; CHECK-SSE2-NEXT: psrld $31, %xmm3
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [5,4294967295,16,5] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [5,4294967295,16,5]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm5 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm5
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,2,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm2[2,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_allones_and_poweroftwo: ; CHECK-SSE41-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,3435973837] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,3435973837]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm3, %xmm2
; CHECK-SSE41-NEXT: psrld $2, %xmm2 ; CHECK-SSE41-NEXT: psrld $2, %xmm2
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm3
; CHECK-SSE41-NEXT: psrld $31, %xmm3 ; CHECK-SSE41-NEXT: psrld $31, %xmm3
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,3435973837] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,3435973837]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm2, %xmm3
; CHECK-AVX1-NEXT: vpsrld $31, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm2
; CHECK-AVX1-NEXT: vpsrld $31, %xmm1, %xmm3
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_urem_odd_allones_and_poweroftwo: ; CHECK-AVX2-LABEL: test_urem_odd_allones_and_poweroftwo:
Show All 34 Lines
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,2147483649,268435456,2454267027] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,2147483649,268435456,2454267027]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,2] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm3 ; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm3
; CHECK-SSE2-NEXT: psrld $31, %xmm3 ; CHECK-SSE2-NEXT: psrld $31, %xmm3
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm2[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm2[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [14,4294967295,16,14] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [14,4294967295,16,14]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm5 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm5
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,2,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[2,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_even_allones_and_poweroftwo: ; CHECK-SSE41-LABEL: test_urem_even_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE41-NEXT: psrld $1, %xmm1 ; CHECK-SSE41-NEXT: psrld $1, %xmm1
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,2147483649,268435456,2454267027] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,2147483649,268435456,2454267027]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm4 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE41-NEXT: pmuludq %xmm3, %xmm1 ; CHECK-SSE41-NEXT: pmuludq %xmm3, %xmm1
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm4[2,3],xmm1[4,5],xmm4[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm1[0,1],xmm4[2,3],xmm1[4,5],xmm4[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm4, %xmm2
; CHECK-SSE41-NEXT: psrld $2, %xmm2 ; CHECK-SSE41-NEXT: psrld $2, %xmm2
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm3 ; CHECK-SSE41-NEXT: psrld $31, %xmm4
; CHECK-SSE41-NEXT: psrld $31, %xmm3 ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm4[2,3],xmm2[4,5],xmm4[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [2454267027,2147483649,268435456,2454267027] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [2454267027,2147483649,268435456,2454267027]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm4, %xmm2, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm4, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm3, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm2, %xmm3
; CHECK-AVX1-NEXT: vpsrld $31, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm2
; CHECK-AVX1-NEXT: vpsrld $31, %xmm1, %xmm3
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_urem_even_allones_and_poweroftwo: ; CHECK-AVX2-LABEL: test_urem_even_allones_and_poweroftwo:
Show All 39 Lines
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3 ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrld $2, %xmm3 ; CHECK-SSE2-NEXT: psrld $2, %xmm3
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,3],xmm2[2,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3]
; CHECK-SSE2-NEXT: psrld $5, %xmm2 ; CHECK-SSE2-NEXT: psrld $5, %xmm2
; CHECK-SSE2-NEXT: psrld $31, %xmm1 ; CHECK-SSE2-NEXT: psrld $31, %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [5,4294967295,16,100] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [5,4294967295,16,100]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_even_allones_and_poweroftwo: ; CHECK-SSE41-LABEL: test_urem_odd_even_allones_and_poweroftwo:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,1374389535] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,1374389535]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm3, %xmm2
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm3 ; CHECK-SSE41-NEXT: psrld $5, %xmm2
; CHECK-SSE41-NEXT: movdqa %xmm3, %xmm4
; CHECK-SSE41-NEXT: psrld $31, %xmm4
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: psrld $2, %xmm3 ; CHECK-SSE41-NEXT: psrld $2, %xmm3
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm1[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: psrld $5, %xmm1 ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7]
; CHECK-SSE41-NEXT: psrld $31, %xmm2
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3
; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_allones_and_poweroftwo: ; CHECK-AVX1-LABEL: test_urem_odd_even_allones_and_poweroftwo:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,1374389535] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,1374389535]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm2 ; CHECK-AVX1-NEXT: vpsrld $5, %xmm2, %xmm3
; CHECK-AVX1-NEXT: vpsrld $31, %xmm1, %xmm3 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm2, %xmm4
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm4[0,1,2,3],xmm3[4,5,6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm3 ; CHECK-AVX1-NEXT: vpsrld $2, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_urem_odd_even_allones_and_poweroftwo: ; CHECK-AVX2-LABEL: test_urem_odd_even_allones_and_poweroftwo:
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; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,2147483649,0,2454267027] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,2147483649,0,2454267027]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,2] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: psrld $31, %xmm1 ; CHECK-SSE2-NEXT: psrld $31, %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [14,4294967295,1,14] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [14,4294967295,1,14]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm4 ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0],xmm2[3,0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0,2]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
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; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3 ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm3
; CHECK-SSE2-NEXT: psrld $31, %xmm3 ; CHECK-SSE2-NEXT: psrld $31, %xmm3
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,4294967295,1,100] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,4294967295,1,100]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm4 ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0],xmm2[3,0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0,2]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
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; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[3,0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm2[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm2[3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,16,1,5] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,16,1,5]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_poweroftwo_and_one: ; CHECK-SSE41-LABEL: test_urem_odd_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,268435456,0,3435973837] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,268435456,0,3435973837]
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; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
; CHECK-SSE2-NEXT: psrld $1, %xmm1 ; CHECK-SSE2-NEXT: psrld $1, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,268435456,0,2454267027] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2454267027,268435456,0,2454267027]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm4
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,3,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm0[1,2] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2,3,1]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: psrld $2, %xmm1 ; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: movaps %xmm0, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [14,16,1,14] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [14,16,1,14]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_even_poweroftwo_and_one: ; CHECK-SSE41-LABEL: test_urem_even_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: psrld $2, %xmm1 ; CHECK-SSE2-NEXT: psrld $5, %xmm1
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm4 ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm1[3,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0],xmm1[3,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [5,16,1,100]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm4[0,2] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [5,16,1,100] ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm4
; CHECK-SSE2-NEXT: pmuludq %xmm4, %xmm1 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,2,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: psrld $5, %xmm2 ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[1,1],xmm2[3,3] ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_even_poweroftwo_and_one: ; CHECK-SSE41-LABEL: test_urem_odd_even_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,268435456,0,1374389535] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,268435456,0,1374389535]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2
; CHECK-SSE41-NEXT: psrld $5, %xmm2 ; CHECK-SSE41-NEXT: psrld $5, %xmm2
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1,2,3],xmm2[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: psrld $2, %xmm1 ; CHECK-SSE41-NEXT: psrld $2, %xmm1
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
; CHECK-SSE41-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_odd_even_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,268435456,0,1374389535] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,268435456,0,1374389535]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm2 ; CHECK-AVX1-NEXT: vpsrld $5, %xmm1, %xmm3
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1,2,3],xmm2[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
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; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1 ; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
; CHECK-SSE2-NEXT: psrld $2, %xmm1 ; CHECK-SSE2-NEXT: psrld $2, %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,3],xmm2[2,1] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [5,4294967295,16,1] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [5,4294967295,16,1]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm2 ; CHECK-SSE2-NEXT: psrld $31, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE2-NEXT: psrld $31, %xmm0 ; CHECK-SSE2-NEXT: psrld $31, %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: test_urem_odd_allones_and_poweroftwo_and_one: ; CHECK-SSE41-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,0] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,0]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1 ; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm3, %xmm2
; CHECK-SSE41-NEXT: psrld $2, %xmm2 ; CHECK-SSE41-NEXT: psrld $2, %xmm2
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: psrld $31, %xmm1 ; CHECK-SSE41-NEXT: psrld $31, %xmm3
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm0[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5],xmm0[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3
; CHECK-SSE41-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,0] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [3435973837,2147483649,268435456,0]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm2, %xmm3
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpsrld $31, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpsrld $31, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm0[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
Show All 34 Lines
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2454267027,2147483649,268435456,0] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2454267027,2147483649,268435456,0]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm3 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm3
; CHECK-SSE2-NEXT: psrld $1, %xmm3 ; CHECK-SSE2-NEXT: psrld $1, %xmm3
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm4 ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,3]
; CHECK-SSE2-NEXT: movss {{.*#+}} xmm4 = xmm3[0],xmm4[1,2,3] ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4 ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[1,3,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm1, %xmm2
; CHECK-SSE2-NEXT: psrld $2, %xmm2 ; CHECK-SSE2-NEXT: psrld $2, %xmm2
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm1[2,1] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3]
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [14,4294967295,16,1] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [14,4294967295,16,1]
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-SSE2-NEXT: psrld $31, %xmm1 ; CHECK-SSE2-NEXT: psrld $31, %xmm1
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
Show All 10 Lines
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE41-NEXT: psrld $1, %xmm2 ; CHECK-SSE41-NEXT: psrld $1, %xmm2
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3,4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3,4,5,6,7]
; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: movdqa %xmm3, %xmm2
; CHECK-SSE41-NEXT: psrld $2, %xmm2 ; CHECK-SSE41-NEXT: psrld $2, %xmm2
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-SSE41-NEXT: psrld $31, %xmm1 ; CHECK-SSE41-NEXT: psrld $31, %xmm3
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm2[0,1],xmm3[2,3],xmm2[4,5],xmm3[6,7]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm0[6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5],xmm0[6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm3
; CHECK-SSE41-NEXT: psubd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm3, %xmm0
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1 ; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-SSE41-NEXT: psrld $31, %xmm0 ; CHECK-SSE41-NEXT: psrld $31, %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo_and_one: ; CHECK-AVX1-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2454267027,2147483649,268435456,0] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2454267027,2147483649,268435456,0]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm3 ; CHECK-AVX1-NEXT: vpsrld $1, %xmm0, %xmm3
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,3,4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,3,4,5,6,7]
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm3, %xmm1 ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm2, %xmm3
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpsrld $31, %xmm2, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm2
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpsrld $31, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm0[6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
Show All 34 Lines

llvm/test/CodeGen/X86/urem-seteq-vec-nonzero.ll

Show First 20 Lines • Show All 274 Lines • ▼ Show 20 Lines
} }
define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind { define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind {
; CHECK-SSE2-LABEL: t32_tautological: ; CHECK-SSE2-LABEL: t32_tautological:
; CHECK-SSE2: # %bb.0: ; CHECK-SSE2: # %bb.0:
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531] ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531]
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2 ; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3 ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3] ; CHECK-SSE2-NEXT: psrld $1, %xmm3
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,1,2,2] ; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
; CHECK-SSE2-NEXT: psrld $1, %xmm2 ; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,1,2,3]
; CHECK-SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3] ; CHECK-SSE2-NEXT: movapd %xmm2, %xmm3
; CHECK-SSE2-NEXT: movsd {{.*#+}} xmm1 = xmm0[0],xmm1[1] ; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,2,3]
; CHECK-SSE2-NEXT: movapd %xmm1, %xmm3
; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; CHECK-SSE2-NEXT: pmuludq %xmm2, %xmm1
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] ; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1]
; CHECK-SSE2-NEXT: psubd %xmm3, %xmm0 ; CHECK-SSE2-NEXT: psubd %xmm3, %xmm0
; CHECK-SSE2-NEXT: pcmpeqd {{.*}}(%rip), %xmm0 ; CHECK-SSE2-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
; CHECK-SSE2-NEXT: retq ; CHECK-SSE2-NEXT: retq
; ;
; CHECK-SSE41-LABEL: t32_tautological: ; CHECK-SSE41-LABEL: t32_tautological:
; CHECK-SSE41: # %bb.0: ; CHECK-SSE41: # %bb.0:
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531] ; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531]
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: movdqa %xmm0, %xmm2
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm2
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7] ; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2 ; CHECK-SSE41-NEXT: pmuludq %xmm1, %xmm3
; CHECK-SSE41-NEXT: psrld $1, %xmm2 ; CHECK-SSE41-NEXT: psrld $1, %xmm3
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,5],xmm2[6,7] ; CHECK-SSE41-NEXT: punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2 ; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0 ; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
; CHECK-SSE41-NEXT: pcmpeqd {{.*}}(%rip), %xmm0 ; CHECK-SSE41-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
; CHECK-SSE41-NEXT: retq ; CHECK-SSE41-NEXT: retq
; ;
; CHECK-AVX1-LABEL: t32_tautological: ; CHECK-AVX1-LABEL: t32_tautological:
; CHECK-AVX1: # %bb.0: ; CHECK-AVX1: # %bb.0:
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531] ; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531]
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX1-NEXT: vpsrld $1, %xmm1, %xmm2 ; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7] ; CHECK-AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7] ; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0 ; CHECK-AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
; CHECK-AVX1-NEXT: retq ; CHECK-AVX1-NEXT: retq
; ;
; CHECK-AVX2-LABEL: t32_tautological: ; CHECK-AVX2-LABEL: t32_tautological:
; CHECK-AVX2: # %bb.0: ; CHECK-AVX2: # %bb.0:
; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531] ; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,0,2147483648,2863311531]
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] ; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3] ; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
; CHECK-AVX2-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3] ; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3]
; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1 ; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0 ; CHECK-AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
; CHECK-AVX2-NEXT: retq ; CHECK-AVX2-NEXT: retq
; ;
; CHECK-AVX512VL-LABEL: t32_tautological: ; CHECK-AVX512VL-LABEL: t32_tautological:
Show All 12 Lines

llvm/test/CodeGen/X86/vec-libcalls.ll

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-NEXT: subq $40, %rsp ; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3] ; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0] ; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovapd (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3] ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilps $231, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vpermilps $231, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,1,2,3] ; CHECK-NEXT: # xmm0 = mem[3,1,2,3]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; CHECK-NEXT: addq $40, %rsp ; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = call <4 x float> @llvm.sin.v4f32(<4 x float> %x) %r = call <4 x float> @llvm.sin.v4f32(<4 x float> %x)
ret <4 x float> %r ret <4 x float> %r
} }
define <5 x float> @sin_v5f32(<5 x float> %x) nounwind { define <5 x float> @sin_v5f32(<5 x float> %x) nounwind {
; CHECK-LABEL: sin_v5f32: ; CHECK-LABEL: sin_v5f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $88, %rsp ; CHECK-NEXT: subq $88, %rsp
; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill ; CHECK-NEXT: vmovups %ymm0, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3] ; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0] ; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovapd (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3] ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilps $231, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vpermilps $231, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,1,2,3] ; CHECK-NEXT: # xmm0 = mem[3,1,2,3]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; CHECK-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill ; CHECK-NEXT: vmovups %ymm0, (%rsp) # 32-byte Spill
; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload ; CHECK-NEXT: vmovups {{[-0-9]+}}(%r{{[sb]}}p), %ymm0 # 32-byte Reload
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
Show All 27 Lines
; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; CHECK-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vmovshdup {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,1,3,3] ; CHECK-NEXT: # xmm0 = mem[1,1,3,3]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vpermilpd $1, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[1,0] ; CHECK-NEXT: # xmm0 = mem[1,0]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovapd (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3] ; CHECK-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; CHECK-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: vpermilps $231, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: vpermilps $231, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = mem[3,1,2,3] ; CHECK-NEXT: # xmm0 = mem[3,1,2,3]
; CHECK-NEXT: callq sinf ; CHECK-NEXT: callq sinf
; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload ; CHECK-NEXT: vmovaps (%rsp), %xmm1 # 16-byte Reload
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; CHECK-NEXT: vinsertf128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload ; CHECK-NEXT: vinsertf128 $1, {{[-0-9]+}}(%r{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
; CHECK-NEXT: addq $88, %rsp ; CHECK-NEXT: addq $88, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
▲ Show 20 Lines • Show All 220 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll

Show First 20 Lines • Show All 860 Lines • ▼ Show 20 Lines
; AVX512DQVL-NEXT: ret{{[l|q]}} ; AVX512DQVL-NEXT: ret{{[l|q]}}
%result = call <4 x double> @llvm.experimental.constrained.uitofp.v4f64.v4i64(<4 x i64> %x, %result = call <4 x double> @llvm.experimental.constrained.uitofp.v4f64.v4i64(<4 x i64> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x double> %result ret <4 x double> %result
} }
define <4 x float> @sitofp_v4i64_v4f32(<4 x i64> %x) #0 { define <4 x float> @sitofp_v4i64_v4f32(<4 x i64> %x) #0 {
; AVX-32-LABEL: sitofp_v4i64_v4f32: ; AVX1-32-LABEL: sitofp_v4i64_v4f32:
; AVX-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX1-32-NEXT: pushl %ebp
; AVX-32-NEXT: .cfi_def_cfa_offset 8 ; AVX1-32-NEXT: .cfi_def_cfa_offset 8
; AVX-32-NEXT: .cfi_offset %ebp, -8 ; AVX1-32-NEXT: .cfi_offset %ebp, -8
; AVX-32-NEXT: movl %esp, %ebp ; AVX1-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: .cfi_def_cfa_register %ebp ; AVX1-32-NEXT: .cfi_def_cfa_register %ebp
; AVX-32-NEXT: andl $-8, %esp ; AVX1-32-NEXT: andl $-8, %esp
; AVX-32-NEXT: subl $48, %esp ; AVX1-32-NEXT: subl $48, %esp
; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] ; AVX1-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-32-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1] ; AVX1-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fstps (%esp) ; AVX1-32-NEXT: fstps (%esp)
; AVX-32-NEXT: wait ; AVX1-32-NEXT: wait
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX1-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX1-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX1-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; AVX1-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-32-NEXT: movl %ebp, %esp ; AVX1-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-32-NEXT: popl %ebp ; AVX1-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX-32-NEXT: .cfi_def_cfa %esp, 4 ; AVX1-32-NEXT: movl %ebp, %esp
; AVX-32-NEXT: vzeroupper ; AVX1-32-NEXT: popl %ebp
; AVX-32-NEXT: retl ; AVX1-32-NEXT: .cfi_def_cfa %esp, 4
; AVX1-32-NEXT: vzeroupper
; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: sitofp_v4i64_v4f32: ; AVX1-64-LABEL: sitofp_v4i64_v4f32:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX1-64-NEXT: vmovq %xmm0, %rax ; AVX1-64-NEXT: vmovq %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX1-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-64-NEXT: vmovq %xmm0, %rax ; AVX1-64-NEXT: vmovq %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX1-64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-64-NEXT: vzeroupper ; AVX1-64-NEXT: vzeroupper
; AVX1-64-NEXT: retq ; AVX1-64-NEXT: retq
; ;
; AVX2-32-LABEL: sitofp_v4i64_v4f32:
; AVX2-32: # %bb.0:
; AVX2-32-NEXT: pushl %ebp
; AVX2-32-NEXT: .cfi_def_cfa_offset 8
; AVX2-32-NEXT: .cfi_offset %ebp, -8
; AVX2-32-NEXT: movl %esp, %ebp
; AVX2-32-NEXT: .cfi_def_cfa_register %ebp
; AVX2-32-NEXT: andl $-8, %esp
; AVX2-32-NEXT: subl $48, %esp
; AVX2-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX2-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX2-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX2-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fstps (%esp)
; AVX2-32-NEXT: wait
; AVX2-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX2-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX2-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX2-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX2-32-NEXT: movl %ebp, %esp
; AVX2-32-NEXT: popl %ebp
; AVX2-32-NEXT: .cfi_def_cfa %esp, 4
; AVX2-32-NEXT: vzeroupper
; AVX2-32-NEXT: retl
;
; AVX2-64-LABEL: sitofp_v4i64_v4f32: ; AVX2-64-LABEL: sitofp_v4i64_v4f32:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX2-64-NEXT: vmovq %xmm0, %rax ; AVX2-64-NEXT: vmovq %xmm0, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX2-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX2-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX2-64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-64-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-64-NEXT: vmovq %xmm0, %rax ; AVX2-64-NEXT: vmovq %xmm0, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX2-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX2-64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX2-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-64-NEXT: vzeroupper ; AVX2-64-NEXT: vzeroupper
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512F-32-LABEL: sitofp_v4i64_v4f32:
; AVX512F-32: # %bb.0:
; AVX512F-32-NEXT: pushl %ebp
; AVX512F-32-NEXT: .cfi_def_cfa_offset 8
; AVX512F-32-NEXT: .cfi_offset %ebp, -8
; AVX512F-32-NEXT: movl %esp, %ebp
; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp
; AVX512F-32-NEXT: andl $-8, %esp
; AVX512F-32-NEXT: subl $48, %esp
; AVX512F-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX512F-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512F-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX512F-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fstps (%esp)
; AVX512F-32-NEXT: wait
; AVX512F-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512F-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512F-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512F-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512F-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX512F-32-NEXT: movl %ebp, %esp
; AVX512F-32-NEXT: popl %ebp
; AVX512F-32-NEXT: .cfi_def_cfa %esp, 4
; AVX512F-32-NEXT: vzeroupper
; AVX512F-32-NEXT: retl
;
; AVX512F-64-LABEL: sitofp_v4i64_v4f32: ; AVX512F-64-LABEL: sitofp_v4i64_v4f32:
; AVX512F-64: # %bb.0: ; AVX512F-64: # %bb.0:
; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX512F-64-NEXT: vmovq %xmm0, %rax ; AVX512F-64-NEXT: vmovq %xmm0, %rax
; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512F-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512F-64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512F-64-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-64-NEXT: vmovq %xmm0, %rax ; AVX512F-64-NEXT: vmovq %xmm0, %rax
; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512F-64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX512F-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-64-NEXT: vzeroupper ; AVX512F-64-NEXT: vzeroupper
; AVX512F-64-NEXT: retq ; AVX512F-64-NEXT: retq
; ;
; AVX512VL-32-LABEL: sitofp_v4i64_v4f32:
; AVX512VL-32: # %bb.0:
; AVX512VL-32-NEXT: pushl %ebp
; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8
; AVX512VL-32-NEXT: .cfi_offset %ebp, -8
; AVX512VL-32-NEXT: movl %esp, %ebp
; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp
; AVX512VL-32-NEXT: andl $-8, %esp
; AVX512VL-32-NEXT: subl $48, %esp
; AVX512VL-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX512VL-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX512VL-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,3,0,1]
; AVX512VL-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fstps (%esp)
; AVX512VL-32-NEXT: wait
; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512VL-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512VL-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; AVX512VL-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX512VL-32-NEXT: movl %ebp, %esp
; AVX512VL-32-NEXT: popl %ebp
; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4
; AVX512VL-32-NEXT: vzeroupper
; AVX512VL-32-NEXT: retl
;
; AVX512VL-64-LABEL: sitofp_v4i64_v4f32: ; AVX512VL-64-LABEL: sitofp_v4i64_v4f32:
; AVX512VL-64: # %bb.0: ; AVX512VL-64: # %bb.0:
; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX512VL-64-NEXT: vmovq %xmm0, %rax ; AVX512VL-64-NEXT: vmovq %xmm0, %rax
; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512VL-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512VL-64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512VL-64-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512VL-64-NEXT: vmovq %xmm0, %rax ; AVX512VL-64-NEXT: vmovq %xmm0, %rax
; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX512VL-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-64-NEXT: vzeroupper ; AVX512VL-64-NEXT: vzeroupper
Show All 14 Lines
; AVX512DQVL-NEXT: ret{{[l|q]}} ; AVX512DQVL-NEXT: ret{{[l|q]}}
%result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i64(<4 x i64> %x, %result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i64(<4 x i64> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x float> %result ret <4 x float> %result
} }
define <4 x float> @uitofp_v4i64_v4f32(<4 x i64> %x) #0 { define <4 x float> @uitofp_v4i64_v4f32(<4 x i64> %x) #0 {
; AVX-32-LABEL: uitofp_v4i64_v4f32: ; AVX1-32-LABEL: uitofp_v4i64_v4f32:
; AVX-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX-32-NEXT: pushl %ebp ; AVX1-32-NEXT: pushl %ebp
; AVX-32-NEXT: .cfi_def_cfa_offset 8 ; AVX1-32-NEXT: .cfi_def_cfa_offset 8
; AVX-32-NEXT: .cfi_offset %ebp, -8 ; AVX1-32-NEXT: .cfi_offset %ebp, -8
; AVX-32-NEXT: movl %esp, %ebp ; AVX1-32-NEXT: movl %esp, %ebp
; AVX-32-NEXT: .cfi_def_cfa_register %ebp ; AVX1-32-NEXT: .cfi_def_cfa_register %ebp
; AVX-32-NEXT: andl $-8, %esp ; AVX1-32-NEXT: andl $-8, %esp
; AVX-32-NEXT: subl $48, %esp ; AVX1-32-NEXT: subl $48, %esp
; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] ; AVX1-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-32-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1] ; AVX1-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
; AVX-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp) ; AVX1-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm0, %eax ; AVX1-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX1-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX1-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps (%esp) ; AVX1-32-NEXT: fstps (%esp)
; AVX-32-NEXT: wait ; AVX1-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax ; AVX1-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX1-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX1-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX1-32-NEXT: wait
; AVX-32-NEXT: vextractps $1, %xmm1, %eax ; AVX1-32-NEXT: vextractps $1, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX1-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX1-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX1-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm1, %eax ; AVX1-32-NEXT: vextractps $3, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX1-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX1-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX1-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX1-32-NEXT: wait
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX1-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX1-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX1-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; AVX1-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-32-NEXT: movl %ebp, %esp ; AVX1-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-32-NEXT: popl %ebp ; AVX1-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX-32-NEXT: .cfi_def_cfa %esp, 4 ; AVX1-32-NEXT: movl %ebp, %esp
; AVX-32-NEXT: vzeroupper ; AVX1-32-NEXT: popl %ebp
; AVX-32-NEXT: retl ; AVX1-32-NEXT: .cfi_def_cfa %esp, 4
; AVX1-32-NEXT: vzeroupper
; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: uitofp_v4i64_v4f32: ; AVX1-64-LABEL: uitofp_v4i64_v4f32:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpsrlq $1, %xmm0, %xmm1 ; AVX1-64-NEXT: vpsrlq $1, %xmm0, %xmm1
; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-64-NEXT: vpsrlq $1, %xmm2, %xmm3 ; AVX1-64-NEXT: vpsrlq $1, %xmm2, %xmm3
; AVX1-64-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 ; AVX1-64-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-64-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3 ; AVX1-64-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3
; AVX1-64-NEXT: vorpd %ymm3, %ymm1, %ymm1 ; AVX1-64-NEXT: vorpd %ymm3, %ymm1, %ymm1
; AVX1-64-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1 ; AVX1-64-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; AVX1-64-NEXT: vmovq %xmm1, %rax ; AVX1-64-NEXT: vmovq %xmm1, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; AVX1-64-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX1-64-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-64-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-64-NEXT: vmovq %xmm1, %rax ; AVX1-64-NEXT: vmovq %xmm1, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; AVX1-64-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; AVX1-64-NEXT: vaddps %xmm1, %xmm1, %xmm3 ; AVX1-64-NEXT: vaddps %xmm1, %xmm1, %xmm3
; AVX1-64-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 ; AVX1-64-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-64-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0 ; AVX1-64-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0
; AVX1-64-NEXT: vzeroupper ; AVX1-64-NEXT: vzeroupper
; AVX1-64-NEXT: retq ; AVX1-64-NEXT: retq
; ;
; AVX2-32-LABEL: uitofp_v4i64_v4f32:
; AVX2-32: # %bb.0:
; AVX2-32-NEXT: pushl %ebp
; AVX2-32-NEXT: .cfi_def_cfa_offset 8
; AVX2-32-NEXT: .cfi_offset %ebp, -8
; AVX2-32-NEXT: movl %esp, %ebp
; AVX2-32-NEXT: .cfi_def_cfa_register %ebp
; AVX2-32-NEXT: andl $-8, %esp
; AVX2-32-NEXT: subl $48, %esp
; AVX2-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX2-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX2-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
; AVX2-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp)
; AVX2-32-NEXT: vextractps $1, %xmm0, %eax
; AVX2-32-NEXT: shrl $31, %eax
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX2-32-NEXT: fstps (%esp)
; AVX2-32-NEXT: wait
; AVX2-32-NEXT: vextractps $3, %xmm0, %eax
; AVX2-32-NEXT: shrl $31, %eax
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX2-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX2-32-NEXT: wait
; AVX2-32-NEXT: vextractps $1, %xmm1, %eax
; AVX2-32-NEXT: shrl $31, %eax
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX2-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX2-32-NEXT: wait
; AVX2-32-NEXT: vextractps $3, %xmm1, %eax
; AVX2-32-NEXT: shrl $31, %eax
; AVX2-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX2-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX2-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX2-32-NEXT: wait
; AVX2-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX2-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX2-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX2-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX2-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX2-32-NEXT: movl %ebp, %esp
; AVX2-32-NEXT: popl %ebp
; AVX2-32-NEXT: .cfi_def_cfa %esp, 4
; AVX2-32-NEXT: vzeroupper
; AVX2-32-NEXT: retl
;
; AVX2-64-LABEL: uitofp_v4i64_v4f32: ; AVX2-64-LABEL: uitofp_v4i64_v4f32:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1] ; AVX2-64-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1]
; AVX2-64-NEXT: vpand %ymm1, %ymm0, %ymm1 ; AVX2-64-NEXT: vpand %ymm1, %ymm0, %ymm1
; AVX2-64-NEXT: vpsrlq $1, %ymm0, %ymm2 ; AVX2-64-NEXT: vpsrlq $1, %ymm0, %ymm2
; AVX2-64-NEXT: vpor %ymm1, %ymm2, %ymm1 ; AVX2-64-NEXT: vpor %ymm1, %ymm2, %ymm1
; AVX2-64-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1 ; AVX2-64-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX2-64-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-64-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX2-64-NEXT: vmovq %xmm1, %rax ; AVX2-64-NEXT: vmovq %xmm1, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; AVX2-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX2-64-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-64-NEXT: vextracti128 $1, %ymm1, %xmm1 ; AVX2-64-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX2-64-NEXT: vmovq %xmm1, %rax ; AVX2-64-NEXT: vmovq %xmm1, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; AVX2-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX2-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX2-64-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-64-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1 ; AVX2-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1
; AVX2-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0] ; AVX2-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX2-64-NEXT: vaddps %xmm1, %xmm1, %xmm2 ; AVX2-64-NEXT: vaddps %xmm1, %xmm1, %xmm2
; AVX2-64-NEXT: vextracti128 $1, %ymm0, %xmm3 ; AVX2-64-NEXT: vextracti128 $1, %ymm0, %xmm3
; AVX2-64-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX2-64-NEXT: vpackssdw %xmm3, %xmm0, %xmm0
; AVX2-64-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0 ; AVX2-64-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX2-64-NEXT: vzeroupper ; AVX2-64-NEXT: vzeroupper
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512F-32-LABEL: uitofp_v4i64_v4f32:
; AVX512F-32: # %bb.0:
; AVX512F-32-NEXT: pushl %ebp
; AVX512F-32-NEXT: .cfi_def_cfa_offset 8
; AVX512F-32-NEXT: .cfi_offset %ebp, -8
; AVX512F-32-NEXT: movl %esp, %ebp
; AVX512F-32-NEXT: .cfi_def_cfa_register %ebp
; AVX512F-32-NEXT: andl $-8, %esp
; AVX512F-32-NEXT: subl $48, %esp
; AVX512F-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX512F-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512F-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
; AVX512F-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: vextractps $1, %xmm0, %eax
; AVX512F-32-NEXT: shrl $31, %eax
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512F-32-NEXT: fstps (%esp)
; AVX512F-32-NEXT: wait
; AVX512F-32-NEXT: vextractps $3, %xmm0, %eax
; AVX512F-32-NEXT: shrl $31, %eax
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512F-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: wait
; AVX512F-32-NEXT: vextractps $1, %xmm1, %eax
; AVX512F-32-NEXT: shrl $31, %eax
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512F-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: wait
; AVX512F-32-NEXT: vextractps $3, %xmm1, %eax
; AVX512F-32-NEXT: shrl $31, %eax
; AVX512F-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512F-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F-32-NEXT: wait
; AVX512F-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512F-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512F-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512F-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512F-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512F-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX512F-32-NEXT: movl %ebp, %esp
; AVX512F-32-NEXT: popl %ebp
; AVX512F-32-NEXT: .cfi_def_cfa %esp, 4
; AVX512F-32-NEXT: vzeroupper
; AVX512F-32-NEXT: retl
;
; AVX512F-64-LABEL: uitofp_v4i64_v4f32: ; AVX512F-64-LABEL: uitofp_v4i64_v4f32:
; AVX512F-64: # %bb.0: ; AVX512F-64: # %bb.0:
; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1 ; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; AVX512F-64-NEXT: vmovq %xmm0, %rax ; AVX512F-64-NEXT: vmovq %xmm0, %rax
; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512F-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512F-64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512F-64-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-64-NEXT: vmovq %xmm0, %rax ; AVX512F-64-NEXT: vmovq %xmm0, %rax
; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512F-64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; AVX512F-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512F-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-64-NEXT: vzeroupper ; AVX512F-64-NEXT: vzeroupper
; AVX512F-64-NEXT: retq ; AVX512F-64-NEXT: retq
; ;
; AVX512VL-32-LABEL: uitofp_v4i64_v4f32:
; AVX512VL-32: # %bb.0:
; AVX512VL-32-NEXT: pushl %ebp
; AVX512VL-32-NEXT: .cfi_def_cfa_offset 8
; AVX512VL-32-NEXT: .cfi_offset %ebp, -8
; AVX512VL-32-NEXT: movl %esp, %ebp
; AVX512VL-32-NEXT: .cfi_def_cfa_register %ebp
; AVX512VL-32-NEXT: andl $-8, %esp
; AVX512VL-32-NEXT: subl $48, %esp
; AVX512VL-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX512VL-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX512VL-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
; AVX512VL-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: vextractps $1, %xmm0, %eax
; AVX512VL-32-NEXT: shrl $31, %eax
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512VL-32-NEXT: fstps (%esp)
; AVX512VL-32-NEXT: wait
; AVX512VL-32-NEXT: vextractps $3, %xmm0, %eax
; AVX512VL-32-NEXT: shrl $31, %eax
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512VL-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: wait
; AVX512VL-32-NEXT: vextractps $1, %xmm1, %eax
; AVX512VL-32-NEXT: shrl $31, %eax
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512VL-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: wait
; AVX512VL-32-NEXT: vextractps $3, %xmm1, %eax
; AVX512VL-32-NEXT: shrl $31, %eax
; AVX512VL-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; AVX512VL-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512VL-32-NEXT: wait
; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512VL-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512VL-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; AVX512VL-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; AVX512VL-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX512VL-32-NEXT: movl %ebp, %esp
; AVX512VL-32-NEXT: popl %ebp
; AVX512VL-32-NEXT: .cfi_def_cfa %esp, 4
; AVX512VL-32-NEXT: vzeroupper
; AVX512VL-32-NEXT: retl
;
; AVX512VL-64-LABEL: uitofp_v4i64_v4f32: ; AVX512VL-64-LABEL: uitofp_v4i64_v4f32:
; AVX512VL-64: # %bb.0: ; AVX512VL-64: # %bb.0:
; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1 ; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; AVX512VL-64-NEXT: vmovq %xmm0, %rax ; AVX512VL-64-NEXT: vmovq %xmm0, %rax
; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512VL-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512VL-64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512VL-64-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512VL-64-NEXT: vmovq %xmm0, %rax ; AVX512VL-64-NEXT: vmovq %xmm0, %rax
; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; AVX512VL-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512VL-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-64-NEXT: vzeroupper ; AVX512VL-64-NEXT: vzeroupper
Show All 22 Lines

llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll

Show First 20 Lines • Show All 427 Lines • ▼ Show 20 Lines
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fstps (%esp) ; NODQ-32-NEXT: fstps (%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; NODQ-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; NODQ-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; NODQ-32-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; NODQ-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
; NODQ-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NODQ-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NODQ-32-NEXT: movl %ebp, %esp ; NODQ-32-NEXT: movl %ebp, %esp
; NODQ-32-NEXT: popl %ebp ; NODQ-32-NEXT: popl %ebp
; NODQ-32-NEXT: .cfi_def_cfa %esp, 4 ; NODQ-32-NEXT: .cfi_def_cfa %esp, 4
; NODQ-32-NEXT: retl ; NODQ-32-NEXT: retl
; ;
; NODQ-64-LABEL: sitofp_v8i64_v8f32: ; NODQ-64-LABEL: sitofp_v8i64_v8f32:
; NODQ-64: # %bb.0: ; NODQ-64: # %bb.0:
; NODQ-64-NEXT: vextracti32x4 $2, %zmm0, %xmm1 ; NODQ-64-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; NODQ-64-NEXT: vpextrq $1, %xmm1, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; NODQ-64-NEXT: vmovq %xmm1, %rax ; NODQ-64-NEXT: vmovq %xmm1, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] ; NODQ-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; NODQ-64-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NODQ-64-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NODQ-64-NEXT: vmovq %xmm2, %rax ; NODQ-64-NEXT: vmovq %xmm2, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3] ; NODQ-64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; NODQ-64-NEXT: vpextrq $1, %xmm2, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm2
; NODQ-64-NEXT: vmovq %xmm0, %rax ; NODQ-64-NEXT: vmovq %xmm0, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; NODQ-64-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; NODQ-64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NODQ-64-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-64-NEXT: vmovq %xmm0, %rax ; NODQ-64-NEXT: vmovq %xmm0, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; NODQ-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm0 ; NODQ-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm0
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; NODQ-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; NODQ-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NODQ-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NODQ-64-NEXT: retq ; NODQ-64-NEXT: retq
; ;
; DQ-LABEL: sitofp_v8i64_v8f32: ; DQ-LABEL: sitofp_v8i64_v8f32:
; DQ: # %bb.0: ; DQ: # %bb.0:
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm1, %eax ; NODQ-32-NEXT: vextractps $3, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; NODQ-32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; NODQ-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; NODQ-32-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; NODQ-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
; NODQ-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NODQ-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NODQ-32-NEXT: movl %ebp, %esp ; NODQ-32-NEXT: movl %ebp, %esp
; NODQ-32-NEXT: popl %ebp ; NODQ-32-NEXT: popl %ebp
; NODQ-32-NEXT: .cfi_def_cfa %esp, 4 ; NODQ-32-NEXT: .cfi_def_cfa %esp, 4
; NODQ-32-NEXT: retl ; NODQ-32-NEXT: retl
; ;
; NODQ-64-LABEL: uitofp_v8i64_v8f32: ; NODQ-64-LABEL: uitofp_v8i64_v8f32:
; NODQ-64: # %bb.0: ; NODQ-64: # %bb.0:
; NODQ-64-NEXT: vextracti32x4 $2, %zmm0, %xmm1 ; NODQ-64-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; NODQ-64-NEXT: vpextrq $1, %xmm1, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm1, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; NODQ-64-NEXT: vmovq %xmm1, %rax ; NODQ-64-NEXT: vmovq %xmm1, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] ; NODQ-64-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; NODQ-64-NEXT: vextracti32x4 $3, %zmm0, %xmm2 ; NODQ-64-NEXT: vextracti32x4 $3, %zmm0, %xmm2
; NODQ-64-NEXT: vmovq %xmm2, %rax ; NODQ-64-NEXT: vmovq %xmm2, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm3, %xmm3
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm3[0],xmm1[3] ; NODQ-64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; NODQ-64-NEXT: vpextrq $1, %xmm2, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm2, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; NODQ-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm2
; NODQ-64-NEXT: vmovq %xmm0, %rax ; NODQ-64-NEXT: vmovq %xmm0, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; NODQ-64-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; NODQ-64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; NODQ-64-NEXT: vextracti128 $1, %ymm0, %xmm0
; NODQ-64-NEXT: vmovq %xmm0, %rax ; NODQ-64-NEXT: vmovq %xmm0, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm3
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; NODQ-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax ; NODQ-64-NEXT: vpextrq $1, %xmm0, %rax
; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm0 ; NODQ-64-NEXT: vcvtusi2ss %rax, %xmm4, %xmm0
; NODQ-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; NODQ-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; NODQ-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NODQ-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NODQ-64-NEXT: retq ; NODQ-64-NEXT: retq
; ;
; DQ-LABEL: uitofp_v8i64_v8f32: ; DQ-LABEL: uitofp_v8i64_v8f32:
; DQ: # %bb.0: ; DQ: # %bb.0:
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llvm/test/CodeGen/X86/vec_insert-2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64
define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind { define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
; X32-LABEL: t1: ; X32-LABEL: t1:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: t1: ; X64-LABEL: t1:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[2,0] ; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0] ; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; X64-NEXT: movaps %xmm1, %xmm0 ; X64-NEXT: movaps %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1 = insertelement <4 x float> %tmp, float %s, i32 3 %tmp1 = insertelement <4 x float> %tmp, float %s, i32 3
ret <4 x float> %tmp1 ret <4 x float> %tmp1
} }
define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind { define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind {
; X32-LABEL: t2: ; X32-LABEL: t2:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: t2: ; X64-LABEL: t2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movd %edi, %xmm1 ; X64-NEXT: movd %edi, %xmm1
; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 3 %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 3
ret <4 x i32> %tmp1 ret <4 x i32> %tmp1
} }
define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind { define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind {
; X32-LABEL: t3: ; X32-LABEL: t3:
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llvm/test/CodeGen/X86/vec_insert-3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,-sse4.1 | FileCheck %s --check-prefix=X64
define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind { define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind {
; X32-LABEL: t1: ; X32-LABEL: t1:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: movaps %xmm0, %xmm2 ; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0,2] ; X32-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,0]
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm2[2,0]
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: t1: ; X64-LABEL: t1:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, %xmm1 ; X64-NEXT: movq %rdi, %xmm1
; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1 %tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1
ret <2 x i64> %tmp1 ret <2 x i64> %tmp1
} }

llvm/test/CodeGen/X86/vec_insert-5.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X64
; There are no MMX operations in @t1 ; There are no MMX operations in @t1
define void @t1(i32 %a, x86_mmx* %P) nounwind { define void @t1(i32 %a, x86_mmx* %P) nounwind {
; X32-LABEL: t1: ; X32-LABEL: t1:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: shll $12, %ecx ; X32-NEXT: shll $12, %ecx
; X32-NEXT: movd %ecx, %xmm0 ; X32-NEXT: movd %ecx, %xmm0
; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1] ; X32-NEXT: psllq $32, %xmm0
; X32-NEXT: movq %xmm0, (%eax) ; X32-NEXT: movq %xmm0, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: t1: ; X64-LABEL: t1:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: shll $12, %edi ; X64-NEXT: shll $12, %edi
; X64-NEXT: movd %edi, %xmm0 ; X64-NEXT: movd %edi, %xmm0
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1] ; X64-NEXT: psllq $32, %xmm0
; X64-NEXT: movq %xmm0, (%rsi) ; X64-NEXT: movq %xmm0, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
%tmp12 = shl i32 %a, 12 %tmp12 = shl i32 %a, 12
%tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1 %tmp21 = insertelement <2 x i32> undef, i32 %tmp12, i32 1
%tmp22 = insertelement <2 x i32> %tmp21, i32 0, i32 0 %tmp22 = insertelement <2 x i32> %tmp21, i32 0, i32 0
%tmp23 = bitcast <2 x i32> %tmp22 to x86_mmx %tmp23 = bitcast <2 x i32> %tmp22 to x86_mmx
store x86_mmx %tmp23, x86_mmx* %P store x86_mmx %tmp23, x86_mmx* %P
ret void ret void
} }
define <4 x float> @t2(<4 x float>* %P) nounwind { define <4 x float> @t2(<4 x float>* %P) nounwind {
; X32-LABEL: t2: ; X32-LABEL: t2:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: xorps %xmm1, %xmm1 ; X32-NEXT: xorps %xmm1, %xmm1
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[0,0] ; X32-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],mem[0]
; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: t2: ; X64-LABEL: t2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorps %xmm0, %xmm0 ; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[0,0] ; X64-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],mem[0]
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1 = load <4 x float>, <4 x float>* %P %tmp1 = load <4 x float>, <4 x float>* %P
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 > %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
ret <4 x float> %tmp2 ret <4 x float> %tmp2
} }
define <4 x float> @t3(<4 x float>* %P) nounwind { define <4 x float> @t3(<4 x float>* %P) nounwind {
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llvm/test/CodeGen/X86/vec_int_to_fp.ll

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%cvt = sitofp <4 x i32> %a to <4 x double> %cvt = sitofp <4 x i32> %a to <4 x double>
%shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <4 x double> %cvt, <4 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf ret <2 x double> %shuf
} }
define <2 x double> @sitofp_2i16_to_2f64(<8 x i16> %a) { define <2 x double> @sitofp_2i16_to_2f64(<8 x i16> %a) {
; SSE2-LABEL: sitofp_2i16_to_2f64: ; SSE2-LABEL: sitofp_2i16_to_2f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-NEXT: psrad $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: sitofp_2i16_to_2f64: ; SSE41-LABEL: sitofp_2i16_to_2f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 ; SSE41-NEXT: pmovsxwd %xmm0, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: sitofp_2i16_to_2f64: ; AVX-LABEL: sitofp_2i16_to_2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmovsxwd %xmm0, %xmm0 ; AVX-NEXT: vpmovsxwd %xmm0, %xmm0
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i16> %shuf to <2 x double> %cvt = sitofp <2 x i16> %shuf to <2 x double>
ret <2 x double> %cvt ret <2 x double> %cvt
} }
define <2 x double> @sitofp_8i16_to_2f64(<8 x i16> %a) { define <2 x double> @sitofp_8i16_to_2f64(<8 x i16> %a) {
; SSE2-LABEL: sitofp_8i16_to_2f64: ; SSE2-LABEL: sitofp_8i16_to_2f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-NEXT: psrad $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: sitofp_8i16_to_2f64: ; SSE41-LABEL: sitofp_8i16_to_2f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 ; SSE41-NEXT: pmovsxwd %xmm0, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
Show All 16 Lines; AVX512-NEXT: retq
%shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf ret <2 x double> %shuf
} }
define <2 x double> @sitofp_2i8_to_2f64(<16 x i8> %a) { define <2 x double> @sitofp_2i8_to_2f64(<16 x i8> %a) {
; SSE2-LABEL: sitofp_2i8_to_2f64: ; SSE2-LABEL: sitofp_2i8_to_2f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-NEXT: psrad $24, %xmm0 ; SSE2-NEXT: psrad $24, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: sitofp_2i8_to_2f64: ; SSE41-LABEL: sitofp_2i8_to_2f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 ; SSE41-NEXT: pmovsxbd %xmm0, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: sitofp_2i8_to_2f64: ; AVX-LABEL: sitofp_2i8_to_2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmovsxbd %xmm0, %xmm0 ; AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i8> %shuf to <2 x double> %cvt = sitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt ret <2 x double> %cvt
} }
define <2 x double> @sitofp_16i8_to_2f64(<16 x i8> %a) { define <2 x double> @sitofp_16i8_to_2f64(<16 x i8> %a) {
; SSE2-LABEL: sitofp_16i8_to_2f64: ; SSE2-LABEL: sitofp_16i8_to_2f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-NEXT: psrad $24, %xmm0 ; SSE2-NEXT: psrad $24, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: sitofp_16i8_to_2f64: ; SSE41-LABEL: sitofp_16i8_to_2f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pmovsxbd %xmm0, %xmm0 ; SSE41-NEXT: pmovsxbd %xmm0, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
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; ;
; SSE41-LABEL: sitofp_4i64_to_4f32: ; SSE41-LABEL: sitofp_4i64_to_4f32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pextrq $1, %xmm0, %rax ; SSE41-NEXT: pextrq $1, %xmm0, %rax
; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: cvtsi2ss %rax, %xmm2
; SSE41-NEXT: movq %xmm0, %rax ; SSE41-NEXT: movq %xmm0, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE41-NEXT: movq %xmm1, %rax ; SSE41-NEXT: movq %xmm1, %rax
; SSE41-NEXT: xorps %xmm2, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: cvtsi2ss %rax, %xmm2
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE41-NEXT: pextrq $1, %xmm1, %rax ; SSE41-NEXT: pextrq $1, %xmm1, %rax
; SSE41-NEXT: xorps %xmm1, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: cvtsi2ss %rax, %xmm1 ; SSE41-NEXT: cvtsi2ss %rax, %xmm1
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: sitofp_4i64_to_4f32: ; AVX1-LABEL: sitofp_4i64_to_4f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: sitofp_4i64_to_4f32: ; AVX2-LABEL: sitofp_4i64_to_4f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: sitofp_4i64_to_4f32: ; AVX512F-LABEL: sitofp_4i64_to_4f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: sitofp_4i64_to_4f32: ; AVX512VL-LABEL: sitofp_4i64_to_4f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
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; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm1 ; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm1
; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm2 ; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm2
; AVX1-NEXT: vorps %ymm1, %ymm2, %ymm1 ; AVX1-NEXT: vorps %ymm1, %ymm2, %ymm1
; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1 ; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0 ; AVX1-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_4i64_to_4f32_undef: ; AVX2-LABEL: uitofp_4i64_to_4f32_undef:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm2 ; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm2
; AVX2-NEXT: vpor %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpor %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX2-NEXT: vaddps %xmm1, %xmm1, %xmm2 ; AVX2-NEXT: vaddps %xmm1, %xmm1, %xmm2
; AVX2-NEXT: vpackssdw %xmm0, %xmm0, %xmm0 ; AVX2-NEXT: vpackssdw %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0 ; AVX2-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
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; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm5 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm5
; SSE41-NEXT: pextrq $1, %xmm5, %rax ; SSE41-NEXT: pextrq $1, %xmm5, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: movq %xmm5, %rax ; SSE41-NEXT: movq %xmm5, %rax
; SSE41-NEXT: xorps %xmm3, %xmm3 ; SSE41-NEXT: xorps %xmm3, %xmm3
; SSE41-NEXT: cvtsi2ss %rax, %xmm3 ; SSE41-NEXT: cvtsi2ss %rax, %xmm3
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
; SSE41-NEXT: pand %xmm2, %xmm4 ; SSE41-NEXT: pand %xmm2, %xmm4
; SSE41-NEXT: movdqa %xmm2, %xmm5 ; SSE41-NEXT: movdqa %xmm2, %xmm5
; SSE41-NEXT: psrlq $1, %xmm5 ; SSE41-NEXT: psrlq $1, %xmm5
; SSE41-NEXT: por %xmm4, %xmm5 ; SSE41-NEXT: por %xmm4, %xmm5
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
; SSE41-NEXT: movaps %xmm2, %xmm0 ; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2
; SSE41-NEXT: movq %xmm2, %rax ; SSE41-NEXT: movq %xmm2, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0],xmm3[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; SSE41-NEXT: pextrq $1, %xmm2, %rax ; SSE41-NEXT: pextrq $1, %xmm2, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0] ; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0]
; SSE41-NEXT: movaps %xmm3, %xmm2 ; SSE41-NEXT: movaps %xmm3, %xmm2
; SSE41-NEXT: addps %xmm3, %xmm2 ; SSE41-NEXT: addps %xmm3, %xmm2
; SSE41-NEXT: movaps %xmm1, %xmm0 ; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3 ; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
; SSE41-NEXT: movaps %xmm3, %xmm0 ; SSE41-NEXT: movaps %xmm3, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: uitofp_4i64_to_4f32: ; AVX1-LABEL: uitofp_4i64_to_4f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm1 ; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3 ; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3
; AVX1-NEXT: vorpd %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vorpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1 ; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm3 ; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm3
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0 ; AVX1-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_4i64_to_4f32: ; AVX2-LABEL: uitofp_4i64_to_4f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm2 ; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm2
; AVX2-NEXT: vpor %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpor %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm4, %xmm1
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1,2],xmm1[0]
; AVX2-NEXT: vaddps %xmm1, %xmm1, %xmm2 ; AVX2-NEXT: vaddps %xmm1, %xmm1, %xmm2
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
; AVX2-NEXT: vpackssdw %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vpackssdw %xmm3, %xmm0, %xmm0
; AVX2-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0 ; AVX2-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_4i64_to_4f32: ; AVX512F-LABEL: uitofp_4i64_to_4f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: uitofp_4i64_to_4f32: ; AVX512VL-LABEL: uitofp_4i64_to_4f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: vzeroupper
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} }
define <2 x double> @sitofp_load_2i8_to_2f64(<2 x i8> *%a) { define <2 x double> @sitofp_load_2i8_to_2f64(<2 x i8> *%a) {
; SSE2-LABEL: sitofp_load_2i8_to_2f64: ; SSE2-LABEL: sitofp_load_2i8_to_2f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movzwl (%rdi), %eax ; SSE2-NEXT: movzwl (%rdi), %eax
; SSE2-NEXT: movd %eax, %xmm0 ; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; SSE2-NEXT: psrad $24, %xmm0 ; SSE2-NEXT: psrad $24, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: sitofp_load_2i8_to_2f64: ; SSE41-LABEL: sitofp_load_2i8_to_2f64:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movzwl (%rdi), %eax ; SSE41-NEXT: movzwl (%rdi), %eax
; SSE41-NEXT: movd %eax, %xmm0 ; SSE41-NEXT: movd %eax, %xmm0
▲ Show 20 Lines • Show All 829 Lines • ▼ Show 20 Lines
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa (%rdi), %xmm0 ; SSE41-NEXT: movdqa (%rdi), %xmm0
; SSE41-NEXT: movdqa 16(%rdi), %xmm1 ; SSE41-NEXT: movdqa 16(%rdi), %xmm1
; SSE41-NEXT: pextrq $1, %xmm0, %rax ; SSE41-NEXT: pextrq $1, %xmm0, %rax
; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: cvtsi2ss %rax, %xmm2
; SSE41-NEXT: movq %xmm0, %rax ; SSE41-NEXT: movq %xmm0, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE41-NEXT: movq %xmm1, %rax ; SSE41-NEXT: movq %xmm1, %rax
; SSE41-NEXT: xorps %xmm2, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: cvtsi2ss %rax, %xmm2
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE41-NEXT: pextrq $1, %xmm1, %rax ; SSE41-NEXT: pextrq $1, %xmm1, %rax
; SSE41-NEXT: xorps %xmm1, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: cvtsi2ss %rax, %xmm1 ; SSE41-NEXT: cvtsi2ss %rax, %xmm1
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; VEX-LABEL: sitofp_load_4i64_to_4f32: ; VEX-LABEL: sitofp_load_4i64_to_4f32:
; VEX: # %bb.0: ; VEX: # %bb.0:
; VEX-NEXT: vmovdqa (%rdi), %xmm0 ; VEX-NEXT: vmovdqa (%rdi), %xmm0
; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 ; VEX-NEXT: vmovdqa 16(%rdi), %xmm1
; VEX-NEXT: vpextrq $1, %xmm0, %rax ; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; VEX-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; VEX-NEXT: vmovq %xmm0, %rax ; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; VEX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; VEX-NEXT: vmovq %xmm1, %rax ; VEX-NEXT: vmovq %xmm1, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; VEX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; VEX-NEXT: vpextrq $1, %xmm1, %rax ; VEX-NEXT: vpextrq $1, %xmm1, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; VEX-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; VEX-NEXT: retq ; VEX-NEXT: retq
; ;
; AVX512F-LABEL: sitofp_load_4i64_to_4f32: ; AVX512F-LABEL: sitofp_load_4i64_to_4f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 ; AVX512F-NEXT: vmovdqa (%rdi), %xmm0
; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX512F-NEXT: vmovq %xmm1, %rax ; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax ; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: sitofp_load_4i64_to_4f32: ; AVX512VL-LABEL: sitofp_load_4i64_to_4f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 ; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX512VL-NEXT: vmovq %xmm1, %rax ; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqa 16(%rdi), %xmm1 ; SSE41-NEXT: movdqa 16(%rdi), %xmm1
; SSE41-NEXT: movdqa 32(%rdi), %xmm2 ; SSE41-NEXT: movdqa 32(%rdi), %xmm2
; SSE41-NEXT: movdqa 48(%rdi), %xmm3 ; SSE41-NEXT: movdqa 48(%rdi), %xmm3
; SSE41-NEXT: pextrq $1, %xmm0, %rax ; SSE41-NEXT: pextrq $1, %xmm0, %rax
; SSE41-NEXT: cvtsi2ss %rax, %xmm4 ; SSE41-NEXT: cvtsi2ss %rax, %xmm4
; SSE41-NEXT: movq %xmm0, %rax ; SSE41-NEXT: movq %xmm0, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; SSE41-NEXT: movq %xmm1, %rax ; SSE41-NEXT: movq %xmm1, %rax
; SSE41-NEXT: xorps %xmm4, %xmm4 ; SSE41-NEXT: xorps %xmm4, %xmm4
; SSE41-NEXT: cvtsi2ss %rax, %xmm4 ; SSE41-NEXT: cvtsi2ss %rax, %xmm4
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm4[0],xmm0[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm4[0]
; SSE41-NEXT: pextrq $1, %xmm1, %rax ; SSE41-NEXT: pextrq $1, %xmm1, %rax
; SSE41-NEXT: xorps %xmm1, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: cvtsi2ss %rax, %xmm1 ; SSE41-NEXT: cvtsi2ss %rax, %xmm1
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; SSE41-NEXT: pextrq $1, %xmm2, %rax ; SSE41-NEXT: pextrq $1, %xmm2, %rax
; SSE41-NEXT: xorps %xmm4, %xmm4 ; SSE41-NEXT: xorps %xmm4, %xmm4
; SSE41-NEXT: cvtsi2ss %rax, %xmm4 ; SSE41-NEXT: cvtsi2ss %rax, %xmm4
; SSE41-NEXT: movq %xmm2, %rax ; SSE41-NEXT: movq %xmm2, %rax
; SSE41-NEXT: xorps %xmm1, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: cvtsi2ss %rax, %xmm1 ; SSE41-NEXT: cvtsi2ss %rax, %xmm1
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
; SSE41-NEXT: movq %xmm3, %rax ; SSE41-NEXT: movq %xmm3, %rax
; SSE41-NEXT: xorps %xmm2, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: cvtsi2ss %rax, %xmm2
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE41-NEXT: pextrq $1, %xmm3, %rax ; SSE41-NEXT: pextrq $1, %xmm3, %rax
; SSE41-NEXT: xorps %xmm2, %xmm2 ; SSE41-NEXT: xorps %xmm2, %xmm2
; SSE41-NEXT: cvtsi2ss %rax, %xmm2 ; SSE41-NEXT: cvtsi2ss %rax, %xmm2
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0] ; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; VEX-LABEL: sitofp_load_8i64_to_8f32: ; VEX-LABEL: sitofp_load_8i64_to_8f32:
; VEX: # %bb.0: ; VEX: # %bb.0:
; VEX-NEXT: vmovaps (%rdi), %xmm0 ; VEX-NEXT: vmovaps (%rdi), %xmm0
; VEX-NEXT: vmovdqa 16(%rdi), %xmm1 ; VEX-NEXT: vmovdqa 16(%rdi), %xmm1
; VEX-NEXT: vmovdqa 32(%rdi), %xmm2 ; VEX-NEXT: vmovdqa 32(%rdi), %xmm2
; VEX-NEXT: vmovdqa 48(%rdi), %xmm3 ; VEX-NEXT: vmovdqa 48(%rdi), %xmm3
; VEX-NEXT: vpextrq $1, %xmm2, %rax ; VEX-NEXT: vpextrq $1, %xmm2, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; VEX-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; VEX-NEXT: vmovq %xmm2, %rax ; VEX-NEXT: vmovq %xmm2, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2 ; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2
; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] ; VEX-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; VEX-NEXT: vmovq %xmm3, %rax ; VEX-NEXT: vmovq %xmm3, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; VEX-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; VEX-NEXT: vpextrq $1, %xmm3, %rax ; VEX-NEXT: vpextrq $1, %xmm3, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; VEX-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; VEX-NEXT: vpextrq $1, %xmm0, %rax ; VEX-NEXT: vpextrq $1, %xmm0, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VEX-NEXT: vmovq %xmm0, %rax ; VEX-NEXT: vmovq %xmm0, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 ; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] ; VEX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; VEX-NEXT: vmovq %xmm1, %rax ; VEX-NEXT: vmovq %xmm1, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] ; VEX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; VEX-NEXT: vpextrq $1, %xmm1, %rax ; VEX-NEXT: vpextrq $1, %xmm1, %rax
; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; VEX-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; VEX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; VEX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; VEX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; VEX-NEXT: retq ; VEX-NEXT: retq
; ;
; AVX512F-LABEL: sitofp_load_8i64_to_8f32: ; AVX512F-LABEL: sitofp_load_8i64_to_8f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm0 ; AVX512F-NEXT: vmovaps (%rdi), %xmm0
; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2 ; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2
; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3 ; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3
; AVX512F-NEXT: vpextrq $1, %xmm2, %rax ; AVX512F-NEXT: vpextrq $1, %xmm2, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; AVX512F-NEXT: vmovq %xmm2, %rax ; AVX512F-NEXT: vmovq %xmm2, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; AVX512F-NEXT: vmovq %xmm3, %rax ; AVX512F-NEXT: vmovq %xmm3, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; AVX512F-NEXT: vpextrq $1, %xmm3, %rax ; AVX512F-NEXT: vpextrq $1, %xmm3, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; AVX512F-NEXT: vmovq %xmm1, %rax ; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax ; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: sitofp_load_8i64_to_8f32: ; AVX512VL-LABEL: sitofp_load_8i64_to_8f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovaps (%rdi), %xmm0 ; AVX512VL-NEXT: vmovaps (%rdi), %xmm0
; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2 ; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2
; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3 ; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3
; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; AVX512VL-NEXT: vmovq %xmm2, %rax ; AVX512VL-NEXT: vmovq %xmm2, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; AVX512VL-NEXT: vmovq %xmm3, %rax ; AVX512VL-NEXT: vmovq %xmm3, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3]
; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; AVX512VL-NEXT: vmovq %xmm1, %rax ; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3]
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX512VL-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqa %xmm1, %xmm0 ; SSE41-NEXT: movdqa %xmm1, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm5 ; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm5
; SSE41-NEXT: pextrq $1, %xmm5, %rax ; SSE41-NEXT: pextrq $1, %xmm5, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: movq %xmm5, %rax ; SSE41-NEXT: movq %xmm5, %rax
; SSE41-NEXT: xorps %xmm3, %xmm3 ; SSE41-NEXT: xorps %xmm3, %xmm3
; SSE41-NEXT: cvtsi2ss %rax, %xmm3 ; SSE41-NEXT: cvtsi2ss %rax, %xmm3
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
; SSE41-NEXT: pand %xmm2, %xmm4 ; SSE41-NEXT: pand %xmm2, %xmm4
; SSE41-NEXT: movdqa %xmm2, %xmm5 ; SSE41-NEXT: movdqa %xmm2, %xmm5
; SSE41-NEXT: psrlq $1, %xmm5 ; SSE41-NEXT: psrlq $1, %xmm5
; SSE41-NEXT: por %xmm4, %xmm5 ; SSE41-NEXT: por %xmm4, %xmm5
; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3] ; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,3],xmm2[1,3]
; SSE41-NEXT: movaps %xmm2, %xmm0 ; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2
; SSE41-NEXT: movq %xmm2, %rax ; SSE41-NEXT: movq %xmm2, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0],xmm3[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; SSE41-NEXT: pextrq $1, %xmm2, %rax ; SSE41-NEXT: pextrq $1, %xmm2, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0] ; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0]
; SSE41-NEXT: movaps %xmm3, %xmm2 ; SSE41-NEXT: movaps %xmm3, %xmm2
; SSE41-NEXT: addps %xmm3, %xmm2 ; SSE41-NEXT: addps %xmm3, %xmm2
; SSE41-NEXT: movaps %xmm1, %xmm0 ; SSE41-NEXT: movaps %xmm1, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3 ; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
Show All 10 Lines
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm3, %ymm3
; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm4 ; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm4
; AVX1-NEXT: vorpd %ymm4, %ymm3, %ymm3 ; AVX1-NEXT: vorpd %ymm4, %ymm3, %ymm3
; AVX1-NEXT: vblendvpd %ymm0, %ymm3, %ymm0, %ymm0 ; AVX1-NEXT: vblendvpd %ymm0, %ymm3, %ymm0, %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm3 ; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm3
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vblendvps %xmm1, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vblendvps %xmm1, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_load_4i64_to_4f32: ; AVX2-LABEL: uitofp_load_4i64_to_4f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vmovdqa (%rdi), %ymm0 ; AVX2-NEXT: vmovdqa (%rdi), %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [1,1,1,1]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm1 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm1
; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm2 ; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm2
; AVX2-NEXT: vpor %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpor %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm1
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm1 ; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm1
; AVX2-NEXT: vmovdqa (%rdi), %xmm2 ; AVX2-NEXT: vmovdqa (%rdi), %xmm2
; AVX2-NEXT: vpackssdw 16(%rdi), %xmm2, %xmm2 ; AVX2-NEXT: vpackssdw 16(%rdi), %xmm2, %xmm2
; AVX2-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vblendvps %xmm2, %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vzeroupper ; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_load_4i64_to_4f32: ; AVX512F-LABEL: uitofp_load_4i64_to_4f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovdqa (%rdi), %xmm0 ; AVX512F-NEXT: vmovdqa (%rdi), %xmm0
; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX512F-NEXT: vmovq %xmm1, %rax ; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax ; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: uitofp_load_4i64_to_4f32: ; AVX512VL-LABEL: uitofp_load_4i64_to_4f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0 ; AVX512VL-NEXT: vmovdqa (%rdi), %xmm0
; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; AVX512VL-NEXT: vmovq %xmm1, %rax ; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm3, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
▲ Show 20 Lines • Show All 297 Lines • ▼ Show 20 Lines
; SSE41-NEXT: movdqa %xmm4, %xmm0 ; SSE41-NEXT: movdqa %xmm4, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm3
; SSE41-NEXT: pextrq $1, %xmm3, %rax ; SSE41-NEXT: pextrq $1, %xmm3, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: movq %xmm3, %rax ; SSE41-NEXT: movq %xmm3, %rax
; SSE41-NEXT: xorps %xmm3, %xmm3 ; SSE41-NEXT: xorps %xmm3, %xmm3
; SSE41-NEXT: cvtsi2ss %rax, %xmm3 ; SSE41-NEXT: cvtsi2ss %rax, %xmm3
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
; SSE41-NEXT: movdqa %xmm5, %xmm0 ; SSE41-NEXT: movdqa %xmm5, %xmm0
; SSE41-NEXT: pand %xmm7, %xmm0 ; SSE41-NEXT: pand %xmm7, %xmm0
; SSE41-NEXT: movdqa %xmm5, %xmm1 ; SSE41-NEXT: movdqa %xmm5, %xmm1
; SSE41-NEXT: psrlq $1, %xmm1 ; SSE41-NEXT: psrlq $1, %xmm1
; SSE41-NEXT: por %xmm0, %xmm1 ; SSE41-NEXT: por %xmm0, %xmm1
; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm5[1,3] ; SSE41-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,3],xmm5[1,3]
; SSE41-NEXT: movaps %xmm5, %xmm0 ; SSE41-NEXT: movaps %xmm5, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm5 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm5
; SSE41-NEXT: movq %xmm5, %rax ; SSE41-NEXT: movq %xmm5, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1],xmm0[0],xmm3[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm3 = xmm3[0],xmm0[0]
; SSE41-NEXT: pextrq $1, %xmm5, %rax ; SSE41-NEXT: pextrq $1, %xmm5, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0] ; SSE41-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm0[0]
; SSE41-NEXT: movaps %xmm3, %xmm1 ; SSE41-NEXT: movaps %xmm3, %xmm1
; SSE41-NEXT: addps %xmm3, %xmm1 ; SSE41-NEXT: addps %xmm3, %xmm1
; SSE41-NEXT: movaps %xmm4, %xmm0 ; SSE41-NEXT: movaps %xmm4, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm3 ; SSE41-NEXT: blendvps %xmm0, %xmm1, %xmm3
; SSE41-NEXT: movdqa %xmm6, %xmm0 ; SSE41-NEXT: movdqa %xmm6, %xmm0
; SSE41-NEXT: pand %xmm7, %xmm0 ; SSE41-NEXT: pand %xmm7, %xmm0
; SSE41-NEXT: movdqa %xmm6, %xmm1 ; SSE41-NEXT: movdqa %xmm6, %xmm1
; SSE41-NEXT: psrlq $1, %xmm1 ; SSE41-NEXT: psrlq $1, %xmm1
; SSE41-NEXT: por %xmm0, %xmm1 ; SSE41-NEXT: por %xmm0, %xmm1
; SSE41-NEXT: movdqa %xmm6, %xmm4 ; SSE41-NEXT: movdqa %xmm6, %xmm4
; SSE41-NEXT: movdqa %xmm6, %xmm0 ; SSE41-NEXT: movdqa %xmm6, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm4 ; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm4
; SSE41-NEXT: pextrq $1, %xmm4, %rax ; SSE41-NEXT: pextrq $1, %xmm4, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: movq %xmm4, %rax ; SSE41-NEXT: movq %xmm4, %rax
; SSE41-NEXT: xorps %xmm1, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: cvtsi2ss %rax, %xmm1 ; SSE41-NEXT: cvtsi2ss %rax, %xmm1
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE41-NEXT: pand %xmm2, %xmm7 ; SSE41-NEXT: pand %xmm2, %xmm7
; SSE41-NEXT: movdqa %xmm2, %xmm4 ; SSE41-NEXT: movdqa %xmm2, %xmm4
; SSE41-NEXT: psrlq $1, %xmm4 ; SSE41-NEXT: psrlq $1, %xmm4
; SSE41-NEXT: por %xmm7, %xmm4 ; SSE41-NEXT: por %xmm7, %xmm4
; SSE41-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm2[1,3] ; SSE41-NEXT: shufps {{.*#+}} xmm6 = xmm6[1,3],xmm2[1,3]
; SSE41-NEXT: movaps %xmm2, %xmm0 ; SSE41-NEXT: movaps %xmm2, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm2 ; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm2
; SSE41-NEXT: movq %xmm2, %rax ; SSE41-NEXT: movq %xmm2, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0],xmm1[3] ; SSE41-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE41-NEXT: pextrq $1, %xmm2, %rax ; SSE41-NEXT: pextrq $1, %xmm2, %rax
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: cvtsi2ss %rax, %xmm0 ; SSE41-NEXT: cvtsi2ss %rax, %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0] ; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
; SSE41-NEXT: movaps %xmm1, %xmm2 ; SSE41-NEXT: movaps %xmm1, %xmm2
; SSE41-NEXT: addps %xmm1, %xmm2 ; SSE41-NEXT: addps %xmm1, %xmm2
; SSE41-NEXT: movaps %xmm6, %xmm0 ; SSE41-NEXT: movaps %xmm6, %xmm0
; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1 ; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm1
Show All 14 Lines
; AVX1-NEXT: vpsrlq $1, %xmm4, %xmm0 ; AVX1-NEXT: vpsrlq $1, %xmm4, %xmm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm7, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm7, %ymm0
; AVX1-NEXT: vorpd %ymm5, %ymm0, %ymm0 ; AVX1-NEXT: vorpd %ymm5, %ymm0, %ymm0
; AVX1-NEXT: vblendvpd %ymm3, %ymm0, %ymm3, %ymm0 ; AVX1-NEXT: vblendvpd %ymm3, %ymm0, %ymm3, %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm3 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm3
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm5 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm5
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm5[0],xmm3[0],xmm5[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm3 = xmm5[0],xmm3[0],xmm5[1],xmm3[1]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm5 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm5
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm5[0],xmm3[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm5[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm0 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1,2],xmm0[0]
; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm3 ; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm3
; AVX1-NEXT: vpackssdw %xmm4, %xmm6, %xmm4 ; AVX1-NEXT: vpackssdw %xmm4, %xmm6, %xmm4
; AVX1-NEXT: vblendvps %xmm4, %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vblendvps %xmm4, %xmm3, %xmm0, %xmm0
; AVX1-NEXT: vandpd %ymm2, %ymm8, %ymm3 ; AVX1-NEXT: vandpd %ymm2, %ymm8, %ymm3
; AVX1-NEXT: vpsrlq $1, %xmm9, %xmm4 ; AVX1-NEXT: vpsrlq $1, %xmm9, %xmm4
; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm5 ; AVX1-NEXT: vpsrlq $1, %xmm1, %xmm5
; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm4, %ymm4 ; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm4, %ymm4
; AVX1-NEXT: vorpd %ymm3, %ymm4, %ymm3 ; AVX1-NEXT: vorpd %ymm3, %ymm4, %ymm3
; AVX1-NEXT: vblendvpd %ymm2, %ymm3, %ymm2, %ymm2 ; AVX1-NEXT: vblendvpd %ymm2, %ymm3, %ymm2, %ymm2
; AVX1-NEXT: vpextrq $1, %xmm2, %rax ; AVX1-NEXT: vpextrq $1, %xmm2, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm3 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm3
; AVX1-NEXT: vmovq %xmm2, %rax ; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
; AVX1-NEXT: vmovq %xmm2, %rax ; AVX1-NEXT: vmovq %xmm2, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX1-NEXT: vpextrq $1, %xmm2, %rax ; AVX1-NEXT: vpextrq $1, %xmm2, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm2 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm10, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1,2],xmm2[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1,2],xmm2[0]
; AVX1-NEXT: vaddps %xmm2, %xmm2, %xmm3 ; AVX1-NEXT: vaddps %xmm2, %xmm2, %xmm3
; AVX1-NEXT: vpackssdw %xmm1, %xmm9, %xmm1 ; AVX1-NEXT: vpackssdw %xmm1, %xmm9, %xmm1
; AVX1-NEXT: vblendvps %xmm1, %xmm3, %xmm2, %xmm1 ; AVX1-NEXT: vblendvps %xmm1, %xmm3, %xmm2, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: uitofp_load_8i64_to_8f32: ; AVX2-LABEL: uitofp_load_8i64_to_8f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vmovaps (%rdi), %ymm0 ; AVX2-NEXT: vmovaps (%rdi), %ymm0
; AVX2-NEXT: vmovdqa 32(%rdi), %ymm1 ; AVX2-NEXT: vmovdqa 32(%rdi), %ymm1
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1,1,1,1] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [1,1,1,1]
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm3 ; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm3
; AVX2-NEXT: vpsrlq $1, %ymm1, %ymm4 ; AVX2-NEXT: vpsrlq $1, %ymm1, %ymm4
; AVX2-NEXT: vpor %ymm3, %ymm4, %ymm3 ; AVX2-NEXT: vpor %ymm3, %ymm4, %ymm3
; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX2-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1 ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1
; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: vmovq %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX2-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX2-NEXT: vpextrq $1, %xmm1, %rax ; AVX2-NEXT: vpextrq $1, %xmm1, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; AVX2-NEXT: vaddps %xmm1, %xmm1, %xmm3 ; AVX2-NEXT: vaddps %xmm1, %xmm1, %xmm3
; AVX2-NEXT: vmovdqa (%rdi), %xmm4 ; AVX2-NEXT: vmovdqa (%rdi), %xmm4
; AVX2-NEXT: vmovdqa 32(%rdi), %xmm5 ; AVX2-NEXT: vmovdqa 32(%rdi), %xmm5
; AVX2-NEXT: vpackssdw 48(%rdi), %xmm5, %xmm5 ; AVX2-NEXT: vpackssdw 48(%rdi), %xmm5, %xmm5
; AVX2-NEXT: vblendvps %xmm5, %xmm3, %xmm1, %xmm1 ; AVX2-NEXT: vblendvps %xmm5, %xmm3, %xmm1, %xmm1
; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm2 ; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm2
; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm3 ; AVX2-NEXT: vpsrlq $1, %ymm0, %ymm3
; AVX2-NEXT: vpor %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpor %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vblendvpd %ymm0, %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm0, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm2 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm2
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax ; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; AVX2-NEXT: vpextrq $1, %xmm0, %rax ; AVX2-NEXT: vpextrq $1, %xmm0, %rax
; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm0 ; AVX2-NEXT: vcvtsi2ss %rax, %xmm6, %xmm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm2 ; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm2
; AVX2-NEXT: vpackssdw 16(%rdi), %xmm4, %xmm3 ; AVX2-NEXT: vpackssdw 16(%rdi), %xmm4, %xmm3
; AVX2-NEXT: vblendvps %xmm3, %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vblendvps %xmm3, %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_load_8i64_to_8f32: ; AVX512F-LABEL: uitofp_load_8i64_to_8f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovaps (%rdi), %xmm0 ; AVX512F-NEXT: vmovaps (%rdi), %xmm0
; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512F-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2 ; AVX512F-NEXT: vmovdqa 32(%rdi), %xmm2
; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3 ; AVX512F-NEXT: vmovdqa 48(%rdi), %xmm3
; AVX512F-NEXT: vpextrq $1, %xmm2, %rax ; AVX512F-NEXT: vpextrq $1, %xmm2, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4
; AVX512F-NEXT: vmovq %xmm2, %rax ; AVX512F-NEXT: vmovq %xmm2, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; AVX512F-NEXT: vmovq %xmm3, %rax ; AVX512F-NEXT: vmovq %xmm3, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm4[0]
; AVX512F-NEXT: vpextrq $1, %xmm3, %rax ; AVX512F-NEXT: vpextrq $1, %xmm3, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; AVX512F-NEXT: vmovq %xmm1, %rax ; AVX512F-NEXT: vmovq %xmm1, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX512F-NEXT: vpextrq $1, %xmm1, %rax ; AVX512F-NEXT: vpextrq $1, %xmm1, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512F-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: uitofp_load_8i64_to_8f32: ; AVX512VL-LABEL: uitofp_load_8i64_to_8f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovaps (%rdi), %xmm0 ; AVX512VL-NEXT: vmovaps (%rdi), %xmm0
; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1 ; AVX512VL-NEXT: vmovdqa 16(%rdi), %xmm1
; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2 ; AVX512VL-NEXT: vmovdqa 32(%rdi), %xmm2
; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3 ; AVX512VL-NEXT: vmovdqa 48(%rdi), %xmm3
; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm2, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm4, %xmm4
; AVX512VL-NEXT: vmovq %xmm2, %rax ; AVX512VL-NEXT: vmovq %xmm2, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
; AVX512VL-NEXT: vmovq %xmm3, %rax ; AVX512VL-NEXT: vmovq %xmm3, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm4
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm4[0],xmm2[3]
; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm3, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm3[0]
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; AVX512VL-NEXT: vmovq %xmm0, %rax ; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
; AVX512VL-NEXT: vmovq %xmm1, %rax ; AVX512VL-NEXT: vmovq %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm3
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3]
; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax ; AVX512VL-NEXT: vpextrq $1, %xmm1, %rax
; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1 ; AVX512VL-NEXT: vcvtusi2ss %rax, %xmm5, %xmm1
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX512VL-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
▲ Show 20 Lines • Show All 652 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec_smulo.ll

Show First 20 Lines • Show All 474 Lines • ▼ Show 20 Lines
; SSE2-NEXT: pcmpgtd %xmm1, %xmm5 ; SSE2-NEXT: pcmpgtd %xmm1, %xmm5
; SSE2-NEXT: pand %xmm6, %xmm5 ; SSE2-NEXT: pand %xmm6, %xmm5
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: pcmpgtd %xmm6, %xmm0 ; SSE2-NEXT: pcmpgtd %xmm6, %xmm0
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: paddd %xmm5, %xmm0 ; SSE2-NEXT: paddd %xmm5, %xmm0
; SSE2-NEXT: pmuludq %xmm6, %xmm1 ; SSE2-NEXT: pmuludq %xmm6, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,3,2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm12 = xmm12[0,0],xmm10[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm12 = xmm12[0],xmm10[0]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm8[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm8[0]
; SSE2-NEXT: pmuludq %xmm12, %xmm3 ; SSE2-NEXT: pmuludq %xmm12, %xmm3
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,3,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
; SSE2-NEXT: psubd %xmm0, %xmm5 ; SSE2-NEXT: psubd %xmm0, %xmm5
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movdqa %xmm0, (%rcx) ; SSE2-NEXT: movdqa %xmm0, (%rcx)
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; SSSE3-NEXT: pcmpgtd %xmm1, %xmm5 ; SSSE3-NEXT: pcmpgtd %xmm1, %xmm5
; SSSE3-NEXT: pand %xmm6, %xmm5 ; SSSE3-NEXT: pand %xmm6, %xmm5
; SSSE3-NEXT: pxor %xmm0, %xmm0 ; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: pcmpgtd %xmm6, %xmm0 ; SSSE3-NEXT: pcmpgtd %xmm6, %xmm0
; SSSE3-NEXT: pand %xmm1, %xmm0 ; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: paddd %xmm5, %xmm0 ; SSSE3-NEXT: paddd %xmm5, %xmm0
; SSSE3-NEXT: pmuludq %xmm6, %xmm1 ; SSSE3-NEXT: pmuludq %xmm6, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,3,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,3,2,3]
; SSSE3-NEXT: shufps {{.*#+}} xmm12 = xmm12[0,0],xmm10[0,0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm12 = xmm12[0],xmm10[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm8[0,0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm8[0]
; SSSE3-NEXT: pmuludq %xmm12, %xmm3 ; SSSE3-NEXT: pmuludq %xmm12, %xmm3
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,3,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,3,2,3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
; SSSE3-NEXT: psubd %xmm0, %xmm5 ; SSSE3-NEXT: psubd %xmm0, %xmm5
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,2,2,3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-NEXT: movdqa %xmm0, (%rcx) ; SSSE3-NEXT: movdqa %xmm0, (%rcx)
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llvm/test/CodeGen/X86/vec_umulo.ll

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; SSE2-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm0[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm0[0]
; SSE2-NEXT: pmuludq %xmm1, %xmm6 ; SSE2-NEXT: pmuludq %xmm1, %xmm6
; SSE2-NEXT: movd %r9d, %xmm0 ; SSE2-NEXT: movd %r9d, %xmm0
; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; SSE2-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: pmuludq %xmm0, %xmm1 ; SSE2-NEXT: pmuludq %xmm0, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,3,2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm2[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
; SSE2-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm4[0,0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSE2-NEXT: pmuludq %xmm3, %xmm5 ; SSE2-NEXT: pmuludq %xmm3, %xmm5
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,3,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pcmpeqd %xmm2, %xmm0 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; SSE2-NEXT: pcmpeqd %xmm3, %xmm3 ; SSE2-NEXT: pcmpeqd %xmm3, %xmm3
; SSE2-NEXT: pxor %xmm3, %xmm0 ; SSE2-NEXT: pxor %xmm3, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm6[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm6[0,2,2,3]
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm0[0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm0[0]
; SSSE3-NEXT: pmuludq %xmm1, %xmm6 ; SSSE3-NEXT: pmuludq %xmm1, %xmm6
; SSSE3-NEXT: movd %r9d, %xmm0 ; SSSE3-NEXT: movd %r9d, %xmm0
; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; SSSE3-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSSE3-NEXT: pmuludq %xmm0, %xmm1 ; SSSE3-NEXT: pmuludq %xmm0, %xmm1
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,3,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,3,2,3]
; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm2[0,0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm5 = xmm5[0,0],xmm4[0,0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0]
; SSSE3-NEXT: pmuludq %xmm3, %xmm5 ; SSSE3-NEXT: pmuludq %xmm3, %xmm5
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,3,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,3,2,3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; SSSE3-NEXT: pxor %xmm2, %xmm2 ; SSSE3-NEXT: pxor %xmm2, %xmm2
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm0 ; SSSE3-NEXT: pcmpeqd %xmm2, %xmm0
; SSSE3-NEXT: pcmpeqd %xmm3, %xmm3 ; SSSE3-NEXT: pcmpeqd %xmm3, %xmm3
; SSSE3-NEXT: pxor %xmm3, %xmm0 ; SSSE3-NEXT: pxor %xmm3, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm6[0,2,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm6[0,2,2,3]
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llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 6,636 Lines • ▼ Show 20 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_sitofp_v4f32_v4i64: ; AVX1-LABEL: constrained_vector_sitofp_v4f32_v4i64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512F-LABEL: constrained_vector_sitofp_v4f32_v4i64: ; AVX512F-LABEL: constrained_vector_sitofp_v4f32_v4i64:
; AVX512F: # %bb.0: # %entry ; AVX512F: # %bb.0: # %entry
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0 ; AVX512F-NEXT: vcvtsi2ss %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512DQ-LABEL: constrained_vector_sitofp_v4f32_v4i64: ; AVX512DQ-LABEL: constrained_vector_sitofp_v4f32_v4i64:
; AVX512DQ: # %bb.0: # %entry ; AVX512DQ: # %bb.0: # %entry
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; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3 ; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3
; AVX1-NEXT: vorpd %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vorpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1 ; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm0, %ymm1
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm3
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm3 = xmm3[0],xmm4[0]
; AVX1-NEXT: vpextrq $1, %xmm1, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0]
; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm3 ; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm3
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0 ; AVX1-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512F-LABEL: constrained_vector_uitofp_v4f32_v4i64: ; AVX512F-LABEL: constrained_vector_uitofp_v4f32_v4i64:
; AVX512F: # %bb.0: # %entry ; AVX512F: # %bb.0: # %entry
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm2, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm2
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm3, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512DQ-LABEL: constrained_vector_uitofp_v4f32_v4i64: ; AVX512DQ-LABEL: constrained_vector_uitofp_v4f32_v4i64:
; AVX512DQ: # %bb.0: # %entry ; AVX512DQ: # %bb.0: # %entry
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llvm/test/CodeGen/X86/vector-half-conversions.ll

Show All 16 Lines
; ALL-NEXT: vcvtph2ps %xmm0, %xmm0 ; ALL-NEXT: vcvtph2ps %xmm0, %xmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%1 = bitcast i16 %a0 to half %1 = bitcast i16 %a0 to half
%2 = fpext half %1 to float %2 = fpext half %1 to float
ret float %2 ret float %2
} }
define <4 x float> @cvt_4i16_to_4f32(<4 x i16> %a0) nounwind { define <4 x float> @cvt_4i16_to_4f32(<4 x i16> %a0) nounwind {
; ALL-LABEL: cvt_4i16_to_4f32: ; AVX1-LABEL: cvt_4i16_to_4f32:
; ALL: # %bb.0: ; AVX1: # %bb.0:
; ALL-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; ALL-NEXT: movq %rax, %rcx ; AVX1-NEXT: movq %rax, %rcx
; ALL-NEXT: movq %rax, %rdx ; AVX1-NEXT: movq %rax, %rdx
; ALL-NEXT: movswl %ax, %esi ; AVX1-NEXT: movswl %ax, %esi
; ALL-NEXT: # kill: def $eax killed $eax killed $rax ; AVX1-NEXT: # kill: def $eax killed $eax killed $rax
; ALL-NEXT: shrl $16, %eax ; AVX1-NEXT: shrl $16, %eax
; ALL-NEXT: shrq $32, %rcx ; AVX1-NEXT: shrq $32, %rcx
; ALL-NEXT: shrq $48, %rdx ; AVX1-NEXT: shrq $48, %rdx
; ALL-NEXT: movswl %dx, %edx ; AVX1-NEXT: movswl %dx, %edx
; ALL-NEXT: vmovd %edx, %xmm0 ; AVX1-NEXT: vmovd %edx, %xmm0
; ALL-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
; ALL-NEXT: movswl %cx, %ecx ; AVX1-NEXT: movswl %cx, %ecx
; ALL-NEXT: vmovd %ecx, %xmm1 ; AVX1-NEXT: vmovd %ecx, %xmm1
; ALL-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; ALL-NEXT: cwtl ; AVX1-NEXT: cwtl
; ALL-NEXT: vmovd %eax, %xmm2 ; AVX1-NEXT: vmovd %eax, %xmm2
; ALL-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2
; ALL-NEXT: vmovd %esi, %xmm3 ; AVX1-NEXT: vmovd %esi, %xmm3
; ALL-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3
; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; ALL-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: cvt_4i16_to_4f32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: movq %rax, %rdx
; AVX2-NEXT: movswl %ax, %esi
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: shrl $16, %eax
; AVX2-NEXT: shrq $32, %rcx
; AVX2-NEXT: shrq $48, %rdx
; AVX2-NEXT: movswl %dx, %edx
; AVX2-NEXT: vmovd %edx, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX2-NEXT: movswl %cx, %ecx
; AVX2-NEXT: vmovd %ecx, %xmm1
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: cwtl
; AVX2-NEXT: vmovd %eax, %xmm2
; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX2-NEXT: vmovd %esi, %xmm3
; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: retq
;
; AVX512F-LABEL: cvt_4i16_to_4f32:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: movq %rax, %rcx
; AVX512F-NEXT: movq %rax, %rdx
; AVX512F-NEXT: movswl %ax, %esi
; AVX512F-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512F-NEXT: shrl $16, %eax
; AVX512F-NEXT: shrq $32, %rcx
; AVX512F-NEXT: shrq $48, %rdx
; AVX512F-NEXT: movswl %dx, %edx
; AVX512F-NEXT: vmovd %edx, %xmm0
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512F-NEXT: movswl %cx, %ecx
; AVX512F-NEXT: vmovd %ecx, %xmm1
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512F-NEXT: cwtl
; AVX512F-NEXT: vmovd %eax, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vmovd %esi, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: cvt_4i16_to_4f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: movq %rax, %rcx
; AVX512VL-NEXT: movq %rax, %rdx
; AVX512VL-NEXT: movswl %ax, %esi
; AVX512VL-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512VL-NEXT: shrl $16, %eax
; AVX512VL-NEXT: shrq $32, %rcx
; AVX512VL-NEXT: shrq $48, %rdx
; AVX512VL-NEXT: movswl %dx, %edx
; AVX512VL-NEXT: vmovd %edx, %xmm0
; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512VL-NEXT: movswl %cx, %ecx
; AVX512VL-NEXT: vmovd %ecx, %xmm1
; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512VL-NEXT: cwtl
; AVX512VL-NEXT: vmovd %eax, %xmm2
; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512VL-NEXT: vmovd %esi, %xmm3
; AVX512VL-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
%1 = bitcast <4 x i16> %a0 to <4 x half> %1 = bitcast <4 x i16> %a0 to <4 x half>
%2 = fpext <4 x half> %1 to <4 x float> %2 = fpext <4 x half> %1 to <4 x float>
ret <4 x float> %2 ret <4 x float> %2
} }
define <4 x float> @cvt_8i16_to_4f32(<8 x i16> %a0) nounwind { define <4 x float> @cvt_8i16_to_4f32(<8 x i16> %a0) nounwind {
; ALL-LABEL: cvt_8i16_to_4f32: ; AVX1-LABEL: cvt_8i16_to_4f32:
; ALL: # %bb.0: ; AVX1: # %bb.0:
; ALL-NEXT: vmovq %xmm0, %rax ; AVX1-NEXT: vmovq %xmm0, %rax
; ALL-NEXT: movq %rax, %rcx ; AVX1-NEXT: movq %rax, %rcx
; ALL-NEXT: movq %rax, %rdx ; AVX1-NEXT: movq %rax, %rdx
; ALL-NEXT: movswl %ax, %esi ; AVX1-NEXT: movswl %ax, %esi
; ALL-NEXT: # kill: def $eax killed $eax killed $rax ; AVX1-NEXT: # kill: def $eax killed $eax killed $rax
; ALL-NEXT: shrl $16, %eax ; AVX1-NEXT: shrl $16, %eax
; ALL-NEXT: shrq $32, %rcx ; AVX1-NEXT: shrq $32, %rcx
; ALL-NEXT: shrq $48, %rdx ; AVX1-NEXT: shrq $48, %rdx
; ALL-NEXT: movswl %dx, %edx ; AVX1-NEXT: movswl %dx, %edx
; ALL-NEXT: vmovd %edx, %xmm0 ; AVX1-NEXT: vmovd %edx, %xmm0
; ALL-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
; ALL-NEXT: movswl %cx, %ecx ; AVX1-NEXT: movswl %cx, %ecx
; ALL-NEXT: vmovd %ecx, %xmm1 ; AVX1-NEXT: vmovd %ecx, %xmm1
; ALL-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; ALL-NEXT: cwtl ; AVX1-NEXT: cwtl
; ALL-NEXT: vmovd %eax, %xmm2 ; AVX1-NEXT: vmovd %eax, %xmm2
; ALL-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2
; ALL-NEXT: vmovd %esi, %xmm3 ; AVX1-NEXT: vmovd %esi, %xmm3
; ALL-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3
; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; ALL-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: cvt_8i16_to_4f32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: movq %rax, %rdx
; AVX2-NEXT: movswl %ax, %esi
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: shrl $16, %eax
; AVX2-NEXT: shrq $32, %rcx
; AVX2-NEXT: shrq $48, %rdx
; AVX2-NEXT: movswl %dx, %edx
; AVX2-NEXT: vmovd %edx, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX2-NEXT: movswl %cx, %ecx
; AVX2-NEXT: vmovd %ecx, %xmm1
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: cwtl
; AVX2-NEXT: vmovd %eax, %xmm2
; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX2-NEXT: vmovd %esi, %xmm3
; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: retq
;
; AVX512F-LABEL: cvt_8i16_to_4f32:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vmovq %xmm0, %rax
; AVX512F-NEXT: movq %rax, %rcx
; AVX512F-NEXT: movq %rax, %rdx
; AVX512F-NEXT: movswl %ax, %esi
; AVX512F-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512F-NEXT: shrl $16, %eax
; AVX512F-NEXT: shrq $32, %rcx
; AVX512F-NEXT: shrq $48, %rdx
; AVX512F-NEXT: movswl %dx, %edx
; AVX512F-NEXT: vmovd %edx, %xmm0
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512F-NEXT: movswl %cx, %ecx
; AVX512F-NEXT: vmovd %ecx, %xmm1
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512F-NEXT: cwtl
; AVX512F-NEXT: vmovd %eax, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vmovd %esi, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: cvt_8i16_to_4f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovq %xmm0, %rax
; AVX512VL-NEXT: movq %rax, %rcx
; AVX512VL-NEXT: movq %rax, %rdx
; AVX512VL-NEXT: movswl %ax, %esi
; AVX512VL-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512VL-NEXT: shrl $16, %eax
; AVX512VL-NEXT: shrq $32, %rcx
; AVX512VL-NEXT: shrq $48, %rdx
; AVX512VL-NEXT: movswl %dx, %edx
; AVX512VL-NEXT: vmovd %edx, %xmm0
; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512VL-NEXT: movswl %cx, %ecx
; AVX512VL-NEXT: vmovd %ecx, %xmm1
; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512VL-NEXT: cwtl
; AVX512VL-NEXT: vmovd %eax, %xmm2
; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512VL-NEXT: vmovd %esi, %xmm3
; AVX512VL-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
%1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %1 = shufflevector <8 x i16> %a0, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%2 = bitcast <4 x i16> %1 to <4 x half> %2 = bitcast <4 x i16> %1 to <4 x half>
%3 = fpext <4 x half> %2 to <4 x float> %3 = fpext <4 x half> %2 to <4 x float>
ret <4 x float> %3 ret <4 x float> %3
} }
define <8 x float> @cvt_8i16_to_8f32(<8 x i16> %a0) nounwind { define <8 x float> @cvt_8i16_to_8f32(<8 x i16> %a0) nounwind {
; ALL-LABEL: cvt_8i16_to_8f32: ; AVX1-LABEL: cvt_8i16_to_8f32:
; ALL: # %bb.0: ; AVX1: # %bb.0:
; ALL-NEXT: vpextrq $1, %xmm0, %rdx ; AVX1-NEXT: vpextrq $1, %xmm0, %rdx
; ALL-NEXT: movq %rdx, %r8 ; AVX1-NEXT: movq %rdx, %r8
; ALL-NEXT: movq %rdx, %r10 ; AVX1-NEXT: movq %rdx, %r10
; ALL-NEXT: movswl %dx, %r9d ; AVX1-NEXT: movswl %dx, %r9d
; ALL-NEXT: # kill: def $edx killed $edx killed $rdx ; AVX1-NEXT: # kill: def $edx killed $edx killed $rdx
; ALL-NEXT: shrl $16, %edx ; AVX1-NEXT: shrl $16, %edx
; ALL-NEXT: shrq $32, %r8 ; AVX1-NEXT: shrq $32, %r8
; ALL-NEXT: shrq $48, %r10 ; AVX1-NEXT: shrq $48, %r10
; ALL-NEXT: vmovq %xmm0, %rdi ; AVX1-NEXT: vmovq %xmm0, %rdi
; ALL-NEXT: movq %rdi, %rax ; AVX1-NEXT: movq %rdi, %rax
; ALL-NEXT: movq %rdi, %rsi ; AVX1-NEXT: movq %rdi, %rsi
; ALL-NEXT: movswl %di, %ecx ; AVX1-NEXT: movswl %di, %ecx
; ALL-NEXT: # kill: def $edi killed $edi killed $rdi ; AVX1-NEXT: # kill: def $edi killed $edi killed $rdi
; ALL-NEXT: shrl $16, %edi ; AVX1-NEXT: shrl $16, %edi
; ALL-NEXT: shrq $32, %rax ; AVX1-NEXT: shrq $32, %rax
; ALL-NEXT: shrq $48, %rsi ; AVX1-NEXT: shrq $48, %rsi
; ALL-NEXT: movswl %si, %esi ; AVX1-NEXT: movswl %si, %esi
; ALL-NEXT: vmovd %esi, %xmm0 ; AVX1-NEXT: vmovd %esi, %xmm0
; ALL-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
; ALL-NEXT: cwtl ; AVX1-NEXT: cwtl
; ALL-NEXT: vmovd %eax, %xmm1 ; AVX1-NEXT: vmovd %eax, %xmm1
; ALL-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; ALL-NEXT: movswl %di, %eax ; AVX1-NEXT: movswl %di, %eax
; ALL-NEXT: vmovd %eax, %xmm2 ; AVX1-NEXT: vmovd %eax, %xmm2
; ALL-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2
; ALL-NEXT: vmovd %ecx, %xmm3 ; AVX1-NEXT: vmovd %ecx, %xmm3
; ALL-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3
; ALL-NEXT: movswl %r10w, %eax ; AVX1-NEXT: movswl %r10w, %eax
; ALL-NEXT: vmovd %eax, %xmm4 ; AVX1-NEXT: vmovd %eax, %xmm4
; ALL-NEXT: vcvtph2ps %xmm4, %xmm4 ; AVX1-NEXT: vcvtph2ps %xmm4, %xmm4
; ALL-NEXT: movswl %r8w, %eax ; AVX1-NEXT: movswl %r8w, %eax
; ALL-NEXT: vmovd %eax, %xmm5 ; AVX1-NEXT: vmovd %eax, %xmm5
; ALL-NEXT: vcvtph2ps %xmm5, %xmm5 ; AVX1-NEXT: vcvtph2ps %xmm5, %xmm5
; ALL-NEXT: movswl %dx, %eax ; AVX1-NEXT: movswl %dx, %eax
; ALL-NEXT: vmovd %eax, %xmm6 ; AVX1-NEXT: vmovd %eax, %xmm6
; ALL-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX1-NEXT: vcvtph2ps %xmm6, %xmm6
; ALL-NEXT: vmovd %r9d, %xmm7 ; AVX1-NEXT: vmovd %r9d, %xmm7
; ALL-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX1-NEXT: vcvtph2ps %xmm7, %xmm7
; ALL-NEXT: vinsertps {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm5 = xmm6[0,1],xmm5[0],xmm6[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm5 = xmm6[0],xmm5[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; ALL-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; ALL-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: cvt_8i16_to_8f32:
; AVX2: # %bb.0:
; AVX2-NEXT: vpextrq $1, %xmm0, %rdx
; AVX2-NEXT: movq %rdx, %r8
; AVX2-NEXT: movq %rdx, %r10
; AVX2-NEXT: movswl %dx, %r9d
; AVX2-NEXT: # kill: def $edx killed $edx killed $rdx
; AVX2-NEXT: shrl $16, %edx
; AVX2-NEXT: shrq $32, %r8
; AVX2-NEXT: shrq $48, %r10
; AVX2-NEXT: vmovq %xmm0, %rdi
; AVX2-NEXT: movq %rdi, %rax
; AVX2-NEXT: movq %rdi, %rsi
; AVX2-NEXT: movswl %di, %ecx
; AVX2-NEXT: # kill: def $edi killed $edi killed $rdi
; AVX2-NEXT: shrl $16, %edi
; AVX2-NEXT: shrq $32, %rax
; AVX2-NEXT: shrq $48, %rsi
; AVX2-NEXT: movswl %si, %esi
; AVX2-NEXT: vmovd %esi, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX2-NEXT: cwtl
; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: movswl %di, %eax
; AVX2-NEXT: vmovd %eax, %xmm2
; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX2-NEXT: vmovd %ecx, %xmm3
; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX2-NEXT: movswl %r10w, %eax
; AVX2-NEXT: vmovd %eax, %xmm4
; AVX2-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX2-NEXT: movswl %r8w, %eax
; AVX2-NEXT: vmovd %eax, %xmm5
; AVX2-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX2-NEXT: movswl %dx, %eax
; AVX2-NEXT: vmovd %eax, %xmm6
; AVX2-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX2-NEXT: vmovd %r9d, %xmm7
; AVX2-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX2-NEXT: vunpcklps {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm5 = xmm6[0],xmm5[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: cvt_8i16_to_8f32:
; AVX512F: # %bb.0:
; AVX512F-NEXT: vpextrq $1, %xmm0, %rdx
; AVX512F-NEXT: movq %rdx, %r8
; AVX512F-NEXT: movq %rdx, %r10
; AVX512F-NEXT: movswl %dx, %r9d
; AVX512F-NEXT: # kill: def $edx killed $edx killed $rdx
; AVX512F-NEXT: shrl $16, %edx
; AVX512F-NEXT: shrq $32, %r8
; AVX512F-NEXT: shrq $48, %r10
; AVX512F-NEXT: vmovq %xmm0, %rdi
; AVX512F-NEXT: movq %rdi, %rax
; AVX512F-NEXT: movq %rdi, %rsi
; AVX512F-NEXT: movswl %di, %ecx
; AVX512F-NEXT: # kill: def $edi killed $edi killed $rdi
; AVX512F-NEXT: shrl $16, %edi
; AVX512F-NEXT: shrq $32, %rax
; AVX512F-NEXT: shrq $48, %rsi
; AVX512F-NEXT: movswl %si, %esi
; AVX512F-NEXT: vmovd %esi, %xmm0
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512F-NEXT: cwtl
; AVX512F-NEXT: vmovd %eax, %xmm1
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512F-NEXT: movswl %di, %eax
; AVX512F-NEXT: vmovd %eax, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vmovd %ecx, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: movswl %r10w, %eax
; AVX512F-NEXT: vmovd %eax, %xmm4
; AVX512F-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX512F-NEXT: movswl %r8w, %eax
; AVX512F-NEXT: vmovd %eax, %xmm5
; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX512F-NEXT: movswl %dx, %eax
; AVX512F-NEXT: vmovd %eax, %xmm6
; AVX512F-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX512F-NEXT: vmovd %r9d, %xmm7
; AVX512F-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm5 = xmm6[0],xmm5[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: cvt_8i16_to_8f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpextrq $1, %xmm0, %rdx
; AVX512VL-NEXT: movq %rdx, %r8
; AVX512VL-NEXT: movq %rdx, %r10
; AVX512VL-NEXT: movswl %dx, %r9d
; AVX512VL-NEXT: # kill: def $edx killed $edx killed $rdx
; AVX512VL-NEXT: shrl $16, %edx
; AVX512VL-NEXT: shrq $32, %r8
; AVX512VL-NEXT: shrq $48, %r10
; AVX512VL-NEXT: vmovq %xmm0, %rdi
; AVX512VL-NEXT: movq %rdi, %rax
; AVX512VL-NEXT: movq %rdi, %rsi
; AVX512VL-NEXT: movswl %di, %ecx
; AVX512VL-NEXT: # kill: def $edi killed $edi killed $rdi
; AVX512VL-NEXT: shrl $16, %edi
; AVX512VL-NEXT: shrq $32, %rax
; AVX512VL-NEXT: shrq $48, %rsi
; AVX512VL-NEXT: movswl %si, %esi
; AVX512VL-NEXT: vmovd %esi, %xmm0
; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512VL-NEXT: cwtl
; AVX512VL-NEXT: vmovd %eax, %xmm1
; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512VL-NEXT: movswl %di, %eax
; AVX512VL-NEXT: vmovd %eax, %xmm2
; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512VL-NEXT: vmovd %ecx, %xmm3
; AVX512VL-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512VL-NEXT: movswl %r10w, %eax
; AVX512VL-NEXT: vmovd %eax, %xmm4
; AVX512VL-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX512VL-NEXT: movswl %r8w, %eax
; AVX512VL-NEXT: vmovd %eax, %xmm5
; AVX512VL-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX512VL-NEXT: movswl %dx, %eax
; AVX512VL-NEXT: vmovd %eax, %xmm6
; AVX512VL-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX512VL-NEXT: vmovd %r9d, %xmm7
; AVX512VL-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm5 = xmm6[0,1],xmm5[0],xmm6[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX512VL-NEXT: retq
%1 = bitcast <8 x i16> %a0 to <8 x half> %1 = bitcast <8 x i16> %a0 to <8 x half>
%2 = fpext <8 x half> %1 to <8 x float> %2 = fpext <8 x half> %1 to <8 x float>
ret <8 x float> %2 ret <8 x float> %2
} }
define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind { define <16 x float> @cvt_16i16_to_16f32(<16 x i16> %a0) nounwind {
; AVX1-LABEL: cvt_16i16_to_16f32: ; AVX1-LABEL: cvt_16i16_to_16f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX1-NEXT: vcvtph2ps %xmm4, %xmm4 ; AVX1-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX1-NEXT: vcvtph2ps %xmm5, %xmm5 ; AVX1-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX1-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX1-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX1-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX1-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm6[0],xmm1[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm6[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm15[0],xmm14[0],xmm15[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm1 = xmm15[0],xmm14[0],xmm15[1],xmm14[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm13[0],xmm1[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm13[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm11[0],xmm10[0],xmm11[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm11[0],xmm10[0],xmm11[1],xmm10[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm9[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: cvt_16i16_to_16f32: ; AVX2-LABEL: cvt_16i16_to_16f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm4 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm4
; AVX2-NEXT: vmovq %xmm4, %rax ; AVX2-NEXT: vmovq %xmm4, %rax
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; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX2-NEXT: vcvtph2ps %xmm4, %xmm4 ; AVX2-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm5, %xmm5 ; AVX2-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX2-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX2-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX2-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX2-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm6[0],xmm1[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm6[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm3[0],xmm0[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm3[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm15[0],xmm14[0],xmm15[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm15[0],xmm14[0],xmm15[1],xmm14[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm13[0],xmm1[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm13[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm11[0],xmm10[0],xmm11[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm11[0],xmm10[0],xmm11[1],xmm10[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm9[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: cvt_16i16_to_16f32: ; AVX512F-LABEL: cvt_16i16_to_16f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm10 ; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm10
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
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; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512F-NEXT: vcvtph2ps %xmm4, %xmm4 ; AVX512F-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX512F-NEXT: vcvtph2ps %xmm10, %xmm10 ; AVX512F-NEXT: vcvtph2ps %xmm10, %xmm10
; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5 ; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX512F-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX512F-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX512F-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX512F-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm6[0],xmm0[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm6[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm5[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm5[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm4 = xmm10[0],xmm4[0],xmm10[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm4 = xmm10[0],xmm4[0],xmm10[1],xmm4[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm4[0,1],xmm1[0],xmm4[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm4[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX512F-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm15[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm15[0],xmm2[1],xmm15[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm14[0],xmm1[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm14[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm13[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm13[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm12[0],xmm11[0],xmm12[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm12[0],xmm11[0],xmm12[1],xmm11[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm9[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: cvt_16i16_to_16f32: ; AVX512VL-LABEL: cvt_16i16_to_16f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm10 ; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm10
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; AVX512VL-NEXT: vcvtph2ps %xmm17, %xmm4 ; AVX512VL-NEXT: vcvtph2ps %xmm17, %xmm4
; AVX512VL-NEXT: vcvtph2ps %xmm18, %xmm0 ; AVX512VL-NEXT: vcvtph2ps %xmm18, %xmm0
; AVX512VL-NEXT: vcvtph2ps %xmm19, %xmm5 ; AVX512VL-NEXT: vcvtph2ps %xmm19, %xmm5
; AVX512VL-NEXT: vcvtph2ps %xmm10, %xmm7 ; AVX512VL-NEXT: vcvtph2ps %xmm10, %xmm7
; AVX512VL-NEXT: vcvtph2ps %xmm20, %xmm3 ; AVX512VL-NEXT: vcvtph2ps %xmm20, %xmm3
; AVX512VL-NEXT: vcvtph2ps %xmm21, %xmm6 ; AVX512VL-NEXT: vcvtph2ps %xmm21, %xmm6
; AVX512VL-NEXT: vcvtph2ps %xmm22, %xmm1 ; AVX512VL-NEXT: vcvtph2ps %xmm22, %xmm1
; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm6[0],xmm1[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm6[0],xmm1[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm3[0]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm7[0],xmm5[0],xmm7[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm7[0],xmm5[0],xmm7[1],xmm5[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm16[0],xmm15[0],xmm16[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm1 = xmm16[0],xmm15[0],xmm16[1],xmm15[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm14[0],xmm1[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm14[0],xmm1[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm13[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm13[0]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm12[0],xmm11[0],xmm12[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm12[0],xmm11[0],xmm12[1],xmm11[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX512VL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512VL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%1 = bitcast <16 x i16> %a0 to <16 x half> %1 = bitcast <16 x i16> %a0 to <16 x half>
%2 = fpext <16 x half> %1 to <16 x float> %2 = fpext <16 x half> %1 to <16 x float>
ret <16 x float> %2 ret <16 x float> %2
Show All 12 Lines
; ALL-NEXT: retq ; ALL-NEXT: retq
%1 = load i16, i16* %a0 %1 = load i16, i16* %a0
%2 = bitcast i16 %1 to half %2 = bitcast i16 %1 to half
%3 = fpext half %2 to float %3 = fpext half %2 to float
ret float %3 ret float %3
} }
define <4 x float> @load_cvt_4i16_to_4f32(<4 x i16>* %a0) nounwind { define <4 x float> @load_cvt_4i16_to_4f32(<4 x i16>* %a0) nounwind {
; ALL-LABEL: load_cvt_4i16_to_4f32: ; AVX1-LABEL: load_cvt_4i16_to_4f32:
; ALL: # %bb.0: ; AVX1: # %bb.0:
; ALL-NEXT: movswl 6(%rdi), %eax ; AVX1-NEXT: movswl 6(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm0 ; AVX1-NEXT: vmovd %eax, %xmm0
; ALL-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
; ALL-NEXT: movswl 4(%rdi), %eax ; AVX1-NEXT: movswl 4(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm1 ; AVX1-NEXT: vmovd %eax, %xmm1
; ALL-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; ALL-NEXT: movswl (%rdi), %eax ; AVX1-NEXT: movswl (%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm2 ; AVX1-NEXT: vmovd %eax, %xmm2
; ALL-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2
; ALL-NEXT: movswl 2(%rdi), %eax ; AVX1-NEXT: movswl 2(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm3 ; AVX1-NEXT: vmovd %eax, %xmm3
; ALL-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3
; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; ALL-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: load_cvt_4i16_to_4f32:
; AVX2: # %bb.0:
; AVX2-NEXT: movswl 6(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX2-NEXT: movswl 4(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: movswl (%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm2
; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX2-NEXT: movswl 2(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm3
; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: retq
;
; AVX512F-LABEL: load_cvt_4i16_to_4f32:
; AVX512F: # %bb.0:
; AVX512F-NEXT: movswl 6(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm0
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512F-NEXT: movswl 4(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm1
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512F-NEXT: movswl (%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: movswl 2(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: load_cvt_4i16_to_4f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: movswl 6(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm0
; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512VL-NEXT: movswl 4(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm1
; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512VL-NEXT: movswl (%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm2
; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512VL-NEXT: movswl 2(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm3
; AVX512VL-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
%1 = load <4 x i16>, <4 x i16>* %a0 %1 = load <4 x i16>, <4 x i16>* %a0
%2 = bitcast <4 x i16> %1 to <4 x half> %2 = bitcast <4 x i16> %1 to <4 x half>
%3 = fpext <4 x half> %2 to <4 x float> %3 = fpext <4 x half> %2 to <4 x float>
ret <4 x float> %3 ret <4 x float> %3
} }
define <4 x float> @load_cvt_8i16_to_4f32(<8 x i16>* %a0) nounwind { define <4 x float> @load_cvt_8i16_to_4f32(<8 x i16>* %a0) nounwind {
; ALL-LABEL: load_cvt_8i16_to_4f32: ; AVX1-LABEL: load_cvt_8i16_to_4f32:
; ALL: # %bb.0: ; AVX1: # %bb.0:
; ALL-NEXT: movq (%rdi), %rax ; AVX1-NEXT: movq (%rdi), %rax
; ALL-NEXT: movq %rax, %rcx ; AVX1-NEXT: movq %rax, %rcx
; ALL-NEXT: movq %rax, %rdx ; AVX1-NEXT: movq %rax, %rdx
; ALL-NEXT: movswl %ax, %esi ; AVX1-NEXT: movswl %ax, %esi
; ALL-NEXT: # kill: def $eax killed $eax killed $rax ; AVX1-NEXT: # kill: def $eax killed $eax killed $rax
; ALL-NEXT: shrl $16, %eax ; AVX1-NEXT: shrl $16, %eax
; ALL-NEXT: shrq $32, %rcx ; AVX1-NEXT: shrq $32, %rcx
; ALL-NEXT: shrq $48, %rdx ; AVX1-NEXT: shrq $48, %rdx
; ALL-NEXT: movswl %dx, %edx ; AVX1-NEXT: movswl %dx, %edx
; ALL-NEXT: vmovd %edx, %xmm0 ; AVX1-NEXT: vmovd %edx, %xmm0
; ALL-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
; ALL-NEXT: movswl %cx, %ecx ; AVX1-NEXT: movswl %cx, %ecx
; ALL-NEXT: vmovd %ecx, %xmm1 ; AVX1-NEXT: vmovd %ecx, %xmm1
; ALL-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; ALL-NEXT: cwtl ; AVX1-NEXT: cwtl
; ALL-NEXT: vmovd %eax, %xmm2 ; AVX1-NEXT: vmovd %eax, %xmm2
; ALL-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2
; ALL-NEXT: vmovd %esi, %xmm3 ; AVX1-NEXT: vmovd %esi, %xmm3
; ALL-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3
; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; ALL-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: load_cvt_8i16_to_4f32:
; AVX2: # %bb.0:
; AVX2-NEXT: movq (%rdi), %rax
; AVX2-NEXT: movq %rax, %rcx
; AVX2-NEXT: movq %rax, %rdx
; AVX2-NEXT: movswl %ax, %esi
; AVX2-NEXT: # kill: def $eax killed $eax killed $rax
; AVX2-NEXT: shrl $16, %eax
; AVX2-NEXT: shrq $32, %rcx
; AVX2-NEXT: shrq $48, %rdx
; AVX2-NEXT: movswl %dx, %edx
; AVX2-NEXT: vmovd %edx, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX2-NEXT: movswl %cx, %ecx
; AVX2-NEXT: vmovd %ecx, %xmm1
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: cwtl
; AVX2-NEXT: vmovd %eax, %xmm2
; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX2-NEXT: vmovd %esi, %xmm3
; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: retq
;
; AVX512F-LABEL: load_cvt_8i16_to_4f32:
; AVX512F: # %bb.0:
; AVX512F-NEXT: movq (%rdi), %rax
; AVX512F-NEXT: movq %rax, %rcx
; AVX512F-NEXT: movq %rax, %rdx
; AVX512F-NEXT: movswl %ax, %esi
; AVX512F-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512F-NEXT: shrl $16, %eax
; AVX512F-NEXT: shrq $32, %rcx
; AVX512F-NEXT: shrq $48, %rdx
; AVX512F-NEXT: movswl %dx, %edx
; AVX512F-NEXT: vmovd %edx, %xmm0
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512F-NEXT: movswl %cx, %ecx
; AVX512F-NEXT: vmovd %ecx, %xmm1
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512F-NEXT: cwtl
; AVX512F-NEXT: vmovd %eax, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: vmovd %esi, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: load_cvt_8i16_to_4f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: movq (%rdi), %rax
; AVX512VL-NEXT: movq %rax, %rcx
; AVX512VL-NEXT: movq %rax, %rdx
; AVX512VL-NEXT: movswl %ax, %esi
; AVX512VL-NEXT: # kill: def $eax killed $eax killed $rax
; AVX512VL-NEXT: shrl $16, %eax
; AVX512VL-NEXT: shrq $32, %rcx
; AVX512VL-NEXT: shrq $48, %rdx
; AVX512VL-NEXT: movswl %dx, %edx
; AVX512VL-NEXT: vmovd %edx, %xmm0
; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512VL-NEXT: movswl %cx, %ecx
; AVX512VL-NEXT: vmovd %ecx, %xmm1
; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512VL-NEXT: cwtl
; AVX512VL-NEXT: vmovd %eax, %xmm2
; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512VL-NEXT: vmovd %esi, %xmm3
; AVX512VL-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: retq
%1 = load <8 x i16>, <8 x i16>* %a0 %1 = load <8 x i16>, <8 x i16>* %a0
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%3 = bitcast <4 x i16> %2 to <4 x half> %3 = bitcast <4 x i16> %2 to <4 x half>
%4 = fpext <4 x half> %3 to <4 x float> %4 = fpext <4 x half> %3 to <4 x float>
ret <4 x float> %4 ret <4 x float> %4
} }
define <8 x float> @load_cvt_8i16_to_8f32(<8 x i16>* %a0) nounwind { define <8 x float> @load_cvt_8i16_to_8f32(<8 x i16>* %a0) nounwind {
; ALL-LABEL: load_cvt_8i16_to_8f32: ; AVX1-LABEL: load_cvt_8i16_to_8f32:
; ALL: # %bb.0: ; AVX1: # %bb.0:
; ALL-NEXT: movswl 6(%rdi), %eax ; AVX1-NEXT: movswl 6(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm0 ; AVX1-NEXT: vmovd %eax, %xmm0
; ALL-NEXT: vcvtph2ps %xmm0, %xmm0 ; AVX1-NEXT: vcvtph2ps %xmm0, %xmm0
; ALL-NEXT: movswl 4(%rdi), %eax ; AVX1-NEXT: movswl 4(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm1 ; AVX1-NEXT: vmovd %eax, %xmm1
; ALL-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; ALL-NEXT: movswl (%rdi), %eax ; AVX1-NEXT: movswl (%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm2 ; AVX1-NEXT: vmovd %eax, %xmm2
; ALL-NEXT: vcvtph2ps %xmm2, %xmm2 ; AVX1-NEXT: vcvtph2ps %xmm2, %xmm2
; ALL-NEXT: movswl 2(%rdi), %eax ; AVX1-NEXT: movswl 2(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm3 ; AVX1-NEXT: vmovd %eax, %xmm3
; ALL-NEXT: vcvtph2ps %xmm3, %xmm3 ; AVX1-NEXT: vcvtph2ps %xmm3, %xmm3
; ALL-NEXT: movswl 14(%rdi), %eax ; AVX1-NEXT: movswl 14(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm4 ; AVX1-NEXT: vmovd %eax, %xmm4
; ALL-NEXT: vcvtph2ps %xmm4, %xmm4 ; AVX1-NEXT: vcvtph2ps %xmm4, %xmm4
; ALL-NEXT: movswl 12(%rdi), %eax ; AVX1-NEXT: movswl 12(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm5 ; AVX1-NEXT: vmovd %eax, %xmm5
; ALL-NEXT: vcvtph2ps %xmm5, %xmm5 ; AVX1-NEXT: vcvtph2ps %xmm5, %xmm5
; ALL-NEXT: movswl 8(%rdi), %eax ; AVX1-NEXT: movswl 8(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm6 ; AVX1-NEXT: vmovd %eax, %xmm6
; ALL-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX1-NEXT: vcvtph2ps %xmm6, %xmm6
; ALL-NEXT: movswl 10(%rdi), %eax ; AVX1-NEXT: movswl 10(%rdi), %eax
; ALL-NEXT: vmovd %eax, %xmm7 ; AVX1-NEXT: vmovd %eax, %xmm7
; ALL-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX1-NEXT: vcvtph2ps %xmm7, %xmm7
; ALL-NEXT: vinsertps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm5 = xmm6[0,1],xmm5[0],xmm6[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm5 = xmm6[0],xmm5[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; ALL-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; ALL-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: load_cvt_8i16_to_8f32:
; AVX2: # %bb.0:
; AVX2-NEXT: movswl 6(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX2-NEXT: movswl 4(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: movswl (%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm2
; AVX2-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX2-NEXT: movswl 2(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm3
; AVX2-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX2-NEXT: movswl 14(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm4
; AVX2-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX2-NEXT: movswl 12(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm5
; AVX2-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX2-NEXT: movswl 8(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm6
; AVX2-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX2-NEXT: movswl 10(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm7
; AVX2-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX2-NEXT: vunpcklps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm5 = xmm6[0],xmm5[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX2-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX2-NEXT: retq
;
; AVX512F-LABEL: load_cvt_8i16_to_8f32:
; AVX512F: # %bb.0:
; AVX512F-NEXT: movswl 6(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm0
; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512F-NEXT: movswl 4(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm1
; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512F-NEXT: movswl (%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm2
; AVX512F-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512F-NEXT: movswl 2(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm3
; AVX512F-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512F-NEXT: movswl 14(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm4
; AVX512F-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX512F-NEXT: movswl 12(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm5
; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX512F-NEXT: movswl 8(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm6
; AVX512F-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX512F-NEXT: movswl 10(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm7
; AVX512F-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm5 = xmm6[0],xmm5[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX512F-NEXT: retq
;
; AVX512VL-LABEL: load_cvt_8i16_to_8f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: movswl 6(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm0
; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm0
; AVX512VL-NEXT: movswl 4(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm1
; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX512VL-NEXT: movswl (%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm2
; AVX512VL-NEXT: vcvtph2ps %xmm2, %xmm2
; AVX512VL-NEXT: movswl 2(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm3
; AVX512VL-NEXT: vcvtph2ps %xmm3, %xmm3
; AVX512VL-NEXT: movswl 14(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm4
; AVX512VL-NEXT: vcvtph2ps %xmm4, %xmm4
; AVX512VL-NEXT: movswl 12(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm5
; AVX512VL-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX512VL-NEXT: movswl 8(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm6
; AVX512VL-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX512VL-NEXT: movswl 10(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm7
; AVX512VL-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm5 = xmm6[0,1],xmm5[0],xmm6[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX512VL-NEXT: retq
%1 = load <8 x i16>, <8 x i16>* %a0 %1 = load <8 x i16>, <8 x i16>* %a0
%2 = bitcast <8 x i16> %1 to <8 x half> %2 = bitcast <8 x i16> %1 to <8 x half>
%3 = fpext <8 x half> %2 to <8 x float> %3 = fpext <8 x half> %2 to <8 x float>
ret <8 x float> %3 ret <8 x float> %3
} }
define <16 x float> @load_cvt_16i16_to_16f32(<16 x i16>* %a0) nounwind { define <16 x float> @load_cvt_16i16_to_16f32(<16 x i16>* %a0) nounwind {
; AVX1-LABEL: load_cvt_16i16_to_16f32: ; AVX1-LABEL: load_cvt_16i16_to_16f32:
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; AVX1-NEXT: vmovd %eax, %xmm6 ; AVX1-NEXT: vmovd %eax, %xmm6
; AVX1-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX1-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX1-NEXT: movswl 8(%rdi), %eax ; AVX1-NEXT: movswl 8(%rdi), %eax
; AVX1-NEXT: vmovd %eax, %xmm7 ; AVX1-NEXT: vmovd %eax, %xmm7
; AVX1-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX1-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX1-NEXT: movswl 10(%rdi), %eax ; AVX1-NEXT: movswl 10(%rdi), %eax
; AVX1-NEXT: vmovd %eax, %xmm1 ; AVX1-NEXT: vmovd %eax, %xmm1
; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX1-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm7[0],xmm1[0],xmm7[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm1 = xmm7[0],xmm1[0],xmm7[1],xmm1[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm6[0],xmm1[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm6[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1],xmm2[0],xmm3[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[1],xmm15[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm13[0],xmm1[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm13[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[2,3] ; AVX1-NEXT: vunpcklps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm9[0]
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: load_cvt_16i16_to_16f32: ; AVX2-LABEL: load_cvt_16i16_to_16f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: movswl 22(%rdi), %eax ; AVX2-NEXT: movswl 22(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm0 ; AVX2-NEXT: vmovd %eax, %xmm0
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; AVX2-NEXT: vmovd %eax, %xmm6 ; AVX2-NEXT: vmovd %eax, %xmm6
; AVX2-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX2-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX2-NEXT: movswl 8(%rdi), %eax ; AVX2-NEXT: movswl 8(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm7 ; AVX2-NEXT: vmovd %eax, %xmm7
; AVX2-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX2-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX2-NEXT: movswl 10(%rdi), %eax ; AVX2-NEXT: movswl 10(%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm1 ; AVX2-NEXT: vmovd %eax, %xmm1
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1 ; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm7[0],xmm1[0],xmm7[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm7[0],xmm1[0],xmm7[1],xmm1[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm6[0],xmm1[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm6[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm5[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0,1],xmm2[0],xmm3[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm2 = xmm3[0],xmm2[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[1],xmm15[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm13[0],xmm1[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm13[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[2,3] ; AVX2-NEXT: vunpcklps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX2-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm9[0]
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512F-LABEL: load_cvt_16i16_to_16f32: ; AVX512F-LABEL: load_cvt_16i16_to_16f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: movswl 6(%rdi), %eax ; AVX512F-NEXT: movswl 6(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm0 ; AVX512F-NEXT: vmovd %eax, %xmm0
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; AVX512F-NEXT: vmovd %eax, %xmm5 ; AVX512F-NEXT: vmovd %eax, %xmm5
; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5 ; AVX512F-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX512F-NEXT: movswl 24(%rdi), %eax ; AVX512F-NEXT: movswl 24(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm6 ; AVX512F-NEXT: vmovd %eax, %xmm6
; AVX512F-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX512F-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX512F-NEXT: movswl 26(%rdi), %eax ; AVX512F-NEXT: movswl 26(%rdi), %eax
; AVX512F-NEXT: vmovd %eax, %xmm7 ; AVX512F-NEXT: vmovd %eax, %xmm7
; AVX512F-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX512F-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX512F-NEXT: vinsertps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm5 = xmm6[0,1],xmm5[0],xmm6[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm5 = xmm6[0],xmm5[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX512F-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[1],xmm15[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm13[0],xmm1[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm13[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[2,3] ; AVX512F-NEXT: vunpcklps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX512F-NEXT: vmovlhps {{.*#+}} xmm2 = xmm2[0],xmm9[0]
; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX512F-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX512F-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512F-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: load_cvt_16i16_to_16f32: ; AVX512VL-LABEL: load_cvt_16i16_to_16f32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: movswl 6(%rdi), %eax ; AVX512VL-NEXT: movswl 6(%rdi), %eax
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; AVX512VL-NEXT: vmovd %eax, %xmm5 ; AVX512VL-NEXT: vmovd %eax, %xmm5
; AVX512VL-NEXT: vcvtph2ps %xmm5, %xmm5 ; AVX512VL-NEXT: vcvtph2ps %xmm5, %xmm5
; AVX512VL-NEXT: movswl 24(%rdi), %eax ; AVX512VL-NEXT: movswl 24(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm6 ; AVX512VL-NEXT: vmovd %eax, %xmm6
; AVX512VL-NEXT: vcvtph2ps %xmm6, %xmm6 ; AVX512VL-NEXT: vcvtph2ps %xmm6, %xmm6
; AVX512VL-NEXT: movswl 26(%rdi), %eax ; AVX512VL-NEXT: movswl 26(%rdi), %eax
; AVX512VL-NEXT: vmovd %eax, %xmm7 ; AVX512VL-NEXT: vmovd %eax, %xmm7
; AVX512VL-NEXT: vcvtph2ps %xmm7, %xmm7 ; AVX512VL-NEXT: vcvtph2ps %xmm7, %xmm7
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm5 = xmm6[0,1],xmm5[0],xmm6[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm5 = xmm6[0,1],xmm5[0],xmm6[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm4 = xmm5[0,1,2],xmm4[0]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX512VL-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm1 = xmm14[0],xmm15[0],xmm14[1],xmm15[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm13[0],xmm1[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm13[0],xmm1[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm12[0]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[2,3] ; AVX512VL-NEXT: vunpcklps {{.*#+}} xmm2 = xmm10[0],xmm11[0],xmm10[1],xmm11[1]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm9[0],xmm2[3]
; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0] ; AVX512VL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm8[0]
; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX512VL-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX512VL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512VL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%1 = load <16 x i16>, <16 x i16>* %a0 %1 = load <16 x i16>, <16 x i16>* %a0
%2 = bitcast <16 x i16> %1 to <16 x half> %2 = bitcast <16 x i16> %1 to <16 x half>
%3 = fpext <16 x half> %2 to <16 x float> %3 = fpext <16 x half> %2 to <16 x float>
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llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll

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; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 ; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2 ; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm4
; AVX1-NEXT: vpsllw $7, %xmm4, %xmm4 ; AVX1-NEXT: vpsllw $7, %xmm4, %xmm4
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6],xmm4[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,5,6],xmm4[7]
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 ; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3 ; AVX1-NEXT: vpsrlw $8, %xmm3, %xmm3
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm4 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm5 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5 ; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5
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; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm4 = xmm4[0],zero,xmm4[1],zero,xmm4[2],zero,xmm4[3],zero,xmm4[4],zero,xmm4[5],zero,xmm4[6],zero,xmm4[7],zero
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4 ; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm4 ; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm4
; AVX1-NEXT: vpackuswb %xmm5, %xmm4, %xmm4 ; AVX1-NEXT: vpackuswb %xmm5, %xmm4, %xmm4
; AVX1-NEXT: vpsubb %xmm4, %xmm3, %xmm3 ; AVX1-NEXT: vpsubb %xmm4, %xmm3, %xmm3
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm5
; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5 ; AVX1-NEXT: vpsllw $7, %xmm5, %xmm5
; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5,6],xmm5[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,5,6],xmm5[7]
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4 ; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm4, %xmm4
; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4 ; AVX1-NEXT: vpsrlw $8, %xmm4, %xmm4
; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm6 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm6 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX1-NEXT: vpsllw $7, %xmm6, %xmm6 ; AVX1-NEXT: vpsllw $7, %xmm6, %xmm6
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llvm/test/CodeGen/X86/vector-reduce-and-bool.ll

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; SSE41-NEXT: pmovmskb %xmm0, %eax ; SSE41-NEXT: pmovmskb %xmm0, %eax
; SSE41-NEXT: cmpb $-1, %al ; SSE41-NEXT: cmpb $-1, %al
; SSE41-NEXT: sete %al ; SSE41-NEXT: sete %al
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: trunc_v8i32_v8i1: ; AVX1-LABEL: trunc_v8i32_v8i1:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: vpmovmskb %xmm0, %eax
; AVX1-NEXT: cmpb $-1, %al ; AVX1-NEXT: cmpb $-1, %al
; AVX1-NEXT: sete %al ; AVX1-NEXT: sete %al
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
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llvm/test/CodeGen/X86/vector-reduce-mul.ll

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; AVX1-NEXT: # kill: def $al killed $al killed $eax ; AVX1-NEXT: # kill: def $al killed $al killed $eax
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: test_v16i8: ; AVX2-LABEL: test_v16i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[2],zero,xmm0[2],zero,xmm0[4],zero,xmm0[6],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero ; AVX2-NEXT: vpshuflw {{.*#+}} xmm1 = xmm0[1,1,2,3,4,5,6,7]
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpextrb $0, %xmm0, %eax ; AVX2-NEXT: vpextrb $0, %xmm0, %eax
; AVX2-NEXT: # kill: def $al killed $al killed $eax ; AVX2-NEXT: # kill: def $al killed $al killed $eax
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512BW-LABEL: test_v16i8: ; AVX512BW-LABEL: test_v16i8:
; AVX512BW: # %bb.0: ; AVX512BW: # %bb.0:
; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] ; AVX512BW-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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llvm/test/CodeGen/X86/vector-reduce-or-bool.ll

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; SSE41-NEXT: pmovmskb %xmm0, %eax ; SSE41-NEXT: pmovmskb %xmm0, %eax
; SSE41-NEXT: testb %al, %al ; SSE41-NEXT: testb %al, %al
; SSE41-NEXT: setne %al ; SSE41-NEXT: setne %al
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: trunc_v8i32_v8i1: ; AVX1-LABEL: trunc_v8i32_v8i1:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: vpmovmskb %xmm0, %eax
; AVX1-NEXT: testb %al, %al ; AVX1-NEXT: testb %al, %al
; AVX1-NEXT: setne %al ; AVX1-NEXT: setne %al
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
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llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll

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; SSE41-NEXT: pmovmskb %xmm0, %eax ; SSE41-NEXT: pmovmskb %xmm0, %eax
; SSE41-NEXT: xorb $0, %al ; SSE41-NEXT: xorb $0, %al
; SSE41-NEXT: setnp %al ; SSE41-NEXT: setnp %al
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: trunc_v8i32_v8i1: ; AVX1-LABEL: trunc_v8i32_v8i1:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0
; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 ; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: vpmovmskb %xmm0, %eax
; AVX1-NEXT: xorb $0, %al ; AVX1-NEXT: xorb $0, %al
; AVX1-NEXT: setnp %al ; AVX1-NEXT: setnp %al
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
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llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll

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; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <16 x i8> %a, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> %shuffle = shufflevector <16 x i8> %a, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
ret <16 x i8> %shuffle ret <16 x i8> %shuffle
} }
define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06(<16 x i8> %a) { define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06(<16 x i8> %a) {
; SSE-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06: ; SSE-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero ; SSE-NEXT: psrlq $8, %xmm0
; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5] ; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06: ; AVX1-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero ; AVX1-NEXT: vpsrlq $8, %xmm0, %xmm0
; AVX1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5] ; AVX1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06: ; AVX2-SLOW-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero ; AVX2-SLOW-NEXT: vpsrlq $8, %xmm0, %xmm0
; AVX2-SLOW-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5] ; AVX2-SLOW-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5]
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06: ; AVX2-FAST-LABEL: shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[1,2,3,4,5,6] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[1,2,3,4,5,6]
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
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} }
define <16 x i8> @PR31301(i8* nocapture readonly %x, i8* nocapture readonly %y) { define <16 x i8> @PR31301(i8* nocapture readonly %x, i8* nocapture readonly %y) {
; SSE2-LABEL: PR31301: ; SSE2-LABEL: PR31301:
; SSE2: # %bb.0: # %entry ; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movzbl (%rdi), %eax ; SSE2-NEXT: movzbl (%rdi), %eax
; SSE2-NEXT: movd %eax, %xmm0 ; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,3,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE2-NEXT: movzbl (%rsi), %eax ; SSE2-NEXT: movzbl (%rsi), %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,2,3,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: PR31301: ; SSSE3-LABEL: PR31301:
; SSSE3: # %bb.0: # %entry ; SSSE3: # %bb.0: # %entry
; SSSE3-NEXT: movzbl (%rdi), %eax ; SSSE3-NEXT: movzbl (%rdi), %eax
; SSSE3-NEXT: movd %eax, %xmm0 ; SSSE3-NEXT: movd %eax, %xmm0
; SSSE3-NEXT: pxor %xmm1, %xmm1 ; SSSE3-NEXT: pxor %xmm1, %xmm1
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llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3> %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
define <4 x i32> @shuffle_v4i32_0124(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @shuffle_v4i32_0124(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: shuffle_v4i32_0124: ; SSE2-LABEL: shuffle_v4i32_0124:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4i32_0124: ; SSE3-LABEL: shuffle_v4i32_0124:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4i32_0124: ; SSSE3-LABEL: shuffle_v4i32_0124:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4i32_0124: ; SSE41-LABEL: shuffle_v4i32_0124:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1OR2-LABEL: shuffle_v4i32_0124: ; AVX1-LABEL: shuffle_v4i32_0124:
; AVX1OR2: # %bb.0: ; AVX1: # %bb.0:
; AVX1OR2-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,2,0] ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,2,0]
; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3] ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
; AVX1OR2-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: shuffle_v4i32_0124:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v4i32_0124: ; AVX512VL-LABEL: shuffle_v4i32_0124:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,4] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,4]
; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4> %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
ret <4 x i32> %shuffle ret <4 x i32> %shuffle
} }
define <4 x i32> @shuffle_v4i32_0142(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @shuffle_v4i32_0142(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: shuffle_v4i32_0142: ; SSE2-LABEL: shuffle_v4i32_0142:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4i32_0142: ; SSE3-LABEL: shuffle_v4i32_0142:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4i32_0142: ; SSSE3-LABEL: shuffle_v4i32_0142:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4i32_0142: ; SSE41-LABEL: shuffle_v4i32_0142:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
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; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2> %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 2>
ret <4 x i32> %shuffle ret <4 x i32> %shuffle
} }
define <4 x i32> @shuffle_v4i32_0412(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @shuffle_v4i32_0412(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: shuffle_v4i32_0412: ; SSE2-LABEL: shuffle_v4i32_0412:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4i32_0412: ; SSE3-LABEL: shuffle_v4i32_0412:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2] ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
; SSE3-NEXT: movaps %xmm1, %xmm0 ; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4i32_0412: ; SSSE3-LABEL: shuffle_v4i32_0412:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[1,2]
; SSSE3-NEXT: movaps %xmm1, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4i32_0412: ; SSE41-LABEL: shuffle_v4i32_0412:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,2] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,2]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1OR2-LABEL: shuffle_v4i32_0412: ; AVX1-LABEL: shuffle_v4i32_0412:
; AVX1OR2: # %bb.0: ; AVX1: # %bb.0:
; AVX1OR2-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,1,1] ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,1,1]
; AVX1OR2-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,2] ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,2]
; AVX1OR2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
; AVX1OR2-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: shuffle_v4i32_0412:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
; AVX2-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,1,2]
; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v4i32_0412: ; AVX512VL-LABEL: shuffle_v4i32_0412:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [0,4,1,2] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [0,4,1,2]
; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0 ; AVX512VL-NEXT: vpermt2d %xmm1, %xmm2, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2> %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 2>
ret <4 x i32> %shuffle ret <4 x i32> %shuffle
} }
define <4 x i32> @shuffle_v4i32_4012(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @shuffle_v4i32_4012(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: shuffle_v4i32_4012: ; SSE2-LABEL: shuffle_v4i32_4012:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4i32_4012: ; SSE3-LABEL: shuffle_v4i32_4012:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2] ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
; SSE3-NEXT: movaps %xmm1, %xmm0 ; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4i32_4012: ; SSSE3-LABEL: shuffle_v4i32_4012:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[0,0] ; SSSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,2]
; SSSE3-NEXT: movaps %xmm1, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4i32_4012: ; SSE41-LABEL: shuffle_v4i32_4012:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,2] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,2]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3> %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) { define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
; SSE2-LABEL: shuffle_v4f32_z4zz: ; SSE2-LABEL: shuffle_v4f32_z4zz:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4f32_z4zz: ; SSE3-LABEL: shuffle_v4f32_z4zz:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE3-NEXT: xorps %xmm1, %xmm1 ; SSE3-NEXT: xorps %xmm1, %xmm1
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4f32_z4zz: ; SSSE3-LABEL: shuffle_v4f32_z4zz:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSSE3-NEXT: xorps %xmm1, %xmm1 ; SSSE3-NEXT: xorps %xmm1, %xmm1
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4f32_z4zz: ; SSE41-LABEL: shuffle_v4f32_z4zz:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero ; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: shuffle_v4f32_z4zz: ; AVX-LABEL: shuffle_v4f32_z4zz:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0> %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) { define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
; SSE2-LABEL: shuffle_v4f32_zz4z: ; SSE2-LABEL: shuffle_v4f32_zz4z:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: movq {{.*#+}} xmm1 = xmm0[0],zero
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4f32_zz4z: ; SSE3-LABEL: shuffle_v4f32_zz4z:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: xorps %xmm1, %xmm1 ; SSE3-NEXT: movq {{.*#+}} xmm1 = xmm0[0],zero
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSE3-NEXT: pxor %xmm0, %xmm0
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4f32_zz4z: ; SSSE3-LABEL: shuffle_v4f32_zz4z:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: xorps %xmm1, %xmm1 ; SSSE3-NEXT: movq {{.*#+}} xmm1 = xmm0[0],zero
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0] ; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4f32_zz4z: ; SSE41-LABEL: shuffle_v4f32_zz4z:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,xmm0[0],zero ; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,zero,xmm0[0],zero
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: shuffle_v4f32_zz4z: ; AVX-LABEL: shuffle_v4f32_zz4z:
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 7> %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) { define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
; SSE2-LABEL: shuffle_v4f32_z6zz: ; SSE2-LABEL: shuffle_v4f32_z6zz:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0] ; SSE2-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4f32_z6zz: ; SSE3-LABEL: shuffle_v4f32_z6zz:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: xorps %xmm1, %xmm1 ; SSE3-NEXT: xorps %xmm1, %xmm1
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0] ; SSE3-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4f32_z6zz: ; SSSE3-LABEL: shuffle_v4f32_z6zz:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: xorps %xmm1, %xmm1 ; SSSE3-NEXT: xorps %xmm1, %xmm1
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0] ; SSSE3-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4f32_z6zz: ; SSE41-LABEL: shuffle_v4f32_z6zz:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero ; SSE41-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: shuffle_v4f32_z6zz: ; AVX-LABEL: shuffle_v4f32_z6zz:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = zero,xmm0[2],zero,zero
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3> %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
define <4 x float> @shuffle_v4f32_0z23(<4 x float> %a) { define <4 x float> @shuffle_v4f32_0z23(<4 x float> %a) {
; SSE2-LABEL: shuffle_v4f32_0z23: ; SSE2-LABEL: shuffle_v4f32_0z23:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4f32_0z23: ; SSE3-LABEL: shuffle_v4f32_0z23:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: xorps %xmm1, %xmm1 ; SSE3-NEXT: xorps %xmm1, %xmm1
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0] ; SSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
; SSE3-NEXT: movaps %xmm1, %xmm0 ; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4f32_0z23: ; SSSE3-LABEL: shuffle_v4f32_0z23:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: xorps %xmm1, %xmm1 ; SSSE3-NEXT: xorps %xmm1, %xmm1
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0] ; SSSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
; SSSE3-NEXT: movaps %xmm1, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4f32_0z23: ; SSE41-LABEL: shuffle_v4f32_0z23:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: xorps %xmm1, %xmm1 ; SSE41-NEXT: xorps %xmm1, %xmm1
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 undef, i32 0, i32 5, i32 1> %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 undef, i32 0, i32 5, i32 1>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %a, <4 x float> %b) { define <4 x float> @shuffle_v4f32_0zz4(<4 x float> %a, <4 x float> %b) {
; SSE2-LABEL: shuffle_v4f32_0zz4: ; SSE2-LABEL: shuffle_v4f32_0zz4:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: movq {{.*#+}} xmm2 = xmm1[0],zero
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm2[2,0] ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4f32_0zz4: ; SSE3-LABEL: shuffle_v4f32_0zz4:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: xorps %xmm2, %xmm2 ; SSE3-NEXT: movq {{.*#+}} xmm2 = xmm1[0],zero
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm2[2,0] ; SSE3-NEXT: pxor %xmm1, %xmm1
; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0] ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
; SSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSE3-NEXT: movaps %xmm2, %xmm0 ; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4f32_0zz4: ; SSSE3-LABEL: shuffle_v4f32_0zz4:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: xorps %xmm2, %xmm2 ; SSSE3-NEXT: movq {{.*#+}} xmm2 = xmm1[0],zero
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm2[2,0] ; SSSE3-NEXT: pxor %xmm1, %xmm1
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; SSSE3-NEXT: movaps %xmm2, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4f32_0zz4: ; SSE41-LABEL: shuffle_v4f32_0zz4:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,zero,xmm1[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: shuffle_v4f32_0zz4: ; AVX-LABEL: shuffle_v4f32_0zz4:
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 undef, i32 undef, i32 6> %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 undef, i32 undef, i32 6>
%shuffle1 = shufflevector <4 x float> zeroinitializer, <4 x float> %shuffle, <4 x i32> <i32 4, i32 1, i32 2, i32 7> %shuffle1 = shufflevector <4 x float> zeroinitializer, <4 x float> %shuffle, <4 x i32> <i32 4, i32 1, i32 2, i32 7>
ret <4 x float> %shuffle1 ret <4 x float> %shuffle1
} }
define <4 x float> @shuffle_v4f32_0z24(<4 x float> %a, <4 x float> %b) { define <4 x float> @shuffle_v4f32_0z24(<4 x float> %a, <4 x float> %b) {
; SSE2-LABEL: shuffle_v4f32_0z24: ; SSE2-LABEL: shuffle_v4f32_0z24:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE2-NEXT: xorps %xmm2, %xmm2 ; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
; SSE2-NEXT: movaps %xmm2, %xmm0 ; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4f32_0z24: ; SSE3-LABEL: shuffle_v4f32_0z24:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE3-NEXT: xorps %xmm2, %xmm2 ; SSE3-NEXT: xorps %xmm2, %xmm2
; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0] ; SSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0] ; SSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
; SSE3-NEXT: movaps %xmm2, %xmm0 ; SSE3-NEXT: movaps %xmm2, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4f32_0z24: ; SSSE3-LABEL: shuffle_v4f32_0z24:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSSE3-NEXT: xorps %xmm2, %xmm2 ; SSSE3-NEXT: xorps %xmm2, %xmm2
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[0,0] ; SSSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[2,0]
; SSSE3-NEXT: movaps %xmm2, %xmm0 ; SSSE3-NEXT: movaps %xmm2, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4f32_0z24: ; SSE41-LABEL: shuffle_v4f32_0z24:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[2],xmm1[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4> %shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
ret <4 x i32> %shuffle ret <4 x i32> %shuffle
} }
define <4 x i32> @shuffle_v4i32_z6zz(<4 x i32> %a) { define <4 x i32> @shuffle_v4i32_z6zz(<4 x i32> %a) {
; SSE2-LABEL: shuffle_v4i32_z6zz: ; SSE2-LABEL: shuffle_v4i32_z6zz:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4i32_z6zz: ; SSE3-LABEL: shuffle_v4i32_z6zz:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
; SSE3-NEXT: xorps %xmm1, %xmm1 ; SSE3-NEXT: xorps %xmm1, %xmm1
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0]
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4i32_z6zz: ; SSSE3-LABEL: shuffle_v4i32_z6zz:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: psrldq {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero
; SSSE3-NEXT: xorps %xmm1, %xmm1 ; SSSE3-NEXT: xorps %xmm1, %xmm1
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0]
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v4i32_z6zz: ; SSE41-LABEL: shuffle_v4i32_z6zz:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
; SSE41-NEXT: pxor %xmm0, %xmm0 ; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5> %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
ret <4 x i32> %shuffle ret <4 x i32> %shuffle
} }
; PR22391 ; PR22391
define <4 x i32> @shuffle_v4i32_2456(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @shuffle_v4i32_2456(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: shuffle_v4i32_2456: ; SSE2-LABEL: shuffle_v4i32_2456:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3],xmm1[0,1]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: shuffle_v4i32_2456: ; SSE3-LABEL: shuffle_v4i32_2456:
; SSE3: # %bb.0: ; SSE3: # %bb.0:
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3],xmm1[0,1]
; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2] ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,2]
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v4i32_2456: ; SSSE3-LABEL: shuffle_v4i32_2456:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2] ; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,2]
; SSSE3-NEXT: palignr {{.*#+}} xmm1 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11] ; SSSE3-NEXT: palignr {{.*#+}} xmm1 = xmm0[12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10,11]
; SSSE3-NEXT: movdqa %xmm1, %xmm0 ; SSSE3-NEXT: movdqa %xmm1, %xmm0
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llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll

Show First 20 Lines • Show All 1,255 Lines • ▼ Show 20 Lines; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 4, i32 3, i32 10, i32 undef, i32 undef, i32 undef, i32 undef> %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 4, i32 3, i32 10, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %shuffle ret <8 x i16> %shuffle
} }
define <8 x i16> @shuffle_v8i16_032dXXXX(<8 x i16> %a, <8 x i16> %b) { define <8 x i16> @shuffle_v8i16_032dXXXX(<8 x i16> %a, <8 x i16> %b) {
; SSE2-LABEL: shuffle_v8i16_032dXXXX: ; SSE2-LABEL: shuffle_v8i16_032dXXXX:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1,2,0]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,6,7] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_v8i16_032dXXXX: ; SSSE3-LABEL: shuffle_v8i16_032dXXXX:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[10,11,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[10,11,u,u,u,u,u,u,u,u]
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; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,0] ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,0]
; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7] ; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
; AVX1-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7] ; AVX1-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: shuffle_v8i16_XXX1X579: ; AVX2-SLOW-LABEL: shuffle_v8i16_XXX1X579:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,0] ; AVX2-SLOW-NEXT: vpbroadcastd %xmm1, %xmm1
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7] ; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,1,2,1,4,5,6,7]
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7] ; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,7,7]
; AVX2-SLOW-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7] ; AVX2-SLOW-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: shuffle_v8i16_XXX1X579: ; AVX2-FAST-LABEL: shuffle_v8i16_XXX1X579:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,0] ; AVX2-FAST-NEXT: vpbroadcastd %xmm1, %xmm1
; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,2,3,8,9,10,11,14,15,14,15] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,2,3,8,9,10,11,14,15,14,15]
; AVX2-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7] ; AVX2-FAST-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm1[7]
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v8i16_XXX1X579: ; AVX512VL-LABEL: shuffle_v8i16_XXX1X579:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,1,4,5,7,9] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,1,4,5,7,9]
; AVX512VL-NEXT: vpermt2w %xmm1, %xmm2, %xmm0 ; AVX512VL-NEXT: vpermt2w %xmm1, %xmm2, %xmm0
Show All 15 Lines
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,8,9,u,u],zero,zero,zero,zero,zero,zero,xmm0[u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,8,9,u,u],zero,zero,zero,zero,zero,zero,xmm0[u,u]
; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[u,u,u,u],zero,zero,xmm1[u,u,0,1,4,5,8,9,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[u,u,u,u],zero,zero,xmm1[u,u,0,1,4,5,8,9,u,u]
; SSSE3-NEXT: por %xmm1, %xmm0 ; SSSE3-NEXT: por %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_v8i16_XX4X8acX: ; SSE41-LABEL: shuffle_v8i16_XX4X8acX:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5] ; SSE41-NEXT: pshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u,u,u,0,1,4,5,8,9,4,5]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: shuffle_v8i16_XX4X8acX: ; AVX1-LABEL: shuffle_v8i16_XX4X8acX:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u,u,u,0,1,4,5,8,9,4,5]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v8i16_XX4X8acX: ; AVX2-LABEL: shuffle_v8i16_XX4X8acX:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5] ; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u,u,u,0,1,4,5,8,9,4,5]
; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v8i16_XX4X8acX: ; AVX512VL-LABEL: shuffle_v8i16_XX4X8acX:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [4,5,4,5,8,10,12,10] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [4,5,4,5,8,10,12,10]
; AVX512VL-NEXT: vpermt2w %xmm1, %xmm2, %xmm0 ; AVX512VL-NEXT: vpermt2w %xmm1, %xmm2, %xmm0
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ret <8 x i16> %shuffle ret <8 x i16> %shuffle
} }
; PR40306 ; PR40306
define <8 x i16> @shuffle_v8i16_9zzzuuuu(<8 x i16> %x) { define <8 x i16> @shuffle_v8i16_9zzzuuuu(<8 x i16> %x) {
; SSE-LABEL: shuffle_v8i16_9zzzuuuu: ; SSE-LABEL: shuffle_v8i16_9zzzuuuu:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,2,0]
; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: shuffle_v8i16_9zzzuuuu: ; AVX1-LABEL: shuffle_v8i16_9zzzuuuu:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,2,0]
; AVX1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX1-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: shuffle_v8i16_9zzzuuuu: ; AVX2-SLOW-LABEL: shuffle_v8i16_9zzzuuuu:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] ; AVX2-SLOW-NEXT: vpbroadcastd %xmm0, %xmm0
; AVX2-SLOW-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX2-SLOW-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: shuffle_v8i16_9zzzuuuu: ; AVX2-FAST-LABEL: shuffle_v8i16_9zzzuuuu:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512VL-SLOW-LABEL: shuffle_v8i16_9zzzuuuu: ; AVX512VL-SLOW-LABEL: shuffle_v8i16_9zzzuuuu:
; AVX512VL-SLOW: # %bb.0: ; AVX512VL-SLOW: # %bb.0:
; AVX512VL-SLOW-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] ; AVX512VL-SLOW-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3]
; AVX512VL-SLOW-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512VL-SLOW-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512VL-SLOW-NEXT: retq ; AVX512VL-SLOW-NEXT: retq
; ;
; AVX512VL-FAST-LABEL: shuffle_v8i16_9zzzuuuu: ; AVX512VL-FAST-LABEL: shuffle_v8i16_9zzzuuuu:
; AVX512VL-FAST: # %bb.0: ; AVX512VL-FAST: # %bb.0:
; AVX512VL-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; AVX512VL-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; AVX512VL-FAST-NEXT: retq ; AVX512VL-FAST-NEXT: retq
%r = shufflevector <8 x i16> zeroinitializer, <8 x i16> %x, <8 x i32> <i32 9, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %r = shufflevector <8 x i16> zeroinitializer, <8 x i16> %x, <8 x i32> <i32 9, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines; AVX2OR512VL-NEXT: retq
%tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
ret <8 x i16> %tmp3 ret <8 x i16> %tmp3
} }
define <8 x i16> @insert_dup_elt3_mem_v8i16_i32(i32* %ptr) { define <8 x i16> @insert_dup_elt3_mem_v8i16_i32(i32* %ptr) {
; SSE2-LABEL: insert_dup_elt3_mem_v8i16_i32: ; SSE2-LABEL: insert_dup_elt3_mem_v8i16_i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,1,0,1,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,1,2,3,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: insert_dup_elt3_mem_v8i16_i32: ; SSSE3-LABEL: insert_dup_elt3_mem_v8i16_i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
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ret <8 x i16> %tmp4 ret <8 x i16> %tmp4
} }
define <8 x i16> @insert_dup_elt3_mem_v8i16_sext_i16(i16* %ptr) { define <8 x i16> @insert_dup_elt3_mem_v8i16_sext_i16(i16* %ptr) {
; SSE2-LABEL: insert_dup_elt3_mem_v8i16_sext_i16: ; SSE2-LABEL: insert_dup_elt3_mem_v8i16_sext_i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movswl (%rdi), %eax ; SSE2-NEXT: movswl (%rdi), %eax
; SSE2-NEXT: movd %eax, %xmm0 ; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,1,0,1,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,1,2,3,4,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: insert_dup_elt3_mem_v8i16_sext_i16: ; SSSE3-LABEL: insert_dup_elt3_mem_v8i16_sext_i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movswl (%rdi), %eax ; SSSE3-NEXT: movswl (%rdi), %eax
; SSSE3-NEXT: movd %eax, %xmm0 ; SSSE3-NEXT: movd %eax, %xmm0
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,3,2,3,2,3,2,3,2,3,2,3,2,3,2,3]
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llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll

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define <16 x i16> @shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27(<16 x i16> %a, <16 x i16> %b) {
; AVX1-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27: ; AVX1-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7] ; AVX1-NEXT: vpalignr {{.*#+}} xmm2 = xmm2[8,9,10,11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3]
; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u,u,u,0,1,4,5,8,9,14,15]
; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27: ; AVX2-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5] ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27: ; AVX512VL-LABEL: shuffle_v16i16_04_05_06_07_16_17_18_27_12_13_14_15_24_25_26_27:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [4,5,6,7,16,17,18,27,12,13,14,15,24,25,26,27] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [4,5,6,7,16,17,18,27,12,13,14,15,24,25,26,27]
; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0 ; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
▲ Show 20 Lines • Show All 949 Lines • ▼ Show 20 Lines
} }
define <16 x i16> @shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27(<16 x i16> %a, <16 x i16> %b) {
; AVX1-LABEL: shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27: ; AVX1-LABEL: shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3],xmm1[4,5,6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,14,15,8,9,12,13,14,15]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27: ; AVX2-LABEL: shuffle_v16i16_00_16_01_17_02_18_03_27_08_24_09_25_10_26_11_27:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5,6,7,8,9,10],ymm2[11],ymm1[12,13,14,15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5,6,7,8,9,10],ymm2[11],ymm1[12,13,14,15]
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; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,14,15,8,9,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,14,15,14,15,8,9,12,13,14,15]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31: ; AVX2-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,8,9,2,3,10,11,4,5,12,13,6,7,14,15,16,17,24,25,18,19,26,27,20,21,28,29,22,23,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,8,9,2,3,10,11,4,5,12,13,6,7,14,15,16,17,24,25,18,19,26,27,20,21,28,29,22,23,30,31]
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31: ; AVX512VL-LABEL: shuffle_v16i16_00_20_01_21_02_22_03_31_08_28_09_29_10_30_11_31:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,20,1,21,2,22,3,31,8,28,9,29,10,30,11,31] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,20,1,21,2,22,3,31,8,28,9,29,10,30,11,31]
; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0 ; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 20, i32 1, i32 21, i32 2, i32 22, i32 3, i32 31, i32 8, i32 28, i32 9, i32 29, i32 10, i32 30, i32 11, i32 31> %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 20, i32 1, i32 21, i32 2, i32 22, i32 3, i32 31, i32 8, i32 28, i32 9, i32 29, i32 10, i32 30, i32 11, i32 31>
ret <16 x i16> %shuffle ret <16 x i16> %shuffle
} }
define <16 x i16> @shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31(<16 x i16> %a, <16 x i16> %b) {
; AVX1-LABEL: shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31: ; AVX1-LABEL: shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] ; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6],xmm2[7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[4,5,0,1,4,5,4,5,0,1,4,5,8,9,14,15]
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31: ; AVX2-LABEL: shuffle_v16i16_04_20_05_21_06_22_07_31_12_28_13_29_14_30_15_31:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm0 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm2 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm2 = ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15]
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; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[4,5,0,1,4,5,4,5,0,1,4,5,8,9,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[4,5,0,1,4,5,4,5,0,1,4,5,8,9,14,15]
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27: ; AVX2-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5],ymm0[6,7]
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15]
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,9,0,1,10,11,2,3,12,13,4,5,14,15,6,7,24,25,16,17,26,27,18,19,28,29,20,21,30,31,22,23] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,9,0,1,10,11,2,3,12,13,4,5,14,15,6,7,24,25,16,17,26,27,18,19,28,29,20,21,30,31,22,23]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27: ; AVX512VL-LABEL: shuffle_v16i16_04_16_05_17_06_18_07_27_12_24_13_25_14_26_15_27:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [4,16,5,17,6,18,7,27,12,24,13,25,14,26,15,27] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [4,16,5,17,6,18,7,27,12,24,13,25,14,26,15,27]
; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0 ; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
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; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,1,1,3,4,5,6,7,8,9,9,11,12,13,14,15] ; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,1,1,3,4,5,6,7,8,9,9,11,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,6,5,7,7,8,9,10,11,14,13,15,15] ; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,6,5,7,7,8,9,10,11,14,13,15,15]
; AVX2-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] ; AVX2-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: shuffle_v16i16_00_16_01_17_06_22_07_31_08_24_09_25_14_30_15_31: ; AVX2-FAST-LABEL: shuffle_v16i16_00_16_01_17_06_22_07_31_08_24_09_25_14_30_15_31:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3] ; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,0,1,4,5,2,3,8,9,12,13,12,13,14,15,16,17,16,17,20,21,18,19,24,25,28,29,28,29,30,31] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,0,1,4,5,2,3,8,9,12,13,u,u,u,u,16,17,16,17,20,21,18,19,24,25,28,29,u,u,u,u]
; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5,6],ymm2[7] ; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2],ymm2[3],ymm1[4,5,6],ymm2[7]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,2,3,2,3,6,7,12,13,10,11,14,15,14,15,16,17,18,19,18,19,22,23,28,29,26,27,30,31,30,31] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,2,3,2,3,6,7,12,13,10,11,14,15,14,15,16,17,18,19,18,19,22,23,28,29,26,27,30,31,30,31]
; AVX2-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15] ; AVX2-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7],ymm0[8],ymm1[9],ymm0[10],ymm1[11],ymm0[12],ymm1[13],ymm0[14],ymm1[15]
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_00_16_01_17_06_22_07_31_08_24_09_25_14_30_15_31: ; AVX512VL-LABEL: shuffle_v16i16_00_16_01_17_06_22_07_31_08_24_09_25_14_30_15_31:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,16,1,17,6,22,7,31,8,24,9,25,14,30,15,31] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,16,1,17,6,22,7,31,8,24,9,25,14,30,15,31]
; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0 ; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 6, i32 22, i32 7, i32 31, i32 8, i32 24, i32 9, i32 25, i32 14, i32 30, i32 15, i32 31> %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 6, i32 22, i32 7, i32 31, i32 8, i32 24, i32 9, i32 25, i32 14, i32 30, i32 15, i32 31>
ret <16 x i16> %shuffle ret <16 x i16> %shuffle
} }
define <16 x i16> @shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25(<16 x i16> %a, <16 x i16> %b) {
; AVX1-LABEL: shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25: ; AVX1-LABEL: shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,0,2,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,0,2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,3,2,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,3,2,3]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3,4,5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3,4,5,6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[8,9,10,11,0,1,2,3,2,3,0,1,12,13,2,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,0,2,3]
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,3,2,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,3,2,3]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25: ; AVX2-SLOW-LABEL: shuffle_v16i16_00_20_01_21_06_16_07_25_08_28_09_29_14_24_15_25:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3] ; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3]
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; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] ; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5]
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: shuffle_v16i16_01_00_17_16_03_02_19_26_09_08_25_24_11_10_27_26: ; AVX2-FAST-LABEL: shuffle_v16i16_01_00_17_16_03_02_19_26_09_08_25_24_11_10_27_26:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3] ; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm1[2,3,2,3]
; AVX2-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm2[2],ymm1[3,4,5,6,7,8,9],ymm2[10],ymm1[11,12,13,14,15] ; AVX2-FAST-NEXT: vpblendw {{.*#+}} ymm1 = ymm1[0,1],ymm2[2],ymm1[3,4,5,6,7,8,9],ymm2[10],ymm1[11,12,13,14,15]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[2,3,0,1,2,3,0,1,8,9,10,11,6,7,4,5,18,19,16,17,18,19,16,17,24,25,26,27,22,23,20,21] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[2,3,0,1,2,3,0,1,8,9,10,11,6,7,4,5,18,19,16,17,18,19,16,17,24,25,26,27,22,23,20,21]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5,6,7,4,5,12,13,14,15,18,19,16,17,22,23,20,21,22,23,20,21,28,29,30,31] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,0,1,u,u,u,u,6,7,4,5,u,u,u,u,18,19,16,17,u,u,u,u,22,23,20,21,u,u,u,u]
; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_01_00_17_16_03_02_19_26_09_08_25_24_11_10_27_26: ; AVX512VL-LABEL: shuffle_v16i16_01_00_17_16_03_02_19_26_09_08_25_24_11_10_27_26:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [1,0,17,16,3,2,19,26,9,8,25,24,11,10,27,26] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [1,0,17,16,3,2,19,26,9,8,25,24,11,10,27,26]
; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0 ; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 1, i32 0, i32 17, i32 16, i32 3, i32 2, i32 19, i32 26, i32 9, i32 8, i32 25, i32 24, i32 11, i32 10, i32 27, i32 26> %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 1, i32 0, i32 17, i32 16, i32 3, i32 2, i32 19, i32 26, i32 9, i32 8, i32 25, i32 24, i32 11, i32 10, i32 27, i32 26>
ret <16 x i16> %shuffle ret <16 x i16> %shuffle
} }
define <16 x i16> @shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11(<16 x i16> %a, <16 x i16> %b) {
; AVX1-LABEL: shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11: ; AVX1-LABEL: shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3],xmm0[4,5,6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,14,15,14,15,8,9,12,13,14,15]
; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11: ; AVX2-LABEL: shuffle_v16i16_16_00_17_01_18_02_19_11_24_08_25_09_26_10_27_11:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm0[2,3,2,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm0[2,3,2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm2[3],ymm0[4,5,6,7,8,9,10],ymm2[11],ymm0[12,13,14,15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm2[3],ymm0[4,5,6,7,8,9,10],ymm2[11],ymm0[12,13,14,15]
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} }
define <16 x i16> @shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15(<16 x i16> %a, <16 x i16> %b) {
; AVX1-LABEL: shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15: ; AVX1-LABEL: shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] ; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6],xmm2[7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,4,5,4,5,0,1,4,5,8,9,14,15]
; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15: ; AVX2-LABEL: shuffle_v16i16_20_04_21_05_22_06_23_15_28_12_29_13_30_14_31_15:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm1 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm1 = ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15]
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm2 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15] ; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm2 = ymm0[4,4,5,5,6,6,7,7,12,12,13,13,14,14,15,15]
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; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,1,3,4,5,6,7] ; AVX1-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[0,2,1,3,4,5,6,7]
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31: ; AVX2-SLOW-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] ; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15] ; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm0 = ymm0[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15] ; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15]
; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3]
; AVX2-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15] ; AVX2-SLOW-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31: ; AVX2-FAST-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] ; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,2,3,6,7,8,9,12,13,10,11,14,15,16,17,20,21,18,19,22,23,24,25,28,29,26,27,30,31] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,2,3,6,7,8,9,12,13,10,11,14,15,16,17,20,21,18,19,22,23,24,25,28,29,26,27,30,31]
; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm1 = ymm1[2,3,2,3]
; AVX2-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15] ; AVX2-FAST-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,6],ymm1[7],ymm0[8,9,10,11,12,13,14],ymm1[15]
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31: ; AVX512VL-LABEL: shuffle_v16i16_00_02_01_03_20_22_21_31_08_10_09_11_28_30_29_31:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,1,3,20,22,21,31,8,10,9,11,28,30,29,31] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,1,3,20,22,21,31,8,10,9,11,28,30,29,31]
; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0 ; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11: ; AVX2-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm0[2,3,2,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[2,3,2,3]
; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0,1,2],ymm1[3],ymm0[4,5,6,7,8,9,10],ymm1[11],ymm0[12,13,14,15] ; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6,7,8,9,10],ymm0[11],ymm1[12,13,14,15]
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7,16,17,18,19,20,21,26,27,24,25,26,27,28,29,22,23] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5,10,11,8,9,10,11,12,13,6,7,16,17,18,19,20,21,26,27,24,25,26,27,28,29,22,23]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11: ; AVX512VL-LABEL: shuffle_v16i16_00_01_02_21_20_21_22_11_08_09_10_29_28_29_30_11:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,21,20,21,22,11,8,9,10,29,28,29,30,11] ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,2,21,20,21,22,11,8,9,10,29,28,29,30,11]
; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0 ; AVX512VL-NEXT: vpermt2w %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines; AVX512VL-NEXT: retq
%shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 5, i32 7, i32 25, i32 undef, i32 undef, i32 undef, i32 9, i32 undef, i32 13, i32 15, i32 25> %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 5, i32 7, i32 25, i32 undef, i32 undef, i32 undef, i32 9, i32 undef, i32 13, i32 15, i32 25>
ret <16 x i16> %shuffle ret <16 x i16> %shuffle
} }
define <16 x i16> @shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu(<16 x i16> %a, <16 x i16> %b) { define <16 x i16> @shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu(<16 x i16> %a, <16 x i16> %b) {
; AVX1-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu: ; AVX1-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5] ; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5]
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3]
; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[2,2,3,3] ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0,1,2,3],xmm2[4,5,6,7] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[u,u,u,u,u,u,u,u,0,1,4,5,8,9,4,5]
; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu: ; AVX2-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,4,5,16,17,20,21,20,21,22,23,16,17,20,21,24,25,20,21] ; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[u,u,u,u,u,u,u,u,0,1,4,5,8,9,4,5,u,u,u,u,u,u,u,u,16,17,20,21,24,25,20,21]
; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7] ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512VL-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu: ; AVX512VL-LABEL: shuffle_v16i16_uu_uu_04_uu_16_18_20_uu_uu_uu_12_uu_24_26_28_uu:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = <u,u,20,u,0,2,4,u,u,u,28,u,8,10,12,u> ; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = <u,u,20,u,0,2,4,u,u,u,28,u,8,10,12,u>
; AVX512VL-NEXT: vpermi2w %ymm0, %ymm1, %ymm2 ; AVX512VL-NEXT: vpermi2w %ymm0, %ymm1, %ymm2
▲ Show 20 Lines • Show All 943 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines; AVX512VL-FAST-NEXT: retq
ret <8 x float> %shuffle ret <8 x float> %shuffle
} }
define <8 x float> @shuffle_v8f32_00040000(<8 x float> %a, <8 x float> %b) { define <8 x float> @shuffle_v8f32_00040000(<8 x float> %a, <8 x float> %b) {
; AVX1-LABEL: shuffle_v8f32_00040000: ; AVX1-LABEL: shuffle_v8f32_00040000:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[0,1,0,1] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[0,1,0,1]
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4] ; AVX1-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,0],ymm0[2,0],ymm1[4,4],ymm0[6,4] ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,0],ymm0[2,0],ymm1[4,4],ymm0[6,4]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v8f32_00040000: ; AVX2OR512VL-LABEL: shuffle_v8f32_00040000:
; AVX2OR512VL: # %bb.0: ; AVX2OR512VL: # %bb.0:
; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,4,0,0,0,0] ; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,4,0,0,0,0]
; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
▲ Show 20 Lines • Show All 222 Lines • ▼ Show 20 Lines
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
ret <8 x float> %shuffle ret <8 x float> %shuffle
} }
define <8 x float> @shuffle_v8f32_08991abb(<8 x float> %a, <8 x float> %b) { define <8 x float> @shuffle_v8f32_08991abb(<8 x float> %a, <8 x float> %b) {
; AVX1-LABEL: shuffle_v8f32_08991abb: ; AVX1-LABEL: shuffle_v8f32_08991abb:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm2 = xmm0[0],xmm1[0]
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1] ; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: shuffle_v8f32_08991abb: ; AVX2-SLOW-LABEL: shuffle_v8f32_08991abb:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
▲ Show 20 Lines • Show All 1,067 Lines • ▼ Show 20 Lines; AVX512VL-FAST-NEXT: retq
ret <8 x i32> %shuffle ret <8 x i32> %shuffle
} }
define <8 x i32> @shuffle_v8i32_00040000(<8 x i32> %a, <8 x i32> %b) { define <8 x i32> @shuffle_v8i32_00040000(<8 x i32> %a, <8 x i32> %b) {
; AVX1-LABEL: shuffle_v8i32_00040000: ; AVX1-LABEL: shuffle_v8i32_00040000:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[0,1,0,1] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm0[0,1,0,1]
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,0],ymm1[0,0],ymm0[4,4],ymm1[4,4] ; AVX1-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,0],ymm0[2,0],ymm1[4,4],ymm0[6,4] ; AVX1-NEXT: vshufps {{.*#+}} ymm0 = ymm1[0,0],ymm0[2,0],ymm1[4,4],ymm0[6,4]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2OR512VL-LABEL: shuffle_v8i32_00040000: ; AVX2OR512VL-LABEL: shuffle_v8i32_00040000:
; AVX2OR512VL: # %bb.0: ; AVX2OR512VL: # %bb.0:
; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,4,0,0,0,0] ; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = [0,0,0,4,0,0,0,0]
; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2OR512VL-NEXT: retq ; AVX2OR512VL-NEXT: retq
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
ret <8 x i32> %shuffle ret <8 x i32> %shuffle
} }
define <8 x i32> @shuffle_v8i32_08991abb(<8 x i32> %a, <8 x i32> %b) { define <8 x i32> @shuffle_v8i32_08991abb(<8 x i32> %a, <8 x i32> %b) {
; AVX1-LABEL: shuffle_v8i32_08991abb: ; AVX1-LABEL: shuffle_v8i32_08991abb:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0],xmm1[0,0] ; AVX1-NEXT: vmovlhps {{.*#+}} xmm2 = xmm0[0],xmm1[0]
; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1] ; AVX1-NEXT: vshufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,1]
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3] ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,2,3,3]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: shuffle_v8i32_08991abb: ; AVX2-SLOW-LABEL: shuffle_v8i32_08991abb:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
Show All 21 Lines
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
%shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11> %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 0, i32 8, i32 9, i32 9, i32 1, i32 10, i32 11, i32 11>
ret <8 x i32> %shuffle ret <8 x i32> %shuffle
} }
define <8 x i32> @shuffle_v8i32_091b2d3f(<8 x i32> %a, <8 x i32> %b) { define <8 x i32> @shuffle_v8i32_091b2d3f(<8 x i32> %a, <8 x i32> %b) {
; AVX1-LABEL: shuffle_v8i32_091b2d3f: ; AVX1-LABEL: shuffle_v8i32_091b2d3f:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[0,1,1,3] ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,1,3,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,3,3]
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: shuffle_v8i32_091b2d3f: ; AVX2-LABEL: shuffle_v8i32_091b2d3f:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
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llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll

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} }
;FIXME: can do better with vpcompress ;FIXME: can do better with vpcompress
define <4 x i32> @test_v16i32_0_1_2_12 (<16 x i32> %v) { define <4 x i32> @test_v16i32_0_1_2_12 (<16 x i32> %v) {
; ALL-LABEL: test_v16i32_0_1_2_12: ; ALL-LABEL: test_v16i32_0_1_2_12:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1 ; ALL-NEXT: vextractf64x4 $1, %zmm0, %ymm1
; ALL-NEXT: vextractf128 $1, %ymm1, %xmm1 ; ALL-NEXT: vextractf128 $1, %ymm1, %xmm1
; ALL-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,2,0] ; ALL-NEXT: vbroadcastss %xmm1, %xmm1
; ALL-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3] ; ALL-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
; ALL-NEXT: vzeroupper ; ALL-NEXT: vzeroupper
; ALL-NEXT: retq ; ALL-NEXT: retq
%res = shufflevector <16 x i32> %v, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 12> %res = shufflevector <16 x i32> %v, <16 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 12>
ret <4 x i32> %res ret <4 x i32> %res
} }
;PR31451 ;PR31451
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llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll

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; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 2, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>) %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> <i8 2, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>)
ret <16 x i8> %1 ret <16 x i8> %1
} }
define i32 @mask_zzz3_v16i8(<16 x i8> %a0) { define i32 @mask_zzz3_v16i8(<16 x i8> %a0) {
; SSSE3-LABEL: mask_zzz3_v16i8: ; SSSE3-LABEL: mask_zzz3_v16i8:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,xmm0[14,u,u,u,u,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: psrldq {{.*#+}} xmm0 = xmm0[11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSSE3-NEXT: movd %xmm0, %eax ; SSSE3-NEXT: movd %xmm0, %eax
; SSSE3-NEXT: andl $-16777216, %eax # imm = 0xFF000000
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: mask_zzz3_v16i8: ; SSE41-LABEL: mask_zzz3_v16i8:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,xmm0[14] ; SSE41-NEXT: psllw $8, %xmm0
; SSE41-NEXT: pextrd $3, %xmm0, %eax ; SSE41-NEXT: pextrd $3, %xmm0, %eax
; SSE41-NEXT: andl $-16777216, %eax # imm = 0xFF000000
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: mask_zzz3_v16i8: ; AVX-LABEL: mask_zzz3_v16i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[u,u,u,u,u,u,u,u,u,u,u,u],zero,zero,zero,xmm0[14] ; AVX-NEXT: vpsllw $8, %xmm0, %xmm0
; AVX-NEXT: vpextrd $3, %xmm0, %eax ; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: andl $-16777216, %eax # imm = 0xFF000000
; AVX-NEXT: retq ; AVX-NEXT: retq
%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i8 12, i8 14, i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i8 12, i8 14>) %1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i8 12, i8 14, i8 0, i8 2, i8 4, i8 6, i8 8, i8 10, i8 12, i8 14>)
%2 = bitcast <16 x i8> %1 to <4 x i32> %2 = bitcast <16 x i8> %1 to <4 x i32>
%3 = extractelement <4 x i32> %2, i32 3 %3 = extractelement <4 x i32> %2, i32 3
%4 = and i32 %3, 4278190080 %4 = and i32 %3, 4278190080
ret i32 %4 ret i32 %4
} }
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llvm/test/CodeGen/X86/vector-shuffle-combining.ll

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; ;
; SSE41-LABEL: combine_nested_undef_test15: ; SSE41-LABEL: combine_nested_undef_test15:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1] ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,0,1]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7] ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: combine_nested_undef_test15: ; AVX1-LABEL: combine_nested_undef_test15:
; AVX: # %bb.0: ; AVX1: # %bb.0:
; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,1,1] ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,1,1]
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,1] ; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,1]
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] ; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
; AVX-NEXT: retq ; AVX1-NEXT: retq
;
; AVX2-LABEL: combine_nested_undef_test15:
; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
; AVX2-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,0,1]
; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
; AVX2-NEXT: retq
%1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1> %1 = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 0, i32 4, i32 3, i32 1>
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3> %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
ret <4 x i32> %2 ret <4 x i32> %2
} }
define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) { define <4 x i32> @combine_nested_undef_test16(<4 x i32> %A, <4 x i32> %B) {
; SSE2-LABEL: combine_nested_undef_test16: ; SSE2-LABEL: combine_nested_undef_test16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
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%c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5> %c = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32><i32 0, i32 4, i32 2, i32 5>
%d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3> %d = shufflevector <4 x float> %a, <4 x float> %c, <4 x i32><i32 4, i32 1, i32 5, i32 3>
ret <4 x float> %d ret <4 x float> %d
} }
define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) { define <4 x float> @combine_insertps4(<4 x float> %a, <4 x float> %b) {
; SSE2-LABEL: combine_insertps4: ; SSE2-LABEL: combine_insertps4:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: combine_insertps4: ; SSSE3-LABEL: combine_insertps4:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0] ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,0]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: combine_insertps4: ; SSE41-LABEL: combine_insertps4:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
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%s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2> %s2 = shufflevector <8 x float> %s1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2>
ret <8 x float> %s2 ret <8 x float> %s2
} }
define <4 x float> @PR30264(<4 x float> %x) { define <4 x float> @PR30264(<4 x float> %x) {
; SSE2-LABEL: PR30264: ; SSE2-LABEL: PR30264:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: xorps %xmm1, %xmm1 ; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0] ; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[2,3]
; SSE2-NEXT: movaps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: PR30264: ; SSSE3-LABEL: PR30264:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: xorps %xmm1, %xmm1 ; SSSE3-NEXT: xorps %xmm1, %xmm1
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0] ; SSSE3-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[2,3] ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],mem[2,3]
; SSSE3-NEXT: movaps %xmm1, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: PR30264: ; SSE41-LABEL: PR30264:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps {{.*#+}} xmm1 = <u,u,4.0E+0,1.0E+0> ; SSE41-NEXT: movaps {{.*#+}} xmm1 = <u,u,4.0E+0,1.0E+0>
; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm0[0],zero,xmm1[2,3] ; SSE41-NEXT: insertps {{.*#+}} xmm1 = xmm0[0],zero,xmm1[2,3]
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llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll

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; SSE41-NEXT: # kill: def $edx killed $edx def $rdx ; SSE41-NEXT: # kill: def $edx killed $edx def $rdx
; SSE41-NEXT: # kill: def $esi killed $esi def $rsi ; SSE41-NEXT: # kill: def $esi killed $esi def $rsi
; SSE41-NEXT: # kill: def $edi killed $edi def $rdi ; SSE41-NEXT: # kill: def $edi killed $edi def $rdi
; SSE41-NEXT: andl $3, %edi ; SSE41-NEXT: andl $3, %edi
; SSE41-NEXT: andl $3, %esi ; SSE41-NEXT: andl $3, %esi
; SSE41-NEXT: andl $3, %edx ; SSE41-NEXT: andl $3, %edx
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE41-NEXT: andl $3, %ecx ; SSE41-NEXT: andl $3, %ecx
; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; SSE41-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; SSE41-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: ; AVX-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: # kill: def $ecx killed $ecx def $rcx ; AVX-NEXT: # kill: def $ecx killed $ecx def $rcx
; AVX-NEXT: # kill: def $edx killed $edx def $rdx ; AVX-NEXT: # kill: def $edx killed $edx def $rdx
; AVX-NEXT: # kill: def $esi killed $esi def $rsi ; AVX-NEXT: # kill: def $esi killed $esi def $rsi
; AVX-NEXT: # kill: def $edi killed $edi def $rdi ; AVX-NEXT: # kill: def $edi killed $edi def $rdi
; AVX-NEXT: andl $3, %edi ; AVX-NEXT: andl $3, %edi
; AVX-NEXT: andl $3, %esi ; AVX-NEXT: andl $3, %esi
; AVX-NEXT: andl $3, %edx ; AVX-NEXT: andl $3, %edx
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: andl $3, %ecx ; AVX-NEXT: andl $3, %ecx
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX-NEXT: retq ; AVX-NEXT: retq
%x0 = extractelement <4 x float> %x, i32 %i0 %x0 = extractelement <4 x float> %x, i32 %i0
%x1 = extractelement <4 x float> %x, i32 %i1 %x1 = extractelement <4 x float> %x, i32 %i1
%x2 = extractelement <4 x float> %x, i32 %i2 %x2 = extractelement <4 x float> %x, i32 %i2
%x3 = extractelement <4 x float> %x, i32 %i3 %x3 = extractelement <4 x float> %x, i32 %i3
%r0 = insertelement <4 x float> undef, float %x0, i32 0 %r0 = insertelement <4 x float> undef, float %x0, i32 0
%r1 = insertelement <4 x float> %r0, float %x1, i32 1 %r1 = insertelement <4 x float> %r0, float %x1, i32 1
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: movzwl -24(%rsp,%r9,2), %eax ; SSE2-NEXT: movzwl -24(%rsp,%r9,2), %eax
; SSE2-NEXT: movd %eax, %xmm1 ; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: movzwl -40(%rsp,%r8,2), %eax ; SSE2-NEXT: movzwl -40(%rsp,%r8,2), %eax
; SSE2-NEXT: movd %eax, %xmm2 ; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: ; SSSE3-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: # kill: def $r9d killed $r9d def $r9 ; SSSE3-NEXT: # kill: def $r9d killed $r9d def $r9
; SSSE3-NEXT: # kill: def $r8d killed $r8d def $r8 ; SSSE3-NEXT: # kill: def $r8d killed $r8d def $r8
; SSSE3-NEXT: # kill: def $ecx killed $ecx def $rcx ; SSSE3-NEXT: # kill: def $ecx killed $ecx def $rcx
; SSSE3-NEXT: # kill: def $edx killed $edx def $rdx ; SSSE3-NEXT: # kill: def $edx killed $edx def $rdx
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-NEXT: movzwl -24(%rsp,%r9,2), %eax ; SSSE3-NEXT: movzwl -24(%rsp,%r9,2), %eax
; SSSE3-NEXT: movd %eax, %xmm1 ; SSSE3-NEXT: movd %eax, %xmm1
; SSSE3-NEXT: movzwl -40(%rsp,%r8,2), %eax ; SSSE3-NEXT: movzwl -40(%rsp,%r8,2), %eax
; SSSE3-NEXT: movd %eax, %xmm2 ; SSSE3-NEXT: movd %eax, %xmm2
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
; SSSE3-NEXT: pxor %xmm1, %xmm1 ; SSSE3-NEXT: pxor %xmm1, %xmm1
; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3]
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: ; SSE41-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: # kill: def $r9d killed $r9d def $r9 ; SSE41-NEXT: # kill: def $r9d killed $r9d def $r9
; SSE41-NEXT: # kill: def $r8d killed $r8d def $r8 ; SSE41-NEXT: # kill: def $r8d killed $r8d def $r8
; SSE41-NEXT: # kill: def $ecx killed $ecx def $rcx ; SSE41-NEXT: # kill: def $ecx killed $ecx def $rcx
; SSE41-NEXT: # kill: def $edx killed $edx def $rdx ; SSE41-NEXT: # kill: def $edx killed $edx def $rdx
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llvm/test/CodeGen/X86/vector-shuffle-variable-256.ll

Show First 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
; ALL-NEXT: andl $7, %edi ; ALL-NEXT: andl $7, %edi
; ALL-NEXT: andl $7, %esi ; ALL-NEXT: andl $7, %esi
; ALL-NEXT: andl $7, %edx ; ALL-NEXT: andl $7, %edx
; ALL-NEXT: andl $7, %ecx ; ALL-NEXT: andl $7, %ecx
; ALL-NEXT: andl $7, %r8d ; ALL-NEXT: andl $7, %r8d
; ALL-NEXT: vmovaps %ymm0, (%rsp) ; ALL-NEXT: vmovaps %ymm0, (%rsp)
; ALL-NEXT: andl $7, %r9d ; ALL-NEXT: andl $7, %r9d
; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; ALL-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; ALL-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; ALL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; ALL-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; ALL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; ALL-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; ALL-NEXT: movq %rbp, %rsp ; ALL-NEXT: movq %rbp, %rsp
; ALL-NEXT: popq %rbp ; ALL-NEXT: popq %rbp
; ALL-NEXT: retq ; ALL-NEXT: retq
%x0 = extractelement <8 x float> %x, i32 %i0 %x0 = extractelement <8 x float> %x, i32 %i0
%x1 = extractelement <8 x float> %x, i32 %i1 %x1 = extractelement <8 x float> %x, i32 %i1
%x2 = extractelement <8 x float> %x, i32 %i2 %x2 = extractelement <8 x float> %x, i32 %i2
Show All 29 Lines
; ALL-NEXT: andl $3, %edi ; ALL-NEXT: andl $3, %edi
; ALL-NEXT: andl $3, %esi ; ALL-NEXT: andl $3, %esi
; ALL-NEXT: andl $3, %edx ; ALL-NEXT: andl $3, %edx
; ALL-NEXT: andl $3, %ecx ; ALL-NEXT: andl $3, %ecx
; ALL-NEXT: andl $3, %r8d ; ALL-NEXT: andl $3, %r8d
; ALL-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; ALL-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; ALL-NEXT: andl $3, %r9d ; ALL-NEXT: andl $3, %r9d
; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; ALL-NEXT: vunpcklps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; ALL-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; ALL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3] ; ALL-NEXT: vunpcklps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; ALL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; ALL-NEXT: vmovlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0] ; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; ALL-NEXT: retq ; ALL-NEXT: retq
%x0 = extractelement <4 x float> %x, i32 %i0 %x0 = extractelement <4 x float> %x, i32 %i0
%x1 = extractelement <4 x float> %x, i32 %i1 %x1 = extractelement <4 x float> %x, i32 %i1
%x2 = extractelement <4 x float> %x, i32 %i2 %x2 = extractelement <4 x float> %x, i32 %i2
%x3 = extractelement <4 x float> %x, i32 %i3 %x3 = extractelement <4 x float> %x, i32 %i3
%x4 = extractelement <4 x float> %x, i32 %i4 %x4 = extractelement <4 x float> %x, i32 %i4
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llvm/test/CodeGen/X86/vector-sqrt.ll

Show All 27 Lines
; Function Attrs: nounwind readonly uwtable ; Function Attrs: nounwind readonly uwtable
define <4 x float> @sqrtf4(float* nocapture readonly %v) local_unnamed_addr #0 { define <4 x float> @sqrtf4(float* nocapture readonly %v) local_unnamed_addr #0 {
; CHECK-LABEL: sqrtf4: ; CHECK-LABEL: sqrtf4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vsqrtss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vsqrtss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3] ; CHECK-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: vsqrtss %xmm1, %xmm1, %xmm1 ; CHECK-NEXT: vsqrtss %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0] ; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = load float, float* %v, align 4 %0 = load float, float* %v, align 4
%call = tail call float @sqrtf(float %0) #2 %call = tail call float @sqrtf(float %0) #2
%arrayidx1 = getelementptr inbounds float, float* %v, i64 1 %arrayidx1 = getelementptr inbounds float, float* %v, i64 1
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llvm/test/CodeGen/X86/vector-trunc-math.ll

Show First 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_add_v8i32_v8i16: ; AVX1-LABEL: trunc_add_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_add_v8i32_v8i16: ; AVX2-LABEL: trunc_add_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
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; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; SSE-NEXT: psraw $8, %xmm0 ; SSE-NEXT: psraw $8, %xmm0
; SSE-NEXT: paddw %xmm1, %xmm0 ; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_add_v8i32_v8i16_sext_8i8: ; AVX1-LABEL: trunc_add_v8i32_v8i16_sext_8i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpmovsxbw %xmm0, %xmm0 ; AVX1-NEXT: vpmovsxbw %xmm0, %xmm0
; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_add_v8i32_v8i16_sext_8i8: ; AVX2-LABEL: trunc_add_v8i32_v8i16_sext_8i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
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; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: paddw {{.*}}(%rip), %xmm0 ; SSE-NEXT: paddw {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_add_const_v8i32_v8i16: ; AVX1-LABEL: trunc_add_const_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_add_const_v8i32_v8i16: ; AVX2-LABEL: trunc_add_const_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
▲ Show 20 Lines • Show All 374 Lines • ▼ Show 20 Lines
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_sub_v8i32_v8i16: ; AVX1-LABEL: trunc_sub_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_sub_v8i32_v8i16: ; AVX2-LABEL: trunc_sub_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
▲ Show 20 Lines • Show All 416 Lines • ▼ Show 20 Lines
; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: psubw {{.*}}(%rip), %xmm0 ; SSE-NEXT: psubw {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_sub_const_v8i32_v8i16: ; AVX1-LABEL: trunc_sub_const_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_sub_const_v8i32_v8i16: ; AVX2-LABEL: trunc_sub_const_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_mul_v8i32_v8i16: ; AVX1-LABEL: trunc_mul_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_mul_v8i32_v8i16: ; AVX2-LABEL: trunc_mul_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
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; SSE-NEXT: psrad $16, %xmm1 ; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: packssdw %xmm2, %xmm1 ; SSE-NEXT: packssdw %xmm2, %xmm1
; SSE-NEXT: pmullw %xmm1, %xmm0 ; SSE-NEXT: pmullw %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_mul_v8i32_v8i16_zext_8i8: ; AVX1-LABEL: trunc_mul_v8i32_v8i16_zext_8i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_mul_v8i32_v8i16_zext_8i8: ; AVX2-LABEL: trunc_mul_v8i32_v8i16_zext_8i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
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; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_mul_const_v8i32_v8i16: ; AVX1-LABEL: trunc_mul_const_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_mul_const_v8i32_v8i16: ; AVX2-LABEL: trunc_mul_const_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_and_v8i32_v8i16: ; AVX1-LABEL: trunc_and_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_and_v8i32_v8i16: ; AVX2-LABEL: trunc_and_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_and_const_v8i32_v8i16: ; AVX1-LABEL: trunc_and_const_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_and_const_v8i32_v8i16: ; AVX2-LABEL: trunc_and_const_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_xor_v8i32_v8i16: ; AVX1-LABEL: trunc_xor_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_xor_v8i32_v8i16: ; AVX2-LABEL: trunc_xor_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: pxor {{.*}}(%rip), %xmm0 ; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_xor_const_v8i32_v8i16: ; AVX1-LABEL: trunc_xor_const_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_xor_const_v8i32_v8i16: ; AVX2-LABEL: trunc_xor_const_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
▲ Show 20 Lines • Show All 364 Lines • ▼ Show 20 Lines
; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_or_v8i32_v8i16: ; AVX1-LABEL: trunc_or_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_or_v8i32_v8i16: ; AVX2-LABEL: trunc_or_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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; SSE-NEXT: psrad $16, %xmm0 ; SSE-NEXT: psrad $16, %xmm0
; SSE-NEXT: packssdw %xmm1, %xmm0 ; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: por {{.*}}(%rip), %xmm0 ; SSE-NEXT: por {{.*}}(%rip), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: trunc_or_const_v8i32_v8i16: ; AVX1-LABEL: trunc_or_const_v8i32_v8i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc_or_const_v8i32_v8i16: ; AVX2-LABEL: trunc_or_const_v8i32_v8i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
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llvm/test/CodeGen/X86/vector-trunc.ll

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2] ; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm2 ; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2] ; AVX2-SLOW-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
; AVX2-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-SLOW-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: trunc8i64_8i32_lshr: ; AVX2-FAST-LABEL: trunc8i64_8i32_lshr:
; AVX2-FAST: # %bb.0: # %entry ; AVX2-FAST: # %bb.0: # %entry
; AVX2-FAST-NEXT: vpsrlq $32, %ymm1, %ymm1 ; AVX2-FAST-NEXT: vmovaps {{.*#+}} xmm2 = [1,3,5,7]
; AVX2-FAST-NEXT: vpsrlq $32, %ymm0, %ymm0 ; AVX2-FAST-NEXT: vpermps %ymm0, %ymm2, %ymm0
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2,4,6,4,6,6,7] ; AVX2-FAST-NEXT: vpermps %ymm1, %ymm2, %ymm1
; AVX2-FAST-NEXT: vpermd %ymm0, %ymm2, %ymm0 ; AVX2-FAST-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-FAST-NEXT: vpermd %ymm1, %ymm2, %ymm1
; AVX2-FAST-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
; ;
; AVX512-LABEL: trunc8i64_8i32_lshr: ; AVX512-LABEL: trunc8i64_8i32_lshr:
; AVX512: # %bb.0: # %entry ; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm0 ; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm0
; AVX512-NEXT: vpmovqd %zmm0, %ymm0 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
entry: entry:
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; SSE41-NEXT: pshufb %xmm2, %xmm1 ; SSE41-NEXT: pshufb %xmm2, %xmm1
; SSE41-NEXT: pshufb %xmm2, %xmm0 ; SSE41-NEXT: pshufb %xmm2, %xmm0
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: trunc8i32_8i16: ; AVX1-LABEL: trunc8i32_8i16:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u]
; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: trunc8i32_8i16: ; AVX2-LABEL: trunc8i32_8i16:
; AVX2: # %bb.0: # %entry ; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
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; SSE41-NEXT: shlq $4, %rdi ; SSE41-NEXT: shlq $4, %rdi
; SSE41-NEXT: movdqu %xmm0, (%rsi,%rdi) ; SSE41-NEXT: movdqu %xmm0, (%rsi,%rdi)
; SSE41-NEXT: movdqu %xmm2, 16(%rsi,%rdi) ; SSE41-NEXT: movdqu %xmm2, 16(%rsi,%rdi)
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: store_merge_split: ; AVX1-LABEL: store_merge_split:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = <0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u>
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; AVX1-NEXT: vpshufb %xmm4, %xmm0, %xmm0
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpshufb %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX1-NEXT: shlq $4, %rdi ; AVX1-NEXT: shlq $4, %rdi
; AVX1-NEXT: vmovdqu %xmm0, (%rsi,%rdi) ; AVX1-NEXT: vmovdqu %xmm0, (%rsi,%rdi)
; AVX1-NEXT: vmovdqu %xmm1, 16(%rsi,%rdi) ; AVX1-NEXT: vmovdqu %xmm1, 16(%rsi,%rdi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: store_merge_split: ; AVX2-LABEL: store_merge_split:
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llvm/test/CodeGen/X86/vector-zext.ll

Show First 20 Lines • Show All 1,748 Lines • ▼ Show 20 Linesentry:
%Z = bitcast <16 x i8> %B to <2 x i64> %Z = bitcast <16 x i8> %B to <2 x i64>
ret <2 x i64> %Z ret <2 x i64> %Z
} }
define <4 x i64> @shuf_zext_16i8_to_4i64_offset11(<16 x i8> %A) nounwind uwtable readnone ssp { define <4 x i64> @shuf_zext_16i8_to_4i64_offset11(<16 x i8> %A) nounwind uwtable readnone ssp {
; SSE2-LABEL: shuf_zext_16i8_to_4i64_offset11: ; SSE2-LABEL: shuf_zext_16i8_to_4i64_offset11:
; SSE2: # %bb.0: # %entry ; SSE2: # %bb.0: # %entry
; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero ; SSE2-NEXT: psrlq $8, %xmm1
; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15] ; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
; SSE2-NEXT: movdqa %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SSE2-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
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llvm/test/CodeGen/X86/vselect.ll

Show First 20 Lines • Show All 563 Lines • ▼ Show 20 Lines
; SSE2-LABEL: simplify_select: ; SSE2-LABEL: simplify_select:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pslld $31, %xmm0 ; SSE2-NEXT: pslld $31, %xmm0
; SSE2-NEXT: psrad $31, %xmm0 ; SSE2-NEXT: psrad $31, %xmm0
; SSE2-NEXT: movd %edi, %xmm1 ; SSE2-NEXT: movd %edi, %xmm1
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,1,1] ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,0,1,1]
; SSE2-NEXT: por %xmm1, %xmm2 ; SSE2-NEXT: por %xmm1, %xmm2
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm2[1,1] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[1,3]
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,3]
; SSE2-NEXT: pand %xmm0, %xmm2 ; SSE2-NEXT: pand %xmm0, %xmm2
; SSE2-NEXT: pandn %xmm1, %xmm0 ; SSE2-NEXT: pandn %xmm1, %xmm0
; SSE2-NEXT: por %xmm2, %xmm0 ; SSE2-NEXT: por %xmm2, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE41-LABEL: simplify_select: ; SSE41-LABEL: simplify_select:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
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llvm/test/CodeGen/X86/vshift-4.ll

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesentry:
store <2 x i64> %shl, <2 x i64>* %dst store <2 x i64> %shl, <2 x i64>* %dst
ret void ret void
} }
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind { define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
; X32-LABEL: shift2a: ; X32-LABEL: shift2a:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] ; X32-NEXT: psrlq $32, %xmm1
; X32-NEXT: xorps %xmm2, %xmm2 ; X32-NEXT: pslld %xmm1, %xmm0
; X32-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X32-NEXT: pslld %xmm2, %xmm0
; X32-NEXT: movdqa %xmm0, (%eax) ; X32-NEXT: movdqa %xmm0, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shift2a: ; X64-LABEL: shift2a:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] ; X64-NEXT: psrlq $32, %xmm1
; X64-NEXT: xorps %xmm2, %xmm2 ; X64-NEXT: pslld %xmm1, %xmm0
; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X64-NEXT: pslld %xmm2, %xmm0
; X64-NEXT: movdqa %xmm0, (%rdi) ; X64-NEXT: movdqa %xmm0, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt %shl = shl <4 x i32> %val, %shamt
store <4 x i32> %shl, <4 x i32>* %dst store <4 x i32> %shl, <4 x i32>* %dst
ret void ret void
} }
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind { define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
; X32-LABEL: shift2b: ; X32-LABEL: shift2b:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] ; X32-NEXT: psrlq $32, %xmm1
; X32-NEXT: xorps %xmm2, %xmm2 ; X32-NEXT: pslld %xmm1, %xmm0
; X32-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X32-NEXT: pslld %xmm2, %xmm0
; X32-NEXT: movdqa %xmm0, (%eax) ; X32-NEXT: movdqa %xmm0, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shift2b: ; X64-LABEL: shift2b:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] ; X64-NEXT: psrlq $32, %xmm1
; X64-NEXT: xorps %xmm2, %xmm2 ; X64-NEXT: pslld %xmm1, %xmm0
; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X64-NEXT: pslld %xmm2, %xmm0
; X64-NEXT: movdqa %xmm0, (%rdi) ; X64-NEXT: movdqa %xmm0, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1> %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt %shl = shl <4 x i32> %val, %shamt
store <4 x i32> %shl, <4 x i32>* %dst store <4 x i32> %shl, <4 x i32>* %dst
ret void ret void
} }
define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind { define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
; X32-LABEL: shift2c: ; X32-LABEL: shift2c:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] ; X32-NEXT: psrlq $32, %xmm1
; X32-NEXT: xorps %xmm2, %xmm2 ; X32-NEXT: pslld %xmm1, %xmm0
; X32-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X32-NEXT: pslld %xmm2, %xmm0
; X32-NEXT: movdqa %xmm0, (%eax) ; X32-NEXT: movdqa %xmm0, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shift2c: ; X64-LABEL: shift2c:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3] ; X64-NEXT: psrlq $32, %xmm1
; X64-NEXT: xorps %xmm2, %xmm2 ; X64-NEXT: pslld %xmm1, %xmm0
; X64-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
; X64-NEXT: pslld %xmm2, %xmm0
; X64-NEXT: movdqa %xmm0, (%rdi) ; X64-NEXT: movdqa %xmm0, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt %shl = shl <4 x i32> %val, %shamt
store <4 x i32> %shl, <4 x i32>* %dst store <4 x i32> %shl, <4 x i32>* %dst
ret void ret void
} }
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind { define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
; X32-LABEL: shift3a: ; X32-LABEL: shift3a:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,1,2,3] ; X32-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6,6]
; X32-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
; X32-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X32-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X32-NEXT: psllw %xmm1, %xmm0 ; X32-NEXT: psllw %xmm1, %xmm0
; X32-NEXT: movdqa %xmm0, (%eax) ; X32-NEXT: movdqa %xmm0, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shift3a: ; X64-LABEL: shift3a:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,1,2,3] ; X64-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5,6,6]
; X64-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
; X64-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X64-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X64-NEXT: psllw %xmm1, %xmm0 ; X64-NEXT: psllw %xmm1, %xmm0
; X64-NEXT: movdqa %xmm0, (%rdi) ; X64-NEXT: movdqa %xmm0, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6> %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
%shl = shl <8 x i16> %val, %shamt %shl = shl <8 x i16> %val, %shamt
store <8 x i16> %shl, <8 x i16>* %dst store <8 x i16> %shl, <8 x i16>* %dst
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