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[RISCV] Support 'f' Inline Assembly Constraint
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Authored by lenary on Jul 31 2019, 12:09 AM.

Details

Summary

This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).

This patch adds support in both the clang frontend, and LLVM itself.

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Repository
rL LLVM

Event Timeline

lenary created this revision.Jul 31 2019, 12:09 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJul 31 2019, 12:09 AM
lenary updated this revision to Diff 212513.Jul 31 2019, 12:15 AM
  • Simplify inline-asm-invalid.ll test
asb accepted this revision.Jul 31 2019, 2:40 AM

LGTM, thanks!

This revision is now accepted and ready to land.Jul 31 2019, 2:40 AM
This revision was automatically updated to reflect the committed changes.