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| Differential D64737
RISCV: Add support for floating point registers in inlineasm ClosedPublic Authored by simoncook on Jul 15 2019, 6:19 AM.
Details Summary This adds support for parsing/emitting in IR the floating-point RISC-V
Diff Detail
Event Timelinesimoncook retitled this revision from [PATCH] RISCV: Add support for floating point registers in inlineasm to RISCV: Add support for floating point registers in inlineasm.Jul 15 2019, 6:19 AM Comment Actions As an aside, I've noticed a codegen issue when using floating point clobber lists, resulting in the implicit-defs not being added to INLINEASM instructions. I'm working on a fix for that now and will submit a second patch shortly. Update: This fix is D64751 simoncook added a child revision: D64751: [RISCV] Add support for lowering floating point inlineasm clobbers.Jul 15 2019, 9:14 AM This revision is now accepted and ready to land.Jul 23 2019, 5:13 AM simoncook removed a child revision: D64751: [RISCV] Add support for lowering floating point inlineasm clobbers.Jul 25 2019, 3:20 AM simoncook added a parent revision: D64751: [RISCV] Add support for lowering floating point inlineasm clobbers. lenary added a child revision: D65500: [RISCV] Support 'f' Inline Assembly Constraint.Jul 31 2019, 12:50 AM Closed by commit rL367399: [RISCV] Add support for floating point registers in inlineasm (authored by simoncook). · Explain WhyJul 31 2019, 2:11 AM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 212540 cfe/trunk/lib/Basic/Targets/RISCV.cpp
cfe/trunk/test/Sema/riscv-asm.c
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