Page MenuHomePhabricator

[RISCV] Add support for lowering floating point inlineasm clobbers
ClosedPublic

Authored by simoncook on Jul 15 2019, 9:12 AM.

Details

Summary

This adds the required extension to RISC-V's getRegForInlineAsmConstraint
in order to be able to correctly distringuish between the 32 and 64-bit
floating point registers when the generic fX name appears in inlineasm
clobber contraints. It also adds a check to validate that callee saved
floating point registers are only saved in this case when a hard-float
ABI is selected.

Diff Detail

Repository
rL LLVM

Event Timeline

simoncook created this revision.Jul 15 2019, 9:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 15 2019, 9:12 AM
lenary accepted this revision.Jul 23 2019, 5:17 AM

Looks good to me! Thank you!

This revision is now accepted and ready to land.Jul 23 2019, 5:17 AM

Thanks for reviewing this @lenary, @asb do you want to take a look at this first, or is a LGTM from Sam sufficient for me to merge?

asb accepted this revision.Jul 31 2019, 12:52 AM

LGTM, thanks!

Getting sufficient LGTMs is a bit of a judgement call with LLVM. If the change is large and invasive, then typically you'd wait for the OK from the relevant code owner. For something like this, totally find for anyone active in that part of the codebase to approve.

This revision was automatically updated to reflect the committed changes.