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RISCV: Add support for floating point registers in inlineasm
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Authored by simoncook on Jul 15 2019, 6:19 AM.

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simoncook created this revision.Jul 15 2019, 6:19 AM
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simoncook retitled this revision from [PATCH] RISCV: Add support for floating point registers in inlineasm to RISCV: Add support for floating point registers in inlineasm.Jul 15 2019, 6:19 AM
simoncook added a comment.EditedJul 15 2019, 6:41 AM

As an aside, I've noticed a codegen issue when using floating point clobber lists, resulting in the implicit-defs not being added to INLINEASM instructions. I'm working on a fix for that now and will submit a second patch shortly.

Update: This fix is D64751

lenary accepted this revision.Jul 23 2019, 5:13 AM

Looks good to me! Thank you!

This revision is now accepted and ready to land.Jul 23 2019, 5:13 AM
This revision was automatically updated to reflect the committed changes.
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