[AIX]Global Address Lowering

[Xiangling_L]

Summary

This patch implements global address lowering for 32/64 bit with small/large code model.

1.For 32bit large code model on AIX, there are newly added pseudo opcode LWZtocL & ADDIStocHA32, the support of which on MC layer will be provided by future patches.

2.The default code model on AIX should be small code model

3.Since AIX does not have medium code model, "report_fatal_error" when users specify it.

[Xiangling_L]

ping.

[stefanp]

I feel like this is supposed to be an AIX only patch.
However, there are some cases where you are making changes to PowerPC platforms that are not AIX. I don't know if those changes are safe.
I'm going to add two people to the review who may be interested in this and who work on 32 Bit PowerPC.

FYI: @jhibbits @joerg

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5069

minor nit:
These three can be const.

5133

Here you may be making changes to 32 bit PowerPC platforms that are not AIX.

5142

Here you may be making changes to 32 bit PowerPC platforms that are not AIX. Previously all PowerPC platforms got this: PPC::LDtocL now the 32 bit ones get PPC::LWZtocL even if that 32 bit platform is not AIX.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2671

You don't need to pass the subtarget into this function.

DAG.getSubtarget()

You already have the DAG so you can get the subtarget that way.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

121

I assume this patch is only meant to affect AIX.
If that is the case I'm afraid that this line might actually change the behaviour of non-AIX PowerPC builds for 32Bit. Should we add an AIX guard to this too?

138

I think it would be better to compute TOCReg in processBlock. That might simplify the change a little.

const bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
const unsigned TOCReg = Is64Bit ? PPC::X2 : PPC::R2;

If you do it this way you don't have to pass in more parameters.

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5133

I think the case "PPCISD::TOC_ENTRY" will only deal with SVR4 ABI [32/64bit] + AIX ABI[32/64bit] + Darwin[64bit] like the assertion implies.

And the only parts that will touch the code from line 5106-5109 were 64bit SVR4, 64bit Darwin previously and are 64bit SVR4, 64bit Darwin plus 32bit AIX now. So It only makes changes to 32bit PowerPC AIX platform.

Maybe I can try to put an assertion here for more clarity?

5142

The same reason as above. It will affect only AIX platform. Besides, I think PPC little endien SVR4 ABI doesn't have 32bit mode, and PPC big endien 32bit have small code model only.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2671

Thanks. I will update this.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

121

Thanks for pointing this out. As my understanding, this file is adding a pass to resolve a r2 dependency issue related to ELF ABI under large code model where we use "toc@ha" and "toc@l" to access the toc entry.

And on PPC under SVR4 ABI, or ELF SVR4 ABI more specifically, little-endien ELF ABI doesn't have 32-bit, and even if big-endien ELF ABI has 32-bit, it doesn't have large code model, which means speaking of ELF ABI on PPC, there is no 32-bit large code model.

So I think my patch will only affect AIX 32bit large code model here.

Feel free to raise your further concerns. And maybe I can add an assertion or change it to (is64Bit? && isAIXABI()) for more clarity purpose?

138

Thanks, I will update this.

[stefanp]

You have convinced me that this will only affect AIX. I only have minor comments remaining.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5133

Good point. I missed that.
I don't think you need an assertion. What you have here is fine.

5142

Ok, fair enough. I think this is fine.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

121

I was not aware that this was only for large code model. Ok, I'm convinced that this patch does not affect anything but AIX.
You could add an assert here because it is not obvious why this is only for AIX 32bit.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5089

Just as a note: GCC on AIX generates large code model relocations for -mcmodel=medium. I guess that should get handled at the driver level.

[Xiangling_L]

Address 1st round comments & add a assertion for AIX

[Xiangling_L]

clean the format mess

[sfertile]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5133

I think there is a lot of implicit understanding baked into this code. There were similar comments in a downstream review before posting to phabricator, and now your comment. My understanding was the same as Xianglings based of the assert, i.e. subtarget could be any of the 64-bit ones (Darwin/ELFV1/ELFV2) or 32-bit ELF.

I dug into this a bit deeper to try to verify my understanding. From what I now understand by looking at where we create TOC_ENTRY in ISELLowering (LowerGlobalAddress/LowerConstantPool/LowerJumpTable/LowerBlockAddress) we only create a TOC entry for

64-bit ELF
32-bit position-independent ELF (-fPIC or -fPIE)

clang accepts -mcmodel=medium/large for 32-bit ELF target but we always produce a small code model TOC access. (the system gcc I'm using produces error: -mcmodel not supported in this configuration when trying to set the code model with -m32).

I think based on the number of people making the same comments, and both me and Xiangling coming up with the same misunderstanding of what targets reach here we should restructure the code to better document these realities.

The one question I am left with is why we use a single TOC Pseudo for 32-bit small code model (LWZtoc) but have LDtoc/'LDtocJTI`/LDtocCPT/LDtocBA for 64-bit small code model?

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5089

Thanks for mentioning that, I will open an internal issue as a reminder.

5133

The one question I am left with is why we use a single TOC Pseudo for 32-bit small code model (LWZtoc) but have LDtoc/'LDtocJTI`/LDtocCPT/LDtocBA for 64-bit small code model?

I think I kinda know why where are four opcodes for LDtoc but only one for LWZtoc.

It's that under 32bit mode, small/medium/large code model essentially all produce small code model results, so in TOC_ENTRY, we manually address this reality by setting opcode to LWZtoc. But for 64bit model, we only need to manually deal with medium and large code model, and we can leave small code model to table gen. So for different lowering targets[eg. global address, contant pool,...] table gen needs one opcode for each to do the lowering.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

121

sure, I will update it.

[sfertile]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5133

What do you think if we structured the code along these lines:

case PPCISD::TOC_ENTRY: {
  assert(!isDarwin() && "TOC is an ELF/XCOFF construct");

  // 64-bit small codemodel is handled by `SelectCommonCode`.
  if (is64BitELF() && CodeModel == small)
    break;

    // Transforms the ISD::TOC_ENTRY node to a PPCISD::LWZtoc
    auto replaceWithLWZtoc = [this, dl](SDNode *TocEntry) {
      SDValue SymOperand = TocEntry->getOperand(0);
      SDValue TocBase = TocEntry->getOperand(1);
      SDNode *MN = CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, SymOperand,
                                          TocBase);
      transferMemOperands(TocEntry, MN);
      ReplaceNode(TocEntry, MN);
    };


  if (is32BitELF()) {
    assert(isPositionIndependent() &&
            "32-bit ELF can only have TOC entries in position independant code.");
    // 32-bit ELF always uses a small codemodel toc access.
    replaceWithLWZtoc(N);
    return;
  }

  if (is32BitAIX() && CodeModel == Small) {
    replaceWithLWZtoc(N);
    return;
  }

  // Small code model has been handled, and PowerPC doesn't support tiny or kernel codemodels.
  assert(CodeModel == Medium || CodeModel == Large && "Unexpected code model");
  if (isAIX() && CodeModel == Medium)
    report_fatal_error("Medium code model is not supported on AIX.");

 // On 64-bit ELF we may be able to access the operand relative to the TOC base (in medium codemodel),
 // in which case we produce ADDItocL(ADDIStocHA(%x2, @sym), @sym).
 // Otherwise, we access the operand indirectly.
 // In 64-bit:
 //   LDtocL(@sym, ADDIStocHA(%x2, @sym))
 // In 32-bit:
 //   LWZtocL(@sym, ADDIStocHA32(%r2, @sym))
 ... Everything below here stays the same ...
}

[sfertile]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

118

Does it help readability if we add some extra helpers to the subtarget combining ABI and pointer width checks?
eg is64BitELF(), is32BitAIX() etc?

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5133

Thank you for your suggestion. I was trying to restructure the code, and I will see if I can adapt your code here to make it better.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

118

or we can do?:

assert(((isPPC64 && isTargetELF()) || isAIXABI) &&...

and

const bool is32BitAIX = !isPPC64 && isAIXABI;
const unsigned TOCReg = (is32BitAIX) ? PPC::X2 : PPC::R2;

[sfertile]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

118

Sure that works as well, stick with that for now. I think we already do a lot of checks like isPPC64() && isSVR4ABI() and with the addition of an AIX target we are going to end up with many more of these. I can post an NFC patch adding my suggestions and we evaluate if it helps or not in that context.

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

118

Thank you for doing that, though I just realized that I shouldn't have checked isPPC64() here, because there does exist 32bit+non-PIC situation[eg. LowerConstantPool] will take advantage of this function. But it seems weird to me that we use R2 for 32-bit. But I guess it's better to keep it that way and make changes for AIX only?

[sfertile]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

118

I'm sorry, I'm not sure I follow.

... though I just realized that I shouldn't have checked isPPC64() here, because there does exist 32bit+non-PIC situation[eg. LowerConstantPool] will take advantage of this function.

32-bit non-PIC ELF code? That will use a LabelRef instead of a TOC entry, and the 32-bit PIC ELF code always uses a LWZtoc so there is no corresponding 'lo' instruction to have to mark an implicit dependency on. If someone modifies address lowering to add a large code model for 32-bit ELF then your assertion should fail, which is what I though you were guarding against.

But it seems weird to me that we use R2 for 32-bit.

Do you mean instead of the GlobalBaseReg? The instructions we are looking for will only exist on AIX where we use r2 as the TOC base.

[Xiangling_L]

restructure the code

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

118

Sorry I didn't make it clear enough. The thing was that after I added the assertion, there were around 200 LIT testcases failed at isPPC64() It's because by default we added the TOCRegDeps pass for each PPC target. That makes me start to think that maybe I shouldn't have added that check here, and maybe there does exist 32bit platform where X2 is needed to be reserved. For example,

[lib/Target/PowerPC/PPCFastISel.cpp]

unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
...
      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
        .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
        .addReg(TmpReg)
        .addMemOperand(MMO);
...
}

It's adding PPCII::MO_TOC_LO target flag to constant pool index on both 32-bit&64-bit, for which, according to the function line 96: hasTOCLoReloc, we need to reserve X2.

And I feel that even if we are right that we shouldn't deal with 32bit medium/large code model anywhere, I am not sure if we want to clean those mess in this patch?

[sfertile]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5068

minor nit: we should probably check for SVR4 explicitly instead of if the object file format is ELF, just to be pedantic.

5072

nit: just check for isDarwin. Its really just an easy way to convey to the reader that Darwin code never reaches here. `
!isDarwin && (isELFABI || isAIXABI)` is tautological.

5074

nit: Couldn't the first operand also be a constant pool index or a block address? Maybe we just say its the symbol-reference?

5076–5085

Can we move this up either directly before or directly after the medium code model error for AIX?

5100

nit: combine the 2 ifs into a single condition.

5108

Follows form previous comment: I think this would be more readable if we try to keep the nesting to a minimum, eg:

if (!isPPC64 && isELFABI) {
   ....
   return;
}

if (!isPPC64 && isAIX && CModel == CodeModel::Small) {
  ...
return;
}

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3169

I think the naming convention is for 32-bit instructions is to have no number appended to the name, and 64-bit instructions have '8' appended.

[Xiangling_L]

minor changes of restructured code

[Xiangling_L]

restrict r0 usage for pseudo opcode ADDIStocHA32

[sfertile]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5068

Sorry if my previous comment was unclear. I think the name of the local was fine, in fact i find it much more readable then isSVR4ABI, just we should query they subtarget for the ABI instead of checking the object file format.

const bool isELFABI = PPCSubTarget->isSVR4ABI();

5070

minor nit: I personally prefer having error handling (and the following code where we break from the case) before anything else. Not sure how others feel about this.

5070

minor nit: do we need a local for this? As far as I can tell its used just once.

5076–5085

I really think this is better at the top of the block , rather then moving the error checking down. You should be able to get rid of the replaceForMediumOrLargeCM lambda by handling this before AIX large code model.

5102

minor nit: independant --> independent

5104

minor nit: codemodel --> code model

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

118

The thing was that after I added the assertion, there were around 200 LIT testcases failed at isPPC64() It's because by default we added the TOCRegDeps pass for each PPC target.

Ok. the failures are understandable then, we always add the pass so it runs but does nothing on 32-bit ELF targets. FWIW the 32-bit ELF abi supplement does have large code model examples, although using r31 as a GOT-pointer, and unless the 32-bit ELF linker does optimizations then there is no implicit dependence for the global register they do use.

It's adding PPCII::MO_TOC_LO target flag to constant pool index on both 32-bit&64-bit, for which, according to the function line 96: hasTOCLoReloc, we need to reserve X2.

That code will only be run for 64-bit targets. There is no comments explicitly stating that, but they get a temporary register from the PPC::G8RC_and_G8RC_NOX0RegClass register class which is 64-bit gpr register. 'PPC::X2' is likewise a 64-bit gpr, we couldn't add it as an operand on a 32-bit instruction.

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

251–252

I suggest we take this chance to split this up. It gets longer, but I think much more readable. Something along the lines of:

if (JIT)
  return CodeModel::Small;

if (TT.isOSAIX())
  return CodeModel::Small;

assert(TT.isOSBinFormatELF() && "All remaining PPC OSs are ELF based.");

if (TT.isArch32())
  return CodeMode::Small;

assert(TT.isArch64() && "Unsupported  PPC architecture.");
return CodeModel::Medium;

I made the assumption we don't have to support Darwin here anymore. There may be 1 or 2 tests left that use a Darwin target with llvm-mc. If you encounter problems I'll look at changing the test to no longer need darwin if possible. I think we have reached a point where we should try to actively clean up the darwin code.

[Xiangling_L]

further restructure the code

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

251–252

Thanks, I updated it. And there is no Darwin LIT testcase failure currently.

[sfertile]

A couple minor comments, I think we are almost there.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5079

Would it be better to document that Tiny and Kernel code models are not supported with an assert as opposed to a comment? Then we could simplify both the comment and the conditional below to isPPC64 && CodeModel == CodeModel::Small, as well as remove the assert following the comment // Small code model has been handled. below.

5121

minor nit: LWZtocL(@sym, ADDIStocHA(%r2, @sym))

5125

LDtocL(@sym, ADDIStocHA8(%x2, @sym))

5127

ditto

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

14345

minor nit: The second half of the comment doesn't really fit in with the rest of the function. Its an implementation detail (which is also explained at the point we perform said lowering). This function is about when we have to add indirection when accessing an operand. I would suggests shortening the comment to:

// If it is small or large code model, module locals are accessed
// indirectly by loading their address from .toc/.got.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3169

You should be able to rebase onto master to pick up the ADDIStocHA --> ADDIStocHA8 patch.

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

251–252

And there is no Darwin LIT testcase failure currently.

Nice.

[Xiangling_L]

minor changes

[sfertile]

A minor comment, but otherwise LGTM.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

115

minor nit: We only need to check isPPC64(), and not isAIXABI()'. If you want to document that isAIXABI()` is true whenever isPPC64() is false then an assert will do that.

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

115

I see what you mean, but I have a concern that the original code const unsigned TOCReg = PPC::X2 reserves X2 for PPC64 and PPC32, which though has no effect on 32bit mode. But if we do const unsigned TOCReg = (isPPC64) ? PPC::X2 : PPC::R2;, we do affect other 32bit platform other than AIX by reserving r2 considering this machine pass runs for all PPC target. Is this okay?

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

115

To be more clear, as I mentioned before, when I added an assertion for isPPC64 there were 200ish testcases failures, it indicates that there are other 32bit PPC platform running this function, so only check isPPC64 like const unsigned TOCReg = (isPPC64) ? PPC::X2 : PPC::R2; may affect those 32bit platform?

[sfertile]

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

115

Sorry I forgot about this running for every PPC target,. That rules out the assert I mentioned.

the original code const unsigned TOCReg = PPC::X2 reserves X2 for PPC64 and PPC32, which though has no effect on 32bit mode

IIUC it seems to me you are implying setting X2 as an implicit dependence on a 32-bit instruction has no effect. I don't believe this is true. This pass only has no effect on 32-bit ELF/Darwin because hasTOCLoReloc returns false for every instruction on those platforms; None of those opcodes will be used on 32-bit ELF or any Darwin, and as we saw previously PPCII::MO_TOC_LO is only ever (currently) set on 64-bit instructions.

The way this pass runs for every platform but will not possibly be able to modify any instructions on some of those platforms is confusing. I find adding code like the below line extends that confusion, because on its own it seems to imply there are 32-bit targets other then AIX that this pass is relevant too, and for some reason on those targets X2 is a dependence even though its a 32-bit instruction.

If we want to guard against setting an implicit dependence on a platform where its not needed/expected then we need to do exactly that (likely in hasTOCReloc). Using the wrong register as a dependence isn't the way to proceed.

[Xiangling_L]

minor changes

[hubert.reinterpretcast]

Some initial comments.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5081

Minor nit: Fix the spacing.

5084

Move this to after dealing with some initial 32-bit cases.

5089

Put this into a !isPPC64 block.

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5089

I think the usage of replaceWithLWZtoc itself is guarded by !isPPC64, do we still need add !isPPC64 for this block? Or we can add a comment specifying it's 32bit only?

[Xiangling_L]

adjust the flow of the code

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5075

This can be made const.

5076

Use English "code model" or code-style CodeModel.
Use clang-format.

assert((CModel != CodeModel::Tiny || CModel != CodeModel::Kernel) &&
       "PowerPC doesn't support tiny or kernel code models.");

5090

Should dl be captured by copy? It seems to be passed by reference to getMachineNode. Also, a SDLoc holds a DebugLoc, and DebugLoc::hasTrivialDestructor indicates that the destruction is not always free.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5084

Missing space before LDtocCPT.

5088

It might help to have a comment before the block to indicate that it handles the rest of the cases for the small code model.

5100

Indentation is four spaces in from the surrounding context here (should be two).

5106

Closing brace does not line up with the corresponding if.

5114

Add an assertion before this:

assert(CModel != CodeModel::Small);

5114

The English does not match the assertion. The assertion says that either we are dealing with 64-bit (ELF or AIX) or 32-bit AIX.

5118

[ ... ] or 64-bit medium (ELF-only) or large (ELF and AIX) code model code. [ ... ]

5119

Missing space after the period.

5124

Please clarify the treatment of 64-bit AIX.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5132

Remove the extra parentheses and use clang-format:

SDNode *Tmp = CurDAG->getMachineNode(
    isPPC64 ? PPC::ADDIStocHA8 : PPC::ADDIStocHA, dl, VT, TOCbase, GA);

5139

Same comment.

SDNode *MN = CurDAG->getMachineNode(isPPC64 ? PPC::LDtocL : PPC::LWZtocL,
                                    dl, VT, GA, SDValue(Tmp, 0));

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

2671

To be consistent with how the function parameters are declared (note the positioning of the space):

const PPCSubtarget &Subtarget =

Anyhow, I would much like to avoid having this cast here. Can this function be made a private member function of PPCTargetLowering?

2673

This can be const.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

3169

To be consistent with the above lines, add a space before the :.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

115

Remove the extra parentheses.

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

258

"OSes" is the spelling used in various messages.

263

Fix the two consecutive spaces.

llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll

2

lit can display stderr separately from stdout. If we are not checking for error messages, then redirecting stderr to stdout does not seem advantageous.

9

Same comment.

13

Same comment.

llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll

2

Same comment.

9

Same comment.

13

Same comment.

[hubert.reinterpretcast]

@Xiangling_L, I'd be happy to work with you on this off-list to move this along.

[Xiangling_L]

llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll

2

We redirect stderr to stdout because the option -print-before=simple-register-coalescing is used to output the register usage details[eg. nor0] and it outputs to stderr.

[Xiangling_L]

Address latest comments

[hubert.reinterpretcast]

LGTM with a minor issue that can be fixed on check-in.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5075

Minor issue: This is currently (!A || !B), but !(A || B) is meant.

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5075

The landed commit did not address this comment. Could you do an NFC commit to address it?

[Xiangling_L]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5075

Oops.... I addressed it but forgot to commit it together. Will do asap.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

case ISD::BRIND: {
     unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
     unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
     Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
                                            Chain), 0);
     CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
     return;
   }
   case PPCISD::TOC_ENTRY: {
-    assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
-            "Only supported for 64-bit ABI and 32-bit SVR4");
-    if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
-      SDValue GA = N->getOperand(0);
+    const bool isPPC64 = PPCSubTarget->isPPC64();
+    const bool isELFABI = PPCSubTarget->isSVR4ABI();
+    const bool isAIXABI = PPCSubTarget->isAIXABI();
+
+    assert (!PPCSubTarget->isDarwin() && "TOC is an ELF/XCOFF construct");
+
+    // PowerPC only support small, medium and large code model.
+    CodeModel::Model CModel = TM.getCodeModel();
+    assert((CModel != CodeModel::Tiny ||
+           CModel != CodeModel::Kernel) &&
+               "PowerPC doesn't support tiny or kernel codemodels.");
+
+    if (isAIXABI && CModel == CodeModel::Medium)
+      report_fatal_error("Medium code model is not supported on AIX.");
+
+    // For 64-bit small code model, we allow SelectCodeCommon to handle this,
+    // selecting one of LDtoc, LDtocJTI,LDtocCPT, and LDtocBA.
+    if (isPPC64 && CModel == CodeModel::Small)
+      break;
+
+    if (!isPPC64) {
+      // Transforms the ISD::TOC_ENTRY node to a PPCISD::LWZtoc.
+      auto replaceWithLWZtoc = [this, dl](SDNode *TocEntry) {
+        SDValue GA = TocEntry->getOperand(0);
+        SDValue TocBase = TocEntry->getOperand(1);
         SDNode *MN = CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
-                                          N->getOperand(1));
-      transferMemOperands(N, MN);
-      ReplaceNode(N, MN);
+                                            TocBase);
+        transferMemOperands(TocEntry, MN);
+        ReplaceNode(TocEntry, MN);
+      };
+   
+      if (isELFABI) {
+          assert (TM.isPositionIndependent() &&
+                 "32-bit ELF can only have TOC entries in position independent"
+                 " code.");
+          // 32-bit ELF always uses a small code model toc access.
+          replaceWithLWZtoc(N);
           return;
-    }
+        } 
     
-    // For medium and large code model, we generate two instructions as
-    // described below.  Otherwise we allow SelectCodeCommon to handle this,
-    // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
-    CodeModel::Model CModel = TM.getCodeModel();
-    if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
-      break;
+      if (isAIXABI && CModel == CodeModel::Small) {
+          replaceWithLWZtoc(N);
+          return;
+      }  
+    }
+
+    assert((isPPC64 || (isAIXABI && !isPPC64)) && "Only 64-bit ELF or 32-bit AIX"
+          " support medium/large code model."); 
 
-    // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
-    // If it must be toc-referenced according to PPCSubTarget, we generate:
+    // Transforms the ISD::TOC_ENTRY node for 32-bit AIX large code model mode
+    // or 64-bit ELF medium or large code model mode. We generate two
+    // instructions as described below.The first source operand is a symbol
+    // reference. If it must be toc-referenced according to PPCSubTarget, we
+    // generate:
+    // [32-bit AIX]
+    //   LWZtocL(@sym, ADDIStocHA(%r2, @sym))
+    // [64-bit ELF]
     //   LDtocL(@sym, ADDIStocHA8(%x2, @sym))
     // Otherwise we generate:
     //   ADDItocL(ADDIStocHA8(%x2, @sym), @sym)
     SDValue GA = N->getOperand(0);
     SDValue TOCbase = N->getOperand(1);
-    SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA8, dl, MVT::i64,
-                                         TOCbase, GA);
+
+    EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
+    SDNode *Tmp = CurDAG->getMachineNode((isPPC64) ? PPC::ADDIStocHA8 :
+                                         PPC::ADDIStocHA, dl, VT, TOCbase,
+                                         GA);
+
     if (PPCLowering->isAccessedAsGotIndirect(GA)) {
-      // If it is access as got-indirect, we need an extra LD to load
+      // If it is accessed as got-indirect, we need an extra LWZ/LD to load
       // the address.
-      SDNode *MN = CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
+      SDNode *MN = CurDAG->getMachineNode((isPPC64) ? PPC::LDtocL :
+                                          PPC::LWZtocL, dl, VT, GA,
                                           SDValue(Tmp, 0));
+
       transferMemOperands(N, MN);
       ReplaceNode(N, MN);
       return;
     }
 
-    // Build the address relative to the TOC-pointer..
+    // Build the address relative to the TOC-pointer.
     ReplaceNode(N, CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
                                           SDValue(Tmp, 0), GA));
     return;
   }
   case PPCISD::PPC32_PICGOT:
     // Generate a PIC-safe GOT reference.
     assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
       "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 ///
 /// The ShuffleKind distinguishes between big-endian operations with
 /// two different inputs (0), either-endian operations with two identical
 /// inputs (1), and little-endian operations with two different inputs (2).
 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
                                SelectionDAG &DAG) {
   const PPCSubtarget& Subtarget =
       static_cast<const PPCSubtarget&>(DAG.getSubtarget());
   if (!Subtarget.hasP8Vector())
     return false;
 
   bool IsLE = DAG.getDataLayout().isLittleEndian();
   if (ShuffleKind == 0) {
     if (IsLE)
       return false;
     for (unsigned i = 0; i != 16; i += 4)
static void setUsesTOCBasePtr(MachineFunction &MF) {
   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
   FuncInfo->setUsesTOCBasePtr();
 }
 
 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
   setUsesTOCBasePtr(DAG.getMachineFunction());
 }
 
-static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
-                           SDValue GA) {
+static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) {
+  const PPCSubtarget& Subtarget =
+    static_cast<const PPCSubtarget&>(DAG.getSubtarget());
+  bool Is64Bit = Subtarget.isPPC64();
   EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
-  SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
-                DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
-
+  SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
+                        : Subtarget.isAIXABI()
+                              ? DAG.getRegister(PPC::R2, VT)
+                              : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
   SDValue Ops[] = { GA, Reg };
   return DAG.getMemIntrinsicNode(
       PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
       MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
       MachineMemOperand::MOLoad);
 }
 
 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
                                              SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
   const Constant *C = CP->getConstVal();
 
   // 64-bit SVR4 ABI code is always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
   if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
     setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
-    return getTOCEntry(DAG, SDLoc(CP), true, GA);
+    return getTOCEntry(DAG, SDLoc(CP), GA);
   }
 
   unsigned MOHiFlag, MOLoFlag;
   bool IsPIC = isPositionIndependent();
   getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
 
   if (IsPIC && Subtarget.isSVR4ABI()) {
     SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
                                            PPCII::MO_PIC_FLAG);
-    return getTOCEntry(DAG, SDLoc(CP), false, GA);
+    return getTOCEntry(DAG, SDLoc(CP), GA);
   }
 
   SDValue CPIHi =
     DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
   SDValue CPILo =
     DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
   return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
 }
SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
 
   // 64-bit SVR4 ABI code is always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
   if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
     setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
-    return getTOCEntry(DAG, SDLoc(JT), true, GA);
+    return getTOCEntry(DAG, SDLoc(JT), GA);
   }
 
   unsigned MOHiFlag, MOLoFlag;
   bool IsPIC = isPositionIndependent();
   getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
 
   if (IsPIC && Subtarget.isSVR4ABI()) {
     SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
                                         PPCII::MO_PIC_FLAG);
-    return getTOCEntry(DAG, SDLoc(GA), false, GA);
+    return getTOCEntry(DAG, SDLoc(GA), GA);
   }
 
   SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
   SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
   return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
 }
 
 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
                                              SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
   const BlockAddress *BA = BASDN->getBlockAddress();
 
   // 64-bit SVR4 ABI code is always position-independent.
   // The actual BlockAddress is stored in the TOC.
   if (Subtarget.isSVR4ABI() &&
       (Subtarget.isPPC64() || isPositionIndependent())) {
     if (Subtarget.isPPC64())
       setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
-    return getTOCEntry(DAG, SDLoc(BASDN), Subtarget.isPPC64(), GA);
+    return getTOCEntry(DAG, SDLoc(BASDN), GA);
   }
 
   unsigned MOHiFlag, MOLoFlag;
   bool IsPIC = isPositionIndependent();
   getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
   SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
   SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
   return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);

 
 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
                                               SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
   SDLoc DL(GSDN);
   const GlobalValue *GV = GSDN->getGlobal();
 
-  // 64-bit SVR4 ABI code is always position-independent.
+  // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
-  if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
+  if ((Subtarget.isSVR4ABI() && Subtarget.isPPC64()) || Subtarget.isAIXABI()) {
     setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
-    return getTOCEntry(DAG, DL, true, GA);
+    return getTOCEntry(DAG, DL, GA);
   }
 
   unsigned MOHiFlag, MOLoFlag;
   bool IsPIC = isPositionIndependent();
   getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
 
   if (IsPIC && Subtarget.isSVR4ABI()) {
     SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
                                             GSDN->getOffset(),
                                             PPCII::MO_PIC_FLAG);
-    return getTOCEntry(DAG, DL, false, GA);
+    return getTOCEntry(DAG, DL, GA);
   }
 
   SDValue GAHi =
     DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
   SDValue GALo =
     DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
 
   SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
   report_fatal_error("Invalid register name global variable");
 }
 
 bool PPCTargetLowering::isAccessedAsGotIndirect(SDValue GA) const {
   // 32-bit SVR4 ABI access everything as got-indirect.
   if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
     return true;
 
+  // AIX accesses everything indirectly through the TOC, which is similar to
+  // the GOT.
+  if (Subtarget.isAIXABI())
+    return true;
+
   CodeModel::Model CModel = getTargetMachine().getCodeModel();
   // If it is small or large code model, module locals are accessed
-  // indirectly by loading their address from .toc/.got. The difference
-  // is that for large code model we have ADDIStocHA8 + LDtocL and for
-  // small code model we simply have LDtoc.
+  // indirectly by loading their address from .toc/.got.
   if (CModel == CodeModel::Small || CModel == CodeModel::Large)
     return true;
 
   // JumpTable and BlockAddress are accessed as got-indirect.
   if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA))
     return true;
 
   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp),
                               (PPCaddisDtprelHA i32:$reg,
                                                 tglobaltlsaddr:$disp))]>;
 
 // Support for Position-independent code
 def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
                    "#LWZtoc",
                    [(set i32:$rD,
                       (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
+def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg),
+                    "#LWZtocL",
+                    [(set i32:$rD,
+                      (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
+def ADDIStocHA: PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
+                        "#ADDIStocHA",
+                        [(set i32:$rD,
+                          (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>;
+
 // Get Global (GOT) Base Register offset, from the word immediately preceding
 // the function label.
 def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;
 
 
 // Standard shifts.  These are represented separately from the real shifts above
 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
 // amounts.

llvm/lib/Target/PowerPC/PPCTOCRegDeps.cpp

struct PPCTOCRegDeps : public MachineFunctionPass {
     static char ID;
     PPCTOCRegDeps() : MachineFunctionPass(ID) {
       initializePPCTOCRegDepsPass(*PassRegistry::getPassRegistry());
     }
 
 protected:
     bool hasTOCLoReloc(const MachineInstr &MI) {
       if (MI.getOpcode() == PPC::LDtocL ||
-          MI.getOpcode() == PPC::ADDItocL)
+          MI.getOpcode() == PPC::ADDItocL || 
+          MI.getOpcode() == PPC::LWZtocL)
         return true;
 
       for (const MachineOperand &MO : MI.operands()) {
         if ((MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) == PPCII::MO_TOC_LO)
           return true;
       }
 
       return false;
     }
 
     bool processBlock(MachineBasicBlock &MBB) {
       bool Changed = false;
 
+      const bool isPPC64 =
+          MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
+      const unsigned TOCReg = (isPPC64) ? PPC::X2 : PPC::R2;
+
       for (auto &MI : MBB) {
         if (!hasTOCLoReloc(MI))
           continue;
 
-        MI.addOperand(MachineOperand::CreateReg(PPC::X2,
+        MI.addOperand(MachineOperand::CreateReg(TOCReg,
                                                 false  /*IsDef*/,
                                                 true  /*IsImp*/));
         Changed = true;
       }
 
       return Changed;
     }
 
 public:
     bool runOnMachineFunction(MachineFunction &MF) override {
       bool Changed = false;
 
       for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
         MachineBasicBlock &B = *I++;
         if (processBlock(B))
           Changed = true;
       }
 
       return Changed;
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       MachineFunctionPass::getAnalysisUsage(AU);
     }
   };

llvm/lib/Target/PowerPC/PPCTargetMachine.cpp

static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT,
                                                  Optional<CodeModel::Model> CM,
                                                  bool JIT) {
   if (CM) {
     if (*CM == CodeModel::Tiny)
       report_fatal_error("Target does not support the tiny CodeModel", false);
     if (*CM == CodeModel::Kernel)
       report_fatal_error("Target does not support the kernel CodeModel", false);
     return *CM;
   }
-  if (!TT.isOSDarwin() && !JIT &&
-      (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le))
-    return CodeModel::Medium;
+
+  if (JIT)
     return CodeModel::Small;
+  if (TT.isOSAIX())
+    return CodeModel::Small;
+  
+  assert(TT.isOSBinFormatELF() && "All remaining PPC OSs are ELF based.");
+  
+  if (TT.isArch32Bit())
+    return CodeModel::Small;
+
+  assert(TT.isArch64Bit() && "Unsupported  PPC architecture.");
+  return CodeModel::Medium;
 }
 
 
 static ScheduleDAGInstrs *createPPCMachineScheduler(MachineSchedContext *C) {
   const PPCSubtarget &ST = C->MF->getSubtarget<PPCSubtarget>();
   ScheduleDAGMILive *DAG =
     new ScheduleDAGMILive(C, ST.usePPCPreRASchedStrategy() ?
                           llvm::make_unique<PPCPreRASchedStrategy>(C) :

llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll

+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small \
+; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \
+; RUN: %s | FileCheck --check-prefix=SMALL %s
+
+; RUN: not llc -mtriple powerpc-ibm-aix-xcoff -code-model=medium \
+; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s
+
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large \
+; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \
+; RUN: %s | FileCheck --check-prefix=LARGE %s
+
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp \
+; RUN: -print-before=simple-register-coalescing 2>&1 < %s | FileCheck \
+; RUN: --check-prefix=SMALL %s
+
+@msg = common global i8* null, align 4
+@ptr = common global i8* null, align 4
+
+define void @foo() {
+entry:
+; SMALL: %0:gprc_and_gprc_nor0 = LWZtoc @msg, $r2 :: (load 4 from got)
+; SMALL: %1:gprc = LWZ 0, %0:gprc_and_gprc_nor0 :: (dereferenceable load 4 from @msg)
+; SMALL: %2:gprc_and_gprc_nor0 = LWZtoc @ptr, $r2 :: (load 4 from got)
+; SMALL: STW %1:gprc, 0, %2:gprc_and_gprc_nor0 :: (store 4 into @ptr)
+
+; MEDIUM: Medium code model is not supported on AIX.
+
+; LARGE: %0:gprc_and_gprc_nor0 = ADDIStocHA $r2, @msg
+; LARGE: %1:gprc_and_gprc_nor0 = LWZtocL @msg, %0:gprc_and_gprc_nor0, implicit $r2 :: (load 4 from got)
+; LARGE: %2:gprc = LWZ 0, %1:gprc_and_gprc_nor0 :: (dereferenceable load 4 from @msg)
+; LARGE: %3:gprc_and_gprc_nor0 = ADDIStocHA $r2, @ptr
+; LARGE: %4:gprc_and_gprc_nor0 = LWZtocL @ptr, %3:gprc_and_gprc_nor0, implicit $r2 :: (load 4 from got)
+; LARGE: STW %2:gprc, 0, %4:gprc_and_gprc_nor0 :: (store 4 into @ptr)
+
+  %0 = load i8*, i8** @msg, align 4
+  store i8* %0, i8** @ptr, align 4
+  ret void
+}

llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll

+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=small \
+; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \
+; RUN: %s | FileCheck --check-prefix=SMALL %s
+
+; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -code-model=medium \
+; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s
+
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large \
+; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \ 
+; RUN: %s | FileCheck --check-prefix=LARGE %s
+
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp \
+; RUN: -print-before=simple-register-coalescing 2>&1 < %s | FileCheck \
+; RUN: --check-prefix=SMALL %s
+
+@msg = common global i8* null, align 8
+@ptr = common global i8* null, align 8
+
+define void @foo() {
+entry:
+; SMALL: %0:g8rc_and_g8rc_nox0 = LDtoc @msg, $x2 :: (load 8 from got)
+; SMALL: %1:g8rc = LD 0, %0:g8rc_and_g8rc_nox0 :: (dereferenceable load 8 from @msg)
+; SMALL: %2:g8rc_and_g8rc_nox0 = LDtoc @ptr, $x2 :: (load 8 from got)
+; SMALL: STD %1:g8rc, 0, %2:g8rc_and_g8rc_nox0 :: (store 8 into @ptr)
+
+; MEDIUM: Medium code model is not supported on AIX.
+
+; LARGE: %0:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @msg
+; LARGE: %1:g8rc_and_g8rc_nox0 = LDtocL @msg, %0:g8rc_and_g8rc_nox0, implicit $x2 :: (load 8 from got)
+; LARGE: %2:g8rc = LD 0, %1:g8rc_and_g8rc_nox0 :: (dereferenceable load 8 from @msg)
+; LARGE: %3:g8rc_and_g8rc_nox0 = ADDIStocHA8 $x2, @ptr
+; LARGE: %4:g8rc_and_g8rc_nox0 = LDtocL @ptr, %3:g8rc_and_g8rc_nox0, implicit $x2 :: (load 8 from got)
+; LARGE: STD %2:g8rc, 0, %4:g8rc_and_g8rc_nox0 :: (store 8 into @ptr)
+
+  %0 = load i8*, i8** @msg, align 8
+  store i8* %0, i8** @ptr, align 8
+  ret void
+}