Emit diagnostic if an inline asm constraint requires an immediate

[void]

Summary

An inline asm call can result in an immediate after inlining. Therefore emit a
diagnostic here if constraint requires an immediate but one isn't supplied.

[void]

Fix testcase to get the correct error message.

[void]

Add testcase.

[mgorny]

I can confirm that it fixes our issue but I don't feel confident reviewing the code itself. Copying reviewers from the original diff.

[joerg]

It does not fix the issues on our side, but pushes them to a different place. It is still an improvement, but the problem is not solved yet.

[void]

In D60942#1477583, @joerg wrote:

It does not fix the issues on our side, but pushes them to a different place. It is still an improvement, but the problem is not solved yet.

Joerg, What's the error again? (I forgot, sorry.)

[joerg]

On the frontend side:

• __builtin_constant_p is not expanded correctly in EvalConstant.cpp when used as part of codegen for -O0. This means that trivially unreachable branches are emitted (e.g. with a BR with a literal false as condition),
• The constant evaluator has a general problem with overly pessimistic analysis when it comes to possible side effects. Still have to discuss the correct handling with Richard for this.

On the backend side:

• The is_constant intrinsic is lowered too late. The prepare-isel pass it is currently part of is run after the last SimplifyCFG pass, so the now-dead basic blocks are never pruned and therefore the asm statements survive.

All that said, with the discussed generalization from literal 'n' to 'expects immediate', I think this code solves the part of the problem it is meant to solve.

[void]

In D60942#1500730, @joerg wrote:

On the frontend side:

• __builtin_constant_p is not expanded correctly in EvalConstant.cpp when used as part of codegen for -O0. This means that trivially unreachable branches are emitted (e.g. with a BR with a literal false as condition),
• The constant evaluator has a general problem with overly pessimistic analysis when it comes to possible side effects. Still have to discuss the correct handling with Richard for this.

GCC has this to say about __builtin_constant_p's behavior:

A return of 0 does not indicate that the value is not a constant, but merely that GCC cannot prove it is a constant with the specified value of the -O option.

When I was modifying our implementation recently, I made it so that if there are no optimizations then we evaluate to 0 in the front-end before code-gen. It might be that those blocks are being emitted, but they should have something like br i1 false, label %true_bb, label %false_bb or equivalent.

On the backend side:

• The is_constant intrinsic is lowered too late. The prepare-isel pass it is currently part of is run after the last SimplifyCFG pass, so the now-dead basic blocks are never pruned and therefore the asm statements survive.

Is this at -O0 or all optimization levels?

All that said, with the discussed generalization from literal 'n' to 'expects immediate', I think this code solves the part of the problem it is meant to solve.

W00T!

[joerg]

In D60942#1500742, @void wrote:

In D60942#1500730, @joerg wrote:

On the frontend side:

• __builtin_constant_p is not expanded correctly in EvalConstant.cpp when used as part of codegen for -O0. This means that trivially unreachable branches are emitted (e.g. with a BR with a literal false as condition),
• The constant evaluator has a general problem with overly pessimistic analysis when it comes to possible side effects. Still have to discuss the correct handling with Richard for this.

GCC has this to say about __builtin_constant_p's behavior:

A return of 0 does not indicate that the value is not a constant, but merely that GCC cannot prove it is a constant with the specified value of the -O option.

When I was modifying our implementation recently, I made it so that if there are no optimizations then we evaluate to 0 in the front-end before code-gen. It might be that those blocks are being emitted, but they should have something like br i1 false, label %true_bb, label %false_bb or equivalent.

Yes, that's correct. The problem is that with -O0, we never run SimplifyCFG, so those conditional branches make it straight to the backend. As discussed with Richard on IRC, the core issue is that for -O0, the IR generation for __builtin_constant_p is different from the constant folding as part of AST/EvalConstant.cpp. The latter is used by EmitIfStmt and friends to decide whether the BBs should be created in first place and currently fails evaluation for bcp.

On the backend side:

• The is_constant intrinsic is lowered too late. The prepare-isel pass it is currently part of is run after the last SimplifyCFG pass, so the now-dead basic blocks are never pruned and therefore the asm statements survive.

Is this at -O0 or all optimization levels?

With -O0, the intrinsic is never generated and no SimplifyCFG is run either (see above).

[void]

In D60942#1500749, @joerg wrote:

In D60942#1500742, @void wrote:

In D60942#1500730, @joerg wrote:

On the frontend side:

• __builtin_constant_p is not expanded correctly in EvalConstant.cpp when used as part of codegen for -O0. This means that trivially unreachable branches are emitted (e.g. with a BR with a literal false as condition),
• The constant evaluator has a general problem with overly pessimistic analysis when it comes to possible side effects. Still have to discuss the correct handling with Richard for this.

GCC has this to say about __builtin_constant_p's behavior:

A return of 0 does not indicate that the value is not a constant, but merely that GCC cannot prove it is a constant with the specified value of the -O option.

When I was modifying our implementation recently, I made it so that if there are no optimizations then we evaluate to 0 in the front-end before code-gen. It might be that those blocks are being emitted, but they should have something like br i1 false, label %true_bb, label %false_bb or equivalent.

Yes, that's correct. The problem is that with -O0, we never run SimplifyCFG, so those conditional branches make it straight to the backend. As discussed with Richard on IRC, the core issue is that for -O0, the IR generation for __builtin_constant_p is different from the constant folding as part of AST/EvalConstant.cpp. The latter is used by EmitIfStmt and friends to decide whether the BBs should be created in first place and currently fails evaluation for bcp.

On the backend side:

• The is_constant intrinsic is lowered too late. The prepare-isel pass it is currently part of is run after the last SimplifyCFG pass, so the now-dead basic blocks are never pruned and therefore the asm statements survive.

Is this at -O0 or all optimization levels?

With -O0, the intrinsic is never generated and no SimplifyCFG is run either (see above).

Ah! I understand now. I'll see if there's something I can do to help with this. Could you send me some test cases so that I can test things?

[mgorny]

Is there anything blocking this part from being committed?

[joerg]

The patch still needs to be generalized to handle all ICE constraints, but it is not blocked by the review for handling the is.constant intrinsic.

[void]

Expand the diagnostic to support all constraints that require immediates.

[void]

I added a new constraint type C_Immdediate which indicates that a constraint requires an immediate value.

Please take a look.

[void]

Friendly ping.

[void]

Updating.

[void]

Revert the prvious update

[void]

Revert accidentally added files.

[joerg]

lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

439 ↗

(On Diff #210713)

This is an unrelated chunk. Can you drop it please? I like the idea, but it would be nicer if it didn't need to create an intermediate label at all.

[void]

Remove file that sneaked in.

lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

439 ↗

(On Diff #210713)

Ah! Yes, this sneaked in there...

[joerg]

With the exception of the small improvements outlined, this looks good to me.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7966 ↗

(On Diff #212029)

Unrelated, but shouldn't Flags be filtered first? E.g.

Flags &= ~(InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);

There seems to be one test case (PowerPC/xray-ret-is-terminate.ll) that depends on this somewhat.

Adding C_Immediate here seems to be wrong though, since immediates are never loads or stores. As such, shall we just drop this chunk and bring up the Flags update separate?

8056 ↗

(On Diff #212029)

like the "n" constraint

lib/Target/X86/X86ISelLowering.cpp

44780 ↗

(On Diff #212029)

'L' means 0xFF or 0xFFFF, that should be C_Immediate.

44781 ↗

(On Diff #212029)

'M' means 0..3 as shifts for LEA, should be C_Immediate as well.

[void]

Mark some constraints which require immediates as needing immediates.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

7966 ↗

(On Diff #212029)

I wanted to retain the original behavior, but yeah it seems like C_Immediate isn't really worth checking here.

As for the Flags, wouldn't clearing the flags remove previous iterations which set them? This is being called in a loop over all asm contraints...

[joerg]

LGTM otherwise.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

8055 ↗

(On Diff #212068)

Typo still.

[void]

"like" :: "line" -- "potAYto" :: "potAHto"

:-)

[void]

Emit an error for an out-of-range immediate.

[void]

Update testing. This adds support for RISC-V inline asm immediate constraints
so that we emit the same errors that the front-end would.

[void]

I've updated this patch to better coincide with D60943. It adds support for RISC-V inline asm immediate constraints (to make the errors match those of the front-end) and a few more tests. Please take another look, since these are non-trivial changes.

Thanks!

llvm/trunk/include/llvm/CodeGen/TargetLowering.h

public:
   virtual bool ExpandInlineAsm(CallInst *) const {
     return false;
   }
 
   enum ConstraintType {
     C_Register,            // Constraint represents specific register(s).
     C_RegisterClass,       // Constraint represents any of register(s) in class.
     C_Memory,              // Memory constraint.
+    C_Immediate,           // Requires an immediate.
     C_Other,               // Something else.
     C_Unknown              // Unsupported constraint.
   };
 
   enum ConstraintWeight {
     // Generic weights.
     CW_Invalid  = -1,     // No match.
     CW_Okay     = 0,      // Acceptable.

llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (!HasSideEffect)
       HasSideEffect = OpInfo.hasMemory(TLI);
 
     // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
     // FIXME: Could we compute this on OpInfo rather than T?
 
     // Compute the constraint code and ConstraintType to use.
     TLI.ComputeConstraintToUse(T, SDValue());
 
+    if (T.ConstraintType == TargetLowering::C_Immediate &&
+        OpInfo.CallOperand && !isa<ConstantSDNode>(OpInfo.CallOperand))
+      // We've delayed emitting a diagnostic like the "n" constraint because
+      // inlining could cause an integer showing up.
+      return emitInlineAsmError(
+          CS, "constraint '" + Twine(T.ConstraintCode) + "' expects an "
+                  "integer constant expression");
+
     ExtraInfo.update(T);
   }
 
 
   // We won't need to flush pending loads if this asm doesn't touch
   // memory and is nonvolatile.
   SDValue Flag, Chain = (HasSideEffect) ? getRoot() : DAG.getRoot();
 
SDISelAsmOperandInfo &RefOpInfo =
         OpInfo.isMatchingInputConstraint()
             ? ConstraintOperands[OpInfo.getMatchedOperand()]
             : OpInfo;
     GetRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo);
 
     switch (OpInfo.Type) {
     case InlineAsm::isOutput:
       if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
-          (OpInfo.ConstraintType == TargetLowering::C_Other &&
+          ((OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+            OpInfo.ConstraintType == TargetLowering::C_Other) &&
            OpInfo.isIndirect)) {
         unsigned ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         assert(ConstraintID != InlineAsm::Constraint_Unknown &&
                "Failed to convert memory constraint code to constraint id.");
 
         // Add information to the INLINEASM node to know about this output.
         unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
         OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
         AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
                                                         MVT::i32));
         AsmNodeOperands.push_back(OpInfo.CallOperand);
         break;
-      } else if ((OpInfo.ConstraintType == TargetLowering::C_Other &&
+      } else if (((OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+                   OpInfo.ConstraintType == TargetLowering::C_Other) &&
                   !OpInfo.isIndirect) ||
                  OpInfo.ConstraintType == TargetLowering::C_Register ||
                  OpInfo.ConstraintType == TargetLowering::C_RegisterClass) {
         // Otherwise, this outputs to a register (directly for C_Register /
-        // C_RegisterClass, and a target-defined fashion for C_Other). Find a
-        // register that we can use.
+        // C_RegisterClass, and a target-defined fashion for
+        // C_Immediate/C_Other). Find a register that we can use.
         if (OpInfo.AssignedRegs.Regs.empty()) {
           emitInlineAsmError(
               CS, "couldn't allocate output register for constraint '" +
                       Twine(OpInfo.ConstraintCode) + "'");
           return;
         }
 
         // Add information to the INLINEASM node to know that this register is
case InlineAsm::isInput: {
                                                     OpInfo.getMatchedOperand());
         AsmNodeOperands.push_back(DAG.getTargetConstant(
             OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
         AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
         break;
       }
 
       // Treat indirect 'X' constraint as memory.
-      if (OpInfo.ConstraintType == TargetLowering::C_Other &&
+      if ((OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+           OpInfo.ConstraintType == TargetLowering::C_Other) &&
           OpInfo.isIndirect)
         OpInfo.ConstraintType = TargetLowering::C_Memory;
 
-      if (OpInfo.ConstraintType == TargetLowering::C_Other) {
+      if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
+          OpInfo.ConstraintType == TargetLowering::C_Other) {
         std::vector<SDValue> Ops;
         TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
                                           Ops, DAG);
         if (Ops.empty()) {
+          if (OpInfo.ConstraintType == TargetLowering::C_Immediate)
+            if (isa<ConstantSDNode>(InOperandVal)) {
+              emitInlineAsmError(CS, "value out of range for constraint '" +
+                                 Twine(OpInfo.ConstraintCode) + "'");
+              return;
+            }
+
           emitInlineAsmError(CS, "invalid operand for inline asm constraint '" +
                                      Twine(OpInfo.ConstraintCode) + "'");
           return;
         }
 
         // Add information to the INLINEASM node to know about this input.
         unsigned ResOpType =
           InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
case InlineAsm::isInput: {
         AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
                                                         getCurSDLoc(),
                                                         MVT::i32));
         AsmNodeOperands.push_back(InOperandVal);
         break;
       }
 
       assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
-              OpInfo.ConstraintType == TargetLowering::C_Register) &&
+              OpInfo.ConstraintType == TargetLowering::C_Register ||
+              OpInfo.ConstraintType == TargetLowering::C_Immediate) &&
              "Unknown constraint type!");
 
       // TODO: Support this.
       if (OpInfo.isIndirect) {
         emitInlineAsmError(
             CS, "Don't know how to handle indirect register inputs yet "
                 "for constraint '" +
                     Twine(OpInfo.ConstraintCode) + "'");
if (OpInfo.Type == InlineAsm::isOutput) {
         continue;
 
       switch (OpInfo.ConstraintType) {
       case TargetLowering::C_Register:
       case TargetLowering::C_RegisterClass:
         Val = OpInfo.AssignedRegs.getCopyFromRegs(
             DAG, FuncInfo, getCurSDLoc(), Chain, &Flag, CS.getInstruction());
         break;
+      case TargetLowering::C_Immediate:
       case TargetLowering::C_Other:
         Val = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(),
                                               OpInfo, DAG);
         break;
       case TargetLowering::C_Memory:
         break; // Already handled.
       case TargetLowering::C_Unknown:
         assert(false && "Unexpected unknown constraint");

llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

 
 TargetLowering::ConstraintType
 TargetLowering::getConstraintType(StringRef Constraint) const {
   unsigned S = Constraint.size();
 
   if (S == 1) {
     switch (Constraint[0]) {
     default: break;
-    case 'r': return C_RegisterClass;
+    case 'r':
+      return C_RegisterClass;
     case 'm': // memory
     case 'o': // offsetable
     case 'V': // not offsetable
       return C_Memory;
-    case 'i': // Simple Integer or Relocatable Constant
     case 'n': // Simple Integer
     case 'E': // Floating Point Constant
     case 'F': // Floating Point Constant
+      return C_Immediate;
+    case 'i': // Simple Integer or Relocatable Constant
     case 's': // Relocatable Constant
     case 'p': // Address.
     case 'X': // Allow ANY value.
     case 'I': // Target registers.
     case 'J':
     case 'K':
     case 'L':
     case 'M':
TargetLowering::ParseConstraints(const DataLayout &DL,
   }
 
   return ConstraintOperands;
 }
 
 /// Return an integer indicating how general CT is.
 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
   switch (CT) {
+  case TargetLowering::C_Immediate:
   case TargetLowering::C_Other:
   case TargetLowering::C_Unknown:
     return 0;
   case TargetLowering::C_Register:
     return 1;
   case TargetLowering::C_RegisterClass:
     return 2;
   case TargetLowering::C_Memory:
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
   TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
   int BestGenerality = -1;
 
   // Loop over the options, keeping track of the most general one.
   for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
     TargetLowering::ConstraintType CType =
       TLI.getConstraintType(OpInfo.Codes[i]);
 
-    // If this is an 'other' constraint, see if the operand is valid for it.
-    // For example, on X86 we might have an 'rI' constraint.  If the operand
-    // is an integer in the range [0..31] we want to use I (saving a load
-    // of a register), otherwise we must use 'r'.
-    if (CType == TargetLowering::C_Other && Op.getNode()) {
+    // If this is an 'other' or 'immediate' constraint, see if the operand is
+    // valid for it. For example, on X86 we might have an 'rI' constraint. If
+    // the operand is an integer in the range [0..31] we want to use I (saving a
+    // load of a register), otherwise we must use 'r'.
+    if ((CType == TargetLowering::C_Other ||
+         CType == TargetLowering::C_Immediate) && Op.getNode()) {
       assert(OpInfo.Codes[i].size() == 1 &&
              "Unhandled multi-letter 'other' constraint");
       std::vector<SDValue> ResultOps;
       TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
                                        ResultOps, *DAG);
       if (!ResultOps.empty()) {
         BestType = CType;
         BestIdx = i;

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 AArch64TargetLowering::ConstraintType
 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default:
       break;
-    case 'z':
-      return C_Other;
     case 'x':
     case 'w':
       return C_RegisterClass;
     // An address with a single base register. Due to the way we
     // currently handle addresses it is the same as 'r'.
     case 'Q':
       return C_Memory;
+    case 'I':
+    case 'J':
+    case 'K':
+    case 'L':
+    case 'M':
+    case 'N':
+    case 'Y':
+    case 'Z':
+      return C_Immediate;
+    case 'z':
     case 'S': // A symbolic address
       return C_Other;
     }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
 /// Examine constraint type and operand type and determine a weight value.

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

const char *ARMTargetLowering::LowerXConstraint(EVT ConstraintVT) const {
 
   return "r";
 }
 
 /// getConstraintType - Given a constraint letter, return the type of
 /// constraint it is for this target.
 ARMTargetLowering::ConstraintType
 ARMTargetLowering::getConstraintType(StringRef Constraint) const {
-  if (Constraint.size() == 1) {
+  unsigned S = Constraint.size();
+  if (S == 1) {
     switch (Constraint[0]) {
     default:  break;
     case 'l': return C_RegisterClass;
     case 'w': return C_RegisterClass;
     case 'h': return C_RegisterClass;
     case 'x': return C_RegisterClass;
     case 't': return C_RegisterClass;
-    case 'j': return C_Other; // Constant for movw.
-      // An address with a single base register. Due to the way we
-      // currently handle addresses it is the same as an 'r' memory constraint.
+    case 'j': return C_Immediate; // Constant for movw.
     case 'Q': return C_Memory;
     }
-  } else if (Constraint.size() == 2) {
+  } else if (S == 2) {
     switch (Constraint[0]) {
     default: break;
     case 'T': return C_RegisterClass;
     // All 'U+' constraints are addresses.
     case 'U': return C_Memory;
     }
   }
   return TargetLowering::getConstraintType(Constraint);

llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp

 //  Inline Asm Support
 //===----------------------------------------------------------------------===//
 
 AVRTargetLowering::ConstraintType
 AVRTargetLowering::getConstraintType(StringRef Constraint) const {
   if (Constraint.size() == 1) {
     // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
     switch (Constraint[0]) {
+    default:
+      break;
     case 'a': // Simple upper registers
     case 'b': // Base pointer registers pairs
     case 'd': // Upper register
     case 'l': // Lower registers
     case 'e': // Pointer register pairs
     case 'q': // Stack pointer register
     case 'r': // Any register
     case 'w': // Special upper register pairs
if (Constraint.size() == 1) {
     case 'J': // 6-bit negative integer constant
     case 'K': // Integer constant (Range: 2)
     case 'L': // Integer constant (Range: 0)
     case 'M': // 8-bit integer constant
     case 'N': // Integer constant (Range: -1)
     case 'O': // Integer constant (Range: 8, 16, 24)
     case 'P': // Integer constant (Range: 1)
     case 'R': // Integer constant (Range: -6 to 5)x
-      return C_Other;
-    default:
-      break;
+      return C_Immediate;
     }
   }
 
   return TargetLowering::getConstraintType(Constraint);
 }
 
 unsigned
 AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {

llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp

 RISCVTargetLowering::ConstraintType
 RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default:
       break;
     case 'f':
       return C_RegisterClass;
+    case 'I':
+    case 'J':
+    case 'K':
+      return C_Immediate;
     }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
 std::pair<unsigned, const TargetRegisterClass *>
 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                                   StringRef Constraint,

llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::getConstraintType(StringRef Constraint) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default:  break;
     case 'r':
     case 'f':
     case 'e':
       return C_RegisterClass;
     case 'I': // SIMM13
-      return C_Other;
+      return C_Immediate;
     }
   }
 
   return TargetLowering::getConstraintType(Constraint);
 }
 
 TargetLowering::ConstraintWeight SparcTargetLowering::
 getSingleConstraintMatchWeight(AsmOperandInfo &info,

llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp

if (Constraint.size() == 1) {
     case 'm': // Equivalent to 'T'.
       return C_Memory;
 
     case 'I': // Unsigned 8-bit constant
     case 'J': // Unsigned 12-bit constant
     case 'K': // Signed 16-bit constant
     case 'L': // Signed 20-bit displacement (on all targets we support)
     case 'M': // 0x7fffffff
-      return C_Other;
+      return C_Immediate;
 
     default:
       break;
     }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

if (Constraint.size() == 1) {
     case 'd':
     case 'S':
     case 'D':
     case 'A':
       return C_Register;
     case 'I':
     case 'J':
     case 'K':
-    case 'L':
-    case 'M':
     case 'N':
     case 'G':
+    case 'L':
+    case 'M':
+      return C_Immediate;
     case 'C':
     case 'e':
     case 'Z':
       return C_Other;
     default:
       break;
     }
   }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-I.ll

 ; RUN: not llc -mtriple=arm64-eabi < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'I'
+; CHECK-ERRORS: error: value out of range for constraint 'I'
 
 define i32 @constraint_I(i32 %i, i32 %j) nounwind ssp {
 entry:
   %0 = tail call i32 asm sideeffect "add $0, $1, $2", "=r,r,I"(i32 %i, i32 4097) nounwind
   ret i32 %0
 }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-J.ll

 ; RUN: not llc -mtriple=arm64-eabi < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'J'
+; CHECK-ERRORS: error: value out of range for constraint 'J'
 
 define i32 @constraint_J(i32 %i, i32 %j) nounwind ssp {
 entry:
   %0 = tail call i32 asm sideeffect "sub $0, $1, $2", "=r,r,J"(i32 %i, i32 2) nounwind
   ret i32 %0
 }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-K.ll

 ; RUN: not llc -mtriple=arm64-eabi < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'K'
+; CHECK-ERRORS: error: value out of range for constraint 'K'
 
 define i32 @constraint_K(i32 %i, i32 %j) nounwind {
 entry:
   %0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,K"(i32 %i, i32 -1) nounwind
   ret i32 %0
 }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-L.ll

 ; RUN: not llc -mtriple=arm64-eabi < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'L'
+; CHECK-ERRORS: error: value out of range for constraint 'L'
 
 define i32 @constraint_L(i32 %i, i32 %j) nounwind {
 entry:
   %0 = tail call i32 asm sideeffect "eor $0, $1, $2", "=r,r,L"(i32 %i, i64 -1) nounwind
   ret i32 %0
 }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-M.ll

 ; RUN: not llc -mtriple=arm64-eabi < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'M'
+; CHECK-ERRORS: error: value out of range for constraint 'M'
 
 define i32 @constraint_M(i32 %i, i32 %j) nounwind {
 entry:
   %0 = tail call i32 asm sideeffect "movk $0, $1", "=r,M"(i32 305418240) nounwind
   ret i32 %0
 }

llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm-error-N.ll

 ; RUN: not llc -mtriple=arm64-eabi < %s  2> %t
 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
 
 ; Check for at least one invalid constant.
-; CHECK-ERRORS: error: invalid operand for inline asm constraint 'N'
+; CHECK-ERRORS: error: value out of range for constraint 'N'
 
 define i32 @constraint_N(i32 %i, i32 %j) nounwind {
 entry:
   %0 = tail call i32 asm sideeffect "movk $0, $1", "=r,N"(i64 1311761352401879040) nounwind
   ret i32 %0
 }

llvm/trunk/test/CodeGen/RISCV/inline-asm-invalid.ll

 ; RUN: not llc -mtriple=riscv32 < %s 2>&1 | FileCheck %s
 ; RUN: not llc -mtriple=riscv64 < %s 2>&1 | FileCheck %s
 
 define void @constraint_I() {
-; CHECK: error: invalid operand for inline asm constraint 'I'
+; CHECK: error: value out of range for constraint 'I'
   tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 2048)
-; CHECK: error: invalid operand for inline asm constraint 'I'
+; CHECK: error: value out of range for constraint 'I'
   tail call void asm sideeffect "addi a0, a0, $0", "I"(i32 -2049)
   ret void
 }
 
 define void @constraint_J() {
-; CHECK: error: invalid operand for inline asm constraint 'J'
+; CHECK: error: value out of range for constraint 'J'
   tail call void asm sideeffect "addi a0, a0, $0", "J"(i32 1)
   ret void
 }
 
 define void @constraint_K() {
-; CHECK: error: invalid operand for inline asm constraint 'K'
+; CHECK: error: value out of range for constraint 'K'
   tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 32)
-; CHECK: error: invalid operand for inline asm constraint 'K'
+; CHECK: error: value out of range for constraint 'K'
   tail call void asm sideeffect "csrwi mstatus, $0", "K"(i32 -1)
   ret void
 }
 
 define void @constraint_f() nounwind {
 ; CHECK: error: couldn't allocate input reg for constraint 'f'
   tail call void asm "fadd.s fa0, fa0, $0", "f"(float 0.0)
 ; CHECK: error: couldn't allocate input reg for constraint 'f'
   tail call void asm "fadd.d fa0, fa0, $0", "f"(double 0.0)
   ret void
 }

llvm/trunk/test/CodeGen/X86/inline-asm-bad-constraint-n.ll

 ; RUN: not llc -mtriple=i686-- -no-integrated-as < %s 2>&1 | FileCheck %s
 
 @x = global i32 0, align 4
 
-;CHECK: error: invalid operand for inline asm constraint 'n'
+; CHECK: error: constraint 'n' expects an integer constant expression
 define void @foo() {
   %a = getelementptr i32, i32* @x, i32 1
   call void asm sideeffect "foo $0", "n"(i32* %a) nounwind
   ret void
 }

llvm/trunk/test/CodeGen/X86/inline-asm-e-constraint.ll

+; RUN: not llc -mtriple=x86_64-unknown-unknown -no-integrated-as < %s 2>&1 | FileCheck %s
+
+%struct.s = type { i32, i32 }
+
+@pr40890.s = internal global %struct.s zeroinitializer, align 4
+
+; CHECK: error: invalid operand for inline asm constraint 'e'
+; CHECK: error: invalid operand for inline asm constraint 'e'
+
+define void @pr40890() {
+entry:
+  ; This pointer cannot be used as an integer constant expression.
+  tail call void asm sideeffect "\0A#define GLOBAL_A abcd$0\0A", "e,~{dirflag},~{fpsr},~{flags}"(i32* getelementptr inbounds (%struct.s, %struct.s* @pr40890.s, i64 0, i32 0))
+  ; Floating-point is also not okay.
+  tail call void asm sideeffect "\0A#define PI abcd$0\0A", "e,~{dirflag},~{fpsr},~{flags}"(float 0x40091EB860000000)
+  ret void
+}

llvm/trunk/test/CodeGen/X86/inline-asm-imm-out-of-range.ll

+; RUN: not llc -mtriple=i686-- -no-integrated-as < %s 2>&1 | FileCheck %s
+
+; CHECK: error: value out of range for constraint 'I'
+define void @foo() {
+  call void asm sideeffect "foo $0", "I"(i32 42)
+  ret void
+}

llvm/trunk/test/CodeGen/X86/inline-asm-n-constraint.ll

+; RUN: llc -mtriple=x86_64-unknown-unknown -no-integrated-as < %s 2>&1 | FileCheck %s
+
+@x = global i32 0, align 4
+
+define void @foo() {
+; CHECK-LABEL: foo:
+  call void asm sideeffect "foo $0", "n"(i32 42) nounwind
+; CHECK:      #APP
+; CHECK-NEXT: foo    $42
+; CHECK-NEXT: #NO_APP
+  ret void
+; CHECK-NEXT: retq
+}