[ARM] Add ACLE feature macros for MVE.

[SjoerdMeijer]

Summary

If MVE is present at all, then the macro __ARM_FEATURE_MVE is defined
to a value which has bit 0 set for integer MVE, and bit 1 set for
floating-point MVE.

(Floating-point MVE implies integer MVE, so if this macro is defined
at all then it will be set to 1 or 3, never 2.)

[t.p.northover]

Could you add some tests?

[SjoerdMeijer]

Added tests

[ostannard]

clang/lib/Basic/Targets/ARM.cpp

465

Does this also need to set FPU and HasLegalHalfType?

[SjoerdMeijer]

clang/lib/Basic/Targets/ARM.cpp

465

Yep, thanks for catching this one, will fix this.

[SjoerdMeijer]

Set FullFP16 for +mve.fp

[ostannard]

clang/lib/Basic/Targets/ARM.cpp

465

What about FPU? mve.fp requires that the FPU is also enabled, so we should also get the __ARM_FPV5__ macro (unless we're adding a new one for the v8.1M FPU?).

[SjoerdMeijer]

Yep, sorry, missed that one.

[ostannard]

LGTM

[SjoerdMeijer]

Thanks for reviewing!

[thakis]

The test is failing on some bots, e.g. http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/13430/steps/test-stage1-compiler/logs/stdio

/home/buildslave/buildslave1a/clang-with-lto-ubuntu/llvm.src/tools/clang/test/Preprocessor/arm-target-features.c:762:20: error: CHECK-V81M-MVE: expected string not found in input
// CHECK-V81M-MVE: #define __ARM_FEATURE_MVE 1
                   ^
<stdin>:16:1: note: scanning from here
#define __ARM_FEATURE_FMA 1
^
<stdin>:20:1: note: possible intended match here
#define __ARM_FEATURE_MVE 3
^

[dmgreen]

Hello. Hopefully fixed in rC362814!

clang/lib/Basic/Targets/ARM.h

class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
   enum FPUMode {
     VFP2FPU = (1 << 0),
     VFP3FPU = (1 << 1),
     VFP4FPU = (1 << 2),
     NeonFPU = (1 << 3),
     FPARMV8 = (1 << 4)
   };
 
+  enum MVEMode {
+      MVE_INT = (1 << 0),
+      MVE_FP  = (1 << 1)
+  };
+
   // Possible HWDiv features.
   enum HWDivMode { HWDivThumb = (1 << 0), HWDivARM = (1 << 1) };
 
   static bool FPUModeIsVFP(FPUMode Mode) {
     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
   }
 
   static const TargetInfo::GCCRegAlias GCCRegAliases[];
   static const char *const GCCRegNames[];
 
   std::string ABI, CPU;
 
   StringRef CPUProfile;
   StringRef CPUAttr;
 
   enum { FP_Default, FP_VFP, FP_Neon } FPMath;
 
   llvm::ARM::ISAKind ArchISA;
   llvm::ARM::ArchKind ArchKind = llvm::ARM::ArchKind::ARMV4T;
   llvm::ARM::ProfileKind ArchProfile;
   unsigned ArchVersion;
 
   unsigned FPU : 5;
+  unsigned MVE : 2;
 
   unsigned IsAAPCS : 1;
   unsigned HWDiv : 2;
 
   // Initialized via features.
   unsigned SoftFloat : 1;
   unsigned SoftFloatABI : 1;
 
class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo {
   void setArchInfo();
   void setArchInfo(llvm::ARM::ArchKind Kind);
 
   void setAtomic();
 
   bool isThumb() const;
   bool supportsThumb() const;
   bool supportsThumb2() const;
+  bool hasMVE() const;
+  bool hasMVEFloat() const;
 
   StringRef getCPUAttr() const;
   StringRef getCPUProfile() const;
 
 public:
   ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts);
 
   StringRef getABI() const override;

clang/lib/Basic/Targets/ARM.cpp

if (ShouldUseInlineAtomic)
       MaxAtomicInlineWidth = 32;
   } else {
     MaxAtomicPromoteWidth = 64;
     if (ShouldUseInlineAtomic)
       MaxAtomicInlineWidth = 64;
   }
 }
 
+bool ARMTargetInfo::hasMVE() const {
+  return ArchKind == llvm::ARM::ArchKind::ARMV8_1MMainline && MVE != 0;
+}
+
+bool ARMTargetInfo::hasMVEFloat() const {
+  return hasMVE() && (MVE & MVE_FP);
+}
+
 bool ARMTargetInfo::isThumb() const {
   return ArchISA == llvm::ARM::ISAKind::THUMB;
 }
 
 bool ARMTargetInfo::supportsThumb() const {
   return CPUAttr.count('T') || ArchVersion >= 6;
 }
 
for (const auto &Feature : Features) {
     } else if (Feature == "+strict-align") {
       Unaligned = 0;
     } else if (Feature == "+fp16") {
       HW_FP |= HW_FP_HP;
     } else if (Feature == "+fullfp16") {
       HasLegalHalfType = true;
     } else if (Feature == "+dotprod") {
       DotProd = true;
+    } else if (Feature == "+mve") {
+      DSP = 1;
+      MVE |= MVE_INT;
+    } else if (Feature == "+mve.fp") {
+      DSP = 1;
+      HasLegalHalfType = true;
+      MVE |= MVE_INT | MVE_FP;
+      HW_FP |= HW_FP_SP | HW_FP_HP;
     }
   }
 
   switch (ArchVersion) {
   case 6:
     if (ArchProfile == llvm::ARM::ProfileKind::M)
       LDREX = 0;
     else if (ArchKind == llvm::ARM::ArchKind::ARMV6K)
return llvm::StringSwitch<bool>(Feature)
       .Case("arm", true)
       .Case("aarch32", true)
       .Case("softfloat", SoftFloat)
       .Case("thumb", isThumb())
       .Case("neon", (FPU & NeonFPU) && !SoftFloat)
       .Case("vfp", FPU && !SoftFloat)
       .Case("hwdiv", HWDiv & HWDivThumb)
       .Case("hwdiv-arm", HWDiv & HWDivARM)
+      .Case("mve", hasMVE())
       .Default(false);
 }
 
 bool ARMTargetInfo::isValidCPUName(StringRef Name) const {
   return Name == "generic" ||
          llvm::ARM::parseCPUArch(Name) != llvm::ARM::ArchKind::INVALID;
 }
 
if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
     Builder.defineMacro("__ARM_NEON", "1");
     Builder.defineMacro("__ARM_NEON__");
     // current AArch32 NEON implementations do not support double-precision
     // floating-point even when it is present in VFP.
     Builder.defineMacro("__ARM_NEON_FP",
                         "0x" + Twine::utohexstr(HW_FP & ~HW_FP_DP));
   }
 
+  if (hasMVE()) {
+    Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? "3" : "1");
+  }
+
   Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
                       Twine(Opts.WCharSize ? Opts.WCharSize : 4));
 
   Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4");
 
   // CMSE
   if (ArchVersion == 8 && ArchProfile == llvm::ARM::ProfileKind::M)
     Builder.defineMacro("__ARM_FEATURE_CMSE", Opts.Cmse ? "3" : "1");

clang/test/Preprocessor/arm-target-features.c

 
 // Test whether predefines are as expected when targeting krait (softfp FP as default).
 // RUN: %clang -target armv7-eabi -mcpu=krait -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=KRAIT-ALLOW-FP-INSTR %s
 // RUN: %clang -target armv7-eabi -mthumb -mcpu=krait -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=KRAIT-ALLOW-FP-INSTR %s
 // KRAIT-ALLOW-FP-INSTR:#define __ARM_ARCH_EXT_IDIV__ 1
 // KRAIT-ALLOW-FP-INSTR:#define __ARM_FEATURE_DSP 1
 // KRAIT-ALLOW-FP-INSTR:#define  __ARM_VFPV4__ 1
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V81M %s
+// CHECK-V81M: #define __ARM_ARCH 8
+// CHECK-V81M: #define __ARM_ARCH_8_1M_MAIN__ 1
+// CHECK-V81M: #define __ARM_ARCH_ISA_THUMB 2
+// CHECK-V81M: #define __ARM_ARCH_PROFILE 'M'
+// CHECK-V81M-NOT: #define __ARM_FEATURE_DSP
+// CHECK-V81M-NOT: #define __ARM_FEATURE_MVE
+// CHECK-V81M-NOT: #define __ARM_FEATURE_SIMD32
+
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V81M-MVE %s
+// CHECK-V81M-MVE: #define __ARM_FEATURE_DSP 1
+// CHECK-V81M-MVE: #define __ARM_FEATURE_MVE 1
+// CHECK-V81M-MVE: #define __ARM_FEATURE_SIMD32 1
+
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V81M-MVE-FP %s
+// CHECK-V81M-MVE-FP: #define __ARM_FEATURE_DSP 1
+// CHECK-V81M-MVE-FP: #define __ARM_FEATURE_FP16_SCALAR_ARITHMETIC 1
+// CHECK-V81M-MVE-FP: #define __ARM_FEATURE_MVE 3
+// CHECK-V81M-MVE-FP: #define __ARM_FEATURE_SIMD32 1
+
 // RUN: %clang -target armv8.1a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V81A %s
 // CHECK-V81A: #define __ARM_ARCH 8
 // CHECK-V81A: #define __ARM_ARCH_8_1A__ 1
 // CHECK-V81A: #define __ARM_ARCH_PROFILE 'A'
 // CHECK-V81A: #define __ARM_FEATURE_QRDMX 1
 // CHECK-V81A: #define __ARM_FP 0xe
 
 // RUN: %clang -target armv8.2a-none-none-eabi -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-V82A %s