This provides the low-level support to start using MVE vector types in
LLVM IR, loading and storing them, passing them to __asm__ statements
containing hand-written MVE vector instructions, and *if* you have the
hard-float ABI turned on, using them as function parameters.
(In the soft-float ABI, vector types are passed in integer registers,
and combining all those 32-bit integers into a q-reg requires support
for selection DAG nodes like insert_vector_elt and build_vector which
aren't implemented yet for MVE.)
Specifically, this commit adds support for:
- spills, reloads and register moves for MVE vector registers
- ditto for the VPT predication mask that lives in VPR.P0
- make all the MVE vector types legal in ISel, and provide selection DAG patterns for BITCAST, LOAD and STORE
- make loads and stores of scalar FP types conditional on hasFPRegs() rather than hasVFP2Base(). As a result a few existing tests needed their llc command lines updating to use -mattr=-fpregs as their method of turning off all hardware FP support.