[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.

[niravd]

Summary

A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.

Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.

CodeGen tests with non-reordering changes:

X86/aligned-variadic.ll -- memory-based add folded into stored leaq
value.

X86/constant-combiners.ll -- Optimizes out overlap between stores.

X86/pr40631_deadstore_elision -- folds constant byte store into
preceding quad word constant store.

[courbet]

X86/constant-combiners.ll -- Optimizes out overlap between stores.

I don't see that one.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1710

"If the sole user of this node is a token factor, we should ..."

[alexey.zhikhar]

@niravd Hi Nirav, my team and I discovered a compile time regression due to this patch. I submitted a bug report for it, we would really appreciate if you could take a look at it:

https://github.com/llvm/llvm-project/issues/52858

Thank you in advance.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N->getNumOperands() == 2) {
     if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
       return N->getOperand(1);
   }
 
   // Don't simplify token factors if optnone.
   if (OptLevel == CodeGenOpt::None)
     return SDValue();
 
+  // If this is used only a single token factor, we should make sure we have a
+  // chance to merge them together. This prevents TF chains from inhibiting
+  // optimizations.
+  if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
+    AddToWorklist(*(N->use_begin()));
+
   SmallVector<SDNode *, 8> TFs;     // List of token factors to visit.
   SmallVector<SDValue, 8> Ops;      // Ops for replacing token factor.
   SmallPtrSet<SDNode*, 16> SeenOps;
   bool Changed = false;             // If we should replace this token factor.
 
   // Start out with this token factor.
   TFs.push_back(N);
 

llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll

 ; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 define win64cc void @pass_va(i32 %count, ...) nounwind {
 entry:
 ; CHECK: str     x30, [sp, #-80]!
 ; CHECK: add     x8, sp, #24
 ; CHECK: add     x0, sp, #24
-; CHECK: stp     x6, x7, [sp, #64]
-; CHECK: stp     x4, x5, [sp, #48]
-; CHECK: stp     x2, x3, [sp, #32]
-; CHECK: str     x1, [sp, #24]
+; CHECK: stp     x1, x2, [sp, #24]
+; CHECK: stp     x3, x4, [sp, #40]
+; CHECK: stp     x5, x6, [sp, #56]
+; CHECK: str     x7, [sp, #72]
 ; CHECK: str     x8, [sp, #8]
 ; CHECK: bl      other_func
 ; CHECK: ldr     x30, [sp], #80
 ; CHECK: ret
   %ap = alloca i8*, align 8
   %ap1 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap1)
   %ap2 = load i8*, i8** %ap, align 8

llvm/test/CodeGen/AArch64/addr-of-ret-addr.ll

entry:
   %call = call i32 %0(i8* %2, i8* %1)
   %add = add nsw i32 %call, 1
   ret i32 %add
 
 ; CHECK-LABEL: bar
 ; CHECK: sub sp, sp, #96
 ; CHECK: stp x29, x30, [sp, #16]
 ; CHECK: add x29, sp, #16
-; CHECK: str x1, [x29, #24]
+; CHECK: stp x1, x2, [x29, #24]
 ; CHECK: add x1, x29, #8
 ; CHECK: ldp x29, x30, [sp, #16]
 ; CHECK: add sp, sp, #96
 }

llvm/test/CodeGen/AArch64/alloca.ll

 ; CHECK-NOFP-AARCH64: add     x29, sp, #64
 ; CHECK-NOFP-AARCH64: sub     [[TMP:x[0-9]+]], x29, #64
 ; CHECK-NOFP-AARCH64: add     x8, [[TMP]], #0
 
 
 ; CHECK: stp     x29, x30, [sp, #-16]!
 ; CHECK: mov     x29, sp
 ; CHECK: sub     sp, sp, #192
-; CHECK: stp     q6, q7, [x29, #-96]
+; CHECK-DAG: stp     q6, q7, [x29, #-96]
 ; [...]
-; CHECK: stp     q0, q1, [x29, #-192]
+; CHECK-DAG: stp     q0, q1, [x29, #-192]
 
-; CHECK: stp     x6, x7, [x29, #-16]
+; CHECK-DAG: stp     x5, x6, [x29, #-24]
 ; [...]
-; CHECK: stp     x2, x3, [x29, #-48]
+; CHECK-DAG: stp     x1, x2, [x29, #-56]
 
 ; CHECK-NOFP-ARM64: stp     x29, x30, [sp, #-16]!
 ; CHECK-NOFP-ARM64: mov     x29, sp
 ; CHECK-NOFP-ARM64: sub     sp, sp, #64
-; CHECK-NOFP-ARM64: stp     x6, x7, [x29, #-16]
+; CHECK-NOFP-ARM64-DAG: stp     x5, x6, [x29, #-24]
 ; [...]
-; CHECK-NOFP-ARM64: stp     x4, x5, [x29, #-32]
+; CHECK-NOFP-ARM64-DAG: stp     x3, x4, [x29, #-40]
 ; [...]
-; CHECK-NOFP-ARM64: stp     x2, x3, [x29, #-48]
+; CHECK-NOFP-ARM64-DAG: stp     x1, x2, [x29, #-56]
 ; [...]
 ; CHECK-NOFP-ARM64: mov     x8, sp
 
   %addr = alloca i8, i64 %n
 
   call void @use_addr(i8* %addr)
 ; CHECK: bl use_addr
 

llvm/test/CodeGen/AArch64/arm64-memcpy-inline.ll

 @.str4 = private unnamed_addr constant [18 x i8] c"DHRYSTONE PROGR  \00", align 1
 @.str5 = private unnamed_addr constant [7 x i8] c"DHRYST\00", align 1
 @.str6 = private unnamed_addr constant [14 x i8] c"/tmp/rmXXXXXX\00", align 1
 @spool.splbuf = internal global [512 x i8] zeroinitializer, align 16
 
 define i32 @t0() {
 entry:
 ; CHECK-LABEL: t0:
-; CHECK: ldur [[REG0:w[0-9]+]], [x[[BASEREG:[0-9]+]], #7]
-; CHECK: stur [[REG0]], [x[[BASEREG2:[0-9]+]], #7]
-; CHECK: ldr [[REG2:x[0-9]+]],
-; CHECK: str [[REG2]],
+; CHECK-DAG: ldur [[REG0:w[0-9]+]], [x[[BASEREG:[0-9]+]], #7]
+; CHECK-DAG: stur [[REG0]], [x[[BASEREG2:[0-9]+]], #7]
+; CHECK-DAG: ldr [[REG2:x[0-9]+]],
+; CHECK-DAG: str [[REG2]],
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* align 8 getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i1 false)
   ret i32 0
 }
 
 define void @t1(i8* nocapture %C) nounwind {
 entry:
 ; CHECK-LABEL: t1:
 ; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]]

 ; CHECK: str [[REG8]], [x0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i1 false)
   ret void
 }
 
 define void @t6() nounwind {
 entry:
 ; CHECK-LABEL: t6:
-; CHECK: ldur [[REG9:x[0-9]+]], [x{{[0-9]+}}, #6]
-; CHECK: stur [[REG9]], [x{{[0-9]+}}, #6]
-; CHECK: ldr
-; CHECK: str
+; CHECK-DAG: ldur [[REG9:x[0-9]+]], [x{{[0-9]+}}, #6]
+; CHECK-DAG: stur [[REG9]], [x{{[0-9]+}}, #6]
+; CHECK-DAG: ldr
+; CHECK-DAG: str
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i1 false)
   ret void
 }
 
 %struct.Foo = type { i32, i32, i32, i32 }
 
 define void @t7(%struct.Foo* nocapture %a, %struct.Foo* nocapture %b) nounwind {
 entry:

llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll

 ; RUN: llc -verify-machineinstrs -mtriple=arm64-linux-gnu -pre-RA-sched=linearize -enable-misched=false -disable-post-ra < %s | FileCheck %s
 
 %va_list = type {i8*, i8*, i8*, i32, i32}
 
 @var = global %va_list zeroinitializer, align 8
 
 declare void @llvm.va_start(i8*)
 
 define void @test_simple(i32 %n, ...) {
 ; CHECK-LABEL: test_simple:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
 ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
 
 ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
 ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
-; CHECK: stp x1, x2, [sp, #[[GR_BASE:[0-9]+]]]
+; CHECK-DAG: stp x6, x7, [sp, #
 ; ... omit middle ones ...
-; CHECK: str x7, [sp, #
+; CHECK-DAG: str x1, [sp, #[[GR_BASE:[0-9]+]]]
 
-; CHECK: stp q0, q1, [sp]
+; CHECK-DAG: stp q0, q1, [sp]
 ; ... omit middle ones ...
-; CHECK: stp q6, q7, [sp, #
+; CHECK-DAG: stp q6, q7, [sp, #
 
 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]]
 
 ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
 ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56
 ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
 
 ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp

 define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
 ; CHECK-LABEL: test_fewargs:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
 ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]]
 
 ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var
 ; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var
 
-; CHECK: stp x3, x4, [sp, #[[GR_BASE:[0-9]+]]]
+; CHECK-DAG: stp x6, x7, [sp, #
 ; ... omit middle ones ...
-; CHECK: str x7, [sp, #
+; CHECK-DAG: str x3, [sp, #[[GR_BASE:[0-9]+]]]
 
-; CHECK: stp q1, q2, [sp]
+; CHECK-DAG: stp q6, q7, [sp, #80]
 ; ... omit middle ones ...
-; CHECK: str q7, [sp, #
+; CHECK-DAG: str q1, [sp]
 
 ; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]]
 
 ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]]
 ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40
 ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8]
 
 ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp
; CHECK: str [[STACK]], [x[[VAR]]]
 
   ret void
 }
 
 ; If there are non-variadic arguments on the stack (here two i64s) then the
 ; __stack field should point just past them.
 define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) {
 ; CHECK-LABEL: test_offsetstack:
-; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #-80]!
-; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #96
-; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var
-; CHECK: str [[STACK_TOP]], [x[[VAR]]]
+
+; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #48]
+; CHECK-DAG: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16]
+; CHECK-DAG: str {{q[0-9]+}}, [sp]
+; CHECK-DAG: add [[STACK_TOP:x[0-9]+]], sp, #96
+; CHECK-DAG: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var
+; CHECK-DAG: str [[STACK_TOP]], [x[[VAR]]]
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
   ret void
 }
 
 declare void @llvm.va_end(i8*)
 

llvm/test/CodeGen/AArch64/win64_vararg.ll

 ; RUN: llc < %s -mtriple=aarch64-pc-win32 | FileCheck %s
 
 define void @pass_va(i32 %count, ...) nounwind {
 entry:
 ; CHECK: str     x30, [sp, #-80]!
 ; CHECK: add     x8, sp, #24
 ; CHECK: add     x0, sp, #24
-; CHECK: stp     x6, x7, [sp, #64]
-; CHECK: stp     x4, x5, [sp, #48]
-; CHECK: stp     x2, x3, [sp, #32]
-; CHECK: str     x1, [sp, #24]
+; CHECK: stp     x1, x2, [sp, #24]
+; CHECK: stp     x3, x4, [sp, #40]
+; CHECK: stp     x5, x6, [sp, #56]
+; CHECK: str     x7, [sp, #72]
 ; CHECK: str     x8, [sp, #8]
 ; CHECK: bl      other_func
 ; CHECK: ldr     x30, [sp], #80
 ; CHECK: ret
   %ap = alloca i8*, align 8
   %ap1 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap1)
   %ap2 = load i8*, i8** %ap, align 8
entry:
   call void @llvm.va_start(i8* %ap1)
   %ap2 = load i8*, i8** %ap, align 8
   ret i8* %ap2
 }
 
 ; CHECK-LABEL: copy1:
 ; CHECK: sub     sp, sp, #80
 ; CHECK: add     x8, sp, #24
-; CHECK: stp     x6, x7, [sp, #64]
-; CHECK: stp     x4, x5, [sp, #48]
-; CHECK: stp     x2, x3, [sp, #32]
-; CHECK: str     x1, [sp, #24]
+; CHECK: stp     x1, x2, [sp, #24]
+; CHECK: stp     x3, x4, [sp, #40]
+; CHECK: stp     x5, x6, [sp, #56]
+; CHECK: str     x7, [sp, #72]
 ; CHECK: stp     x8, x8, [sp], #80
 ; CHECK: ret
 define void @copy1(i64 %a0, ...) nounwind {
 entry:
   %ap = alloca i8*, align 8
   %cp = alloca i8*, align 8
   %ap1 = bitcast i8** %ap to i8*
   %cp1 = bitcast i8** %cp to i8*

 ; CHECK: str     x21, [sp, #-96]!
 ; CHECK: stp     x19, x20, [sp, #16]
 ; CHECK: stp     x29, x30, [sp, #32]
 ; CHECK: add     x29, sp, #32
 ; CHECK: add     x8, x29, #24
 ; CHECK: mov     x19, x2
 ; CHECK: mov     x20, x1
 ; CHECK: mov     x21, x0
-; CHECK: stp     x6, x7, [x29, #48]
-; CHECK: stp     x4, x5, [x29, #32]
-; CHECK: str     x3, [x29, #24]
+; CHECK: stp     x3, x4, [x29, #24]
+; CHECK: stp     x5, x6, [x29, #40]
+; CHECK: str     x7, [x29, #56]
 ; CHECK: str     x8, [sp, #8]
 ; CHECK: bl      __local_stdio_printf_options
 ; CHECK: ldr     x8, [x0]
 ; CHECK: add     x5, x29, #24
 ; CHECK: mov     x1, x21
 ; CHECK: mov     x2, x20
 ; CHECK: orr     x0, x8, #0x2
 ; CHECK: mov     x3, x19

 ; CHECK: add     x29, sp, #48
 ; CHECK: add     x8, x29, #16
 ; CHECK: stur    x8, [x29, #-40]
 ; CHECK: mov     w8, w0
 ; CHECK: add     x8, x8, #15
 ; CHECK: lsr     x15, x8, #4
 ; CHECK: mov     x19, x1
 ; CHECK: mov     [[REG2:x[0-9]+]], sp
-; CHECK: stp     x6, x7, [x29, #48]
-; CHECK: stp     x4, x5, [x29, #32]
 ; CHECK: stp     x2, x3, [x29, #16]
+; CHECK: stp     x4, x5, [x29, #32]
+; CHECK: stp     x6, x7, [x29, #48]
 ; CHECK: bl      __chkstk
 ; CHECK: mov     x8, sp
 ; CHECK: sub     [[REG:x[0-9]+]], x8, x15, lsl #4
 ; CHECK: mov     sp, [[REG]]
 ; CHECK: ldur    [[REG3:x[0-9]+]], [x29, #-40]
 ; CHECK: sxtw    [[REG4:x[0-9]+]], w0
 ; CHECK: bl      __local_stdio_printf_options
 ; CHECK: ldr     x8, [x0]

 ; CHECK-DAG: sub     sp,  sp, #96
 ; CHECK-DAG: str     x21, [sp, #16]
 ; CHECK-DAG: stp     x19, x20, [sp, #24]
 ; CHECK-DAG: str     x30, [sp, #40]
 ; CHECK-DAG: add     x8, sp, #56
 ; CHECK-DAG: mov     x19, x2
 ; CHECK-DAG: mov     x20, x1
 ; CHECK-DAG: mov     x21, x0
-; CHECK-DAG: stp     x6, x7, [sp, #80]
-; CHECK-DAG: stp     x4, x5, [sp, #64]
-; CHECK-DAG: str     x3, [sp, #56]
+; CHECK-DAG: stp     x3, x4, [sp, #56]
+; CHECK-DAG: stp     x5, x6, [sp, #72]
+; CHECK-DAG: str     x7, [sp, #88]
 ; CHECK-DAG: str     x8, [sp, #8]
 ; CHECK-DAG: bl      __local_stdio_printf_options
 ; CHECK-DAG: ldr     x8, [x0]
 ; CHECK-DAG: add     x5, sp, #56
 ; CHECK-DAG: mov     x1, x21
 ; CHECK-DAG: mov     x2, x20
 ; CHECK-DAG: orr     x0, x8, #0x2
 ; CHECK-DAG: mov     x3, x19

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

 }
 
 ; GCN-LABEL: {{^}}tail_call_stack_passed_arg_alignment_v32i32_f64:
 ; GCN: s_mov_b32 s5, s32
 ; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:16 ; 4-byte Folded Spill
 ; GCN: buffer_store_dword v33, off, s[0:3], s5 offset:12 ; 4-byte Folded Spill
 ; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:4
 ; GCN: buffer_load_dword v33, off, s[0:3], s5 offset:8
-; GCN: buffer_store_dword v33, off, s[0:3], s5 offset:8
 ; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:4
+; GCN: buffer_store_dword v33, off, s[0:3], s5 offset:8
 ; GCN: s_getpc_b64
 ; GCN: buffer_load_dword v33, off, s[0:3], s5 offset:12 ; 4-byte Folded Reload
 ; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:16 ; 4-byte Folded Reload
 ; GCN: s_setpc_b64
 define void @tail_call_stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
 entry:
   tail call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp)
   ret void
 }
 
 declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0
 declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }
 attributes #2 = { nounwind noinline }

llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll

entry:
   call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)
   ret i32 0
 }
 
 declare void @f(double);
 
 ; CHECK-LABEL:     test_byval_8_bytes_alignment_fixed_arg:
 ; CHECK-NOT:   str     r1
-; CHECK:       str     r3, [sp, #12]
-; CHECK:       str     r2, [sp, #8]
+; CHECK-DAG:   str     r3, [sp, #12]
+; CHECK-DAG:   str     r2, [sp, #8]
 ; CHECK-NOT:   str     r1
 define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %val) nounwind {
 entry:
   %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
   %0 = load double, double* %a
   call void (double) @f(double %0)
   ret void
 }

llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll

 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s
 
 @.str = private unnamed_addr constant [12 x i8] c"val.a = %f\0A\00"
 %struct_t = type { double, double, double }
 @static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }
 
 declare i32 @printf(i8*, ...)
 
 ; CHECK-LABEL:     test_byval_usage_scheduling:
-; CHECK:       str     r3, [sp, #12]
-; CHECK:       str     r2, [sp, #8]
+; CHECK-DAG:   str     r3, [sp, #12]
+; CHECK-DAG:   str     r2, [sp, #8]
 ; CHECK:       vldr    d16, [sp, #8]
 define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind {
 entry:
   %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0
   %0 = load double, double* %a
   %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %0)
   ret void
 }

llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll

 
 ; a -> r0
 ; b -> r2..r3
 define void @foo2(i32 %a, %struct8bytes8align* byval %b) {
 ; CHECK-LABEL: foo2
 ; CHECK: sub  sp, sp, #8
 ; CHECK: push  {r11, lr}
 ; CHECK: add  r0, sp, #8
-; CHECK: str  r3, [sp, #12]
-; CHECK: str  r2, [sp, #8]
+; CHECK-DAG: str  r3, [sp, #12]
+; CHECK-DAG: str  r2, [sp, #8]
 ; CHECK: bl   usePtr
 ; CHECK: pop  {r11, lr}
 ; CHECK: add  sp, sp, #8
 
   call void @usePtr(%struct8bytes8align* %b)
   ret void
 }
 

 ; a -> r0
 ; b -> r2..r3
 define void @foo4(%struct4bytes* byval %a, %struct8bytes8align* byval %b) {
 ; CHECK-LABEL: foo4
 ; CHECK: sub     sp, sp, #16
 ; CHECK: push    {r11, lr}
 ; CHECK: str     r0, [sp, #8]
 ; CHECK: add     r0, sp, #16
-; CHECK: str     r3, [sp, #20]
-; CHECK: str     r2, [sp, #16]
+; CHECK-DAG: str     r3, [sp, #20]
+; CHECK-DAG: str     r2, [sp, #16]
 ; CHECK: bl      usePtr
 ; CHECK: pop     {r11, lr}
 ; CHECK: add     sp, sp, #16
 ; CHECK: mov     pc, lr
 
   call void @usePtr(%struct8bytes8align* %b)
   ret void
 }

llvm/test/CodeGen/ARM/memset-inline.ll

 entry:
 ; CHECK-7A-LABEL: t2:
 ; CHECK-7A: vmov.i32 {{q[0-9]+}}, #0x0
 ; CHECK-7A: movs r1, #10
 ; CHECK-7A: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2], r1
 ; CHECK-7A: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2]
 ; CHECK-6M-LABEL: t2:
 ; CHECK-6M: movs [[REG:r[0-9]+]], #0
-; CHECK-6M: str  [[REG]], [sp, #20]
-; CHECK-6M: str  [[REG]], [sp, #16]
-; CHECK-6M: str  [[REG]], [sp, #12]
-; CHECK-6M: str  [[REG]], [sp, #8]
-; CHECK-6M: str  [[REG]], [sp, #4]
-; CHECK-6M: str  [[REG]], [sp]
+; CHECK-6M-DAG: str  [[REG]], [sp, #20]
+; CHECK-6M-DAG: str  [[REG]], [sp, #16]
+; CHECK-6M-DAG: str  [[REG]], [sp, #12]
+; CHECK-6M-DAG: str  [[REG]], [sp, #8]
+; CHECK-6M-DAG: str  [[REG]], [sp, #4]
+; CHECK-6M-DAG: str  [[REG]], [sp]
   %buf = alloca [26 x i8], align 1
   %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
   call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i1 false)
   call void @something(i8* %0) nounwind
   ret void
 }
 
 define void @t3(i8* %p) {

llvm/test/CodeGen/ARM/thumb1_return_sequence.ll

; CHECK-V5T:    push {[[SAVED:(r[4567](, )?)+]], lr}
   store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
   store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
   %0 = load <4 x i32>, <4 x i32>* %a, align 16
   call void @llvm.va_start(i8* null)
   ret <4 x i32> %0
 
 ; Epilogue
 ; --------
-; CHECK-V4T:         ldr [[POP:r[4567]]], [sp, #12]
+; CHECK-V4T:         ldr [[POP:r[4567]]], [sp, #16]
 ; CHECK-V4T-NEXT:    mov lr, [[POP]]
 ; CHECK-V4T-NEXT:    pop {[[SAVED]]}
 ; CHECK-V4T-NEXT:    add sp, #16
 ; CHECK-V4T-NEXT:    bx  lr
 ; CHECK-V5T:         lsls r4
 ; CHECK-V5T-NEXT:    mov sp, r4
-; CHECK-V5T:         ldr [[POP:r[4567]]], [sp, #12]
+; CHECK-V5T:         ldr [[POP:r[4567]]], [sp, #16]
 ; CHECK-V5T-NEXT:    mov lr, [[POP]]
 ; CHECK-V5T-NEXT:    pop {[[SAVED]]}
 ; CHECK-V5T-NEXT:    add sp, #16
 ; CHECK-V5T-NEXT:    bx  lr
 }
 
 ; CHECK-V4T-LABEL: simpleframe
 ; CHECK-V5T-LABEL: simpleframe

llvm/test/CodeGen/ARM/unaligned_load_store.ll

 ; RUN: llc -mtriple=arm-eabi -pre-RA-sched=source -mattr=+strict-align %s -o - \
 ; RUN:  | FileCheck %s -check-prefix=EXPANDED
 
 ; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 -mattr=-neon,+strict-align -pre-RA-sched=source %s -o - \
 ; RUN:  | FileCheck %s -check-prefix=EXPANDED
 
 ; RUN: llc -mtriple=armv6-apple-darwin -mcpu=cortex-a8 %s -o - \
 ; RUN:  | FileCheck %s -check-prefix=UNALIGNED
 
 ; rdar://7113725
 ; rdar://12091029
 
 define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
 entry:
 ; EXPANDED-LABEL: t:
-; EXPANDED: ldrb [[R2:r[0-9]+]]
-; EXPANDED: ldrb [[R3:r[0-9]+]]
-; EXPANDED: ldrb [[R12:r[0-9]+]]
-; EXPANDED: ldrb [[R1:r[0-9]+]]
-; EXPANDED: strb [[R1]]
-; EXPANDED: strb [[R12]]
-; EXPANDED: strb [[R3]]
-; EXPANDED: strb [[R2]]
+; EXPANDED-DAG: ldrb [[R2:r[0-9]+]]
+; EXPANDED-DAG: ldrb [[R3:r[0-9]+]]
+; EXPANDED-DAG: ldrb [[R12:r[0-9]+]]
+; EXPANDED-DAG: ldrb [[R1:r[0-9]+]]
+; EXPANDED-DAG: strb [[R1]]
+; EXPANDED-DAG: strb [[R12]]
+; EXPANDED-DAG: strb [[R3]]
+; EXPANDED-DAG: strb [[R2]]
 
 ; UNALIGNED-LABEL: t:
 ; UNALIGNED: ldr r1
 ; UNALIGNED: str r1
 
   %__src1.i = bitcast i8* %b to i32*              ; <i32*> [#uses=1]
   %__dest2.i = bitcast i8* %a to i32*             ; <i32*> [#uses=1]
   %tmp.i = load i32, i32* %__src1.i, align 1           ; <i32> [#uses=1]

llvm/test/CodeGen/AVR/calling-conv/c/basic.ll

define void @ret_void_args_i64(i64 %a) {
   ; CHECK-NEXT: sts     5, r19
   ; CHECK-NEXT: sts     4, r18
   store volatile i64 %a, i64* inttoptr (i64 4 to i64*)
   ret void
 }
 
 ; CHECK-LABEL: ret_void_args_i64_i64
 define void @ret_void_args_i64_i64(i64 %a, i64 %b) {
-  ; CHECK:      sts     11, r25
-  ; CHECK-NEXT: sts     10, r24
-  ; CHECK-NEXT: sts     9, r23
-  ; CHECK-NEXT: sts     8, r22
-  ; CHECK-NEXT: sts     7, r21
-  ; CHECK-NEXT: sts     6, r20
-  ; CHECK-NEXT: sts     5, r19
-  ; CHECK-NEXT: sts     4, r18
+  ; CHECK-DAG:  sts     11, r25
+  ; CHECK-DAG: sts     10, r24
+  ; CHECK-DAG: sts     9, r23
+  ; CHECK-DAG: sts     8, r22
+  ; CHECK-DAG: sts     7, r21
+  ; CHECK-DAG: sts     6, r20
+  ; CHECK-DAG: sts     5, r19
+  ; CHECK-DAG: sts     4, r18
   store volatile i64 %a, i64* inttoptr (i64 4 to i64*)
 
-  ; CHECK-NEXT: sts     11, r17
-  ; CHECK-NEXT: sts     10, r16
-  ; CHECK-NEXT: sts     9, r15
-  ; CHECK-NEXT: sts     8, r14
-  ; CHECK-NEXT: sts     7, r13
-  ; CHECK-NEXT: sts     6, r12
-  ; CHECK-NEXT: sts     5, r11
-  ; CHECK-NEXT: sts     4, r10
+  ; CHECK-DAG: sts     11, r17
+  ; CHECK-DAG: sts     10, r16
+  ; CHECK-DAG: sts     9, r15
+  ; CHECK-DAG: sts     8, r14
+  ; CHECK-DAG: sts     7, r13
+  ; CHECK-DAG: sts     6, r12
+  ; CHECK-DAG: sts     5, r11
+  ; CHECK-DAG: sts     4, r10
   store volatile i64 %b, i64* inttoptr (i64 4 to i64*)
   ret void
 }
 
 ; This is exactly enough to hit the limit of what can be passed
 ; completely in registers.
 ; CHECK-LABEL: ret_void_args_i64_i64_i16
 define void @ret_void_args_i64_i64_i16(i64 %a, i64 %b, i16 %c) {
   ; CHECK:      sts     5, r9
   ; CHECK-NEXT: sts     4, r8
   store volatile i16 %c, i16* inttoptr (i64 4 to i16*)
   ret void
 }

llvm/test/CodeGen/AVR/directmem.ll

 ; CHECK: lds r22, long.static
 ; CHECK: lds r23, long.static+1
 ; CHECK: lds r24, long.static+2
 ; CHECK: lds r25, long.static+3
 ; CHECK: subi r22, 255
 ; CHECK: sbci r23, 255
 ; CHECK: sbci r24, 255
 ; CHECK: sbci r25, 255
-; CHECK: sts long.static+3, r25
-; CHECK: sts long.static+2, r24
-; CHECK: sts long.static+1, r23
-; CHECK: sts long.static, r22
+; CHECK-DAG: sts long.static+3, r25
+; CHECK-DAG: sts long.static+2, r24
+; CHECK-DAG: sts long.static+1, r23
+; CHECK-DAG: sts long.static, r22
   %1 = load i32, i32* @long.static
   %inc = add nsw i32 %1, 1
   store i32 %inc, i32* @long.static
   ret i32 %inc
 }
 
 define void @global64_store() {
 ; CHECK-LABEL: global64_store:

 ; CHECK: subi r18, 255
 ; CHECK: sbci r19, 255
 ; CHECK: sbci r20, 255
 ; CHECK: sbci r21, 255
 ; CHECK: sbci r22, 255
 ; CHECK: sbci r23, 255
 ; CHECK: sbci r24, 255
 ; CHECK: sbci r25, 255
-; CHECK: sts longlong.static+7, r25
-; CHECK: sts longlong.static+6, r24
-; CHECK: sts longlong.static+5, r23
-; CHECK: sts longlong.static+4, r22
-; CHECK: sts longlong.static+3, r21
-; CHECK: sts longlong.static+2, r20
-; CHECK: sts longlong.static+1, r19
-; CHECK: sts longlong.static, r18
+; CHECK-DAG: sts longlong.static+7, r25
+; CHECK-DAG: sts longlong.static+6, r24
+; CHECK-DAG: sts longlong.static+5, r23
+; CHECK-DAG: sts longlong.static+4, r22
+; CHECK-DAG: sts longlong.static+3, r21
+; CHECK-DAG: sts longlong.static+2, r20
+; CHECK-DAG: sts longlong.static+1, r19
+; CHECK-DAG: sts longlong.static, r18
   %1 = load i64, i64* @longlong.static
   %inc = add nsw i64 %1, 1
   store i64 %inc, i64* @longlong.static
   ret i64 %inc
 }
 
 define i8 @constantaddr_read8() {
 ; CHECK-LABEL: constantaddr_read8:

llvm/test/CodeGen/BPF/undef.ll

 ; Function Attrs: nounwind uwtable
 define i32 @ebpf_filter(%struct.__sk_buff* nocapture readnone %ebpf_packet) #0 section "socket1" {
 
 ; EL: r1 = 11033905661445 ll
 ; EB: r1 = 361984551142686720 ll
 ; CHECK: *(u64 *)(r10 - 8) = r1
 
 ; CHECK: r1 = 0
-; CHECK: *(u16 *)(r10 + 24) = r1
-; CHECK: *(u16 *)(r10 + 22) = r1
-; CHECK: *(u16 *)(r10 + 20) = r1
-; CHECK: *(u16 *)(r10 + 18) = r1
-; CHECK: *(u16 *)(r10 + 16) = r1
-; CHECK: *(u16 *)(r10 + 14) = r1
-; CHECK: *(u16 *)(r10 + 12) = r1
-; CHECK: *(u16 *)(r10 + 10) = r1
-; CHECK: *(u16 *)(r10 + 8) = r1
-; CHECK: *(u16 *)(r10 + 6) = r1
-; CHECK: *(u16 *)(r10 + 4) = r1
-; CHECK: *(u16 *)(r10 + 2) = r1
-; CHECK: *(u16 *)(r10 + 0) = r1
-; CHECK: *(u16 *)(r10 + 26) = r1
+; CHECK-DAG: *(u16 *)(r10 + 24) = r1
+; CHECK-DAG: *(u16 *)(r10 + 22) = r1
+; CHECK-DAG: *(u16 *)(r10 + 20) = r1
+; CHECK-DAG: *(u16 *)(r10 + 18) = r1
+; CHECK-DAG: *(u16 *)(r10 + 16) = r1
+; CHECK-DAG: *(u16 *)(r10 + 14) = r1
+; CHECK-DAG: *(u16 *)(r10 + 12) = r1
+; CHECK-DAG: *(u16 *)(r10 + 10) = r1
+; CHECK-DAG: *(u16 *)(r10 + 8) = r1
+; CHECK-DAG: *(u16 *)(r10 + 6) = r1
+; CHECK-DAG: *(u16 *)(r10 + 4) = r1
+; CHECK-DAG: *(u16 *)(r10 + 2) = r1
+; CHECK-DAG: *(u16 *)(r10 + 0) = r1
+; CHECK-DAG: *(u16 *)(r10 + 26) = r1
 
 ; CHECK: r2 = r10
 ; CHECK: r2 += -8
 ; CHECK: r1 = routing
 ; CHECK: call bpf_map_lookup_elem
 ; CHECK: exit
   %key = alloca %struct.routing_key_2, align 1
   %1 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 0

llvm/test/CodeGen/MSP430/cc_args.ll

 
 define void @f_i64_i64(i64 %a, i64 %b) #0 {
 ; CHECK: f_i64_i64:
 ; CHECK: mov  r15, &g_i64+6
 ; CHECK: mov  r14, &g_i64+4
 ; CHECK: mov  r13, &g_i64+2
 ; CHECK: mov  r12, &g_i64
   store volatile i64 %a, i64* @g_i64, align 2
-; CHECK: mov  10(r4), &g_i64+6
-; CHECK: mov  8(r4), &g_i64+4
-; CHECK: mov  6(r4), &g_i64+2
-; CHECK: mov  4(r4), &g_i64
+; CHECK-DAG: mov  10(r4), &g_i64+6
+; CHECK-DAG: mov  8(r4), &g_i64+4
+; CHECK-DAG: mov  6(r4), &g_i64+2
+; CHECK-DAG: mov  4(r4), &g_i64
   store volatile i64 %b, i64* @g_i64, align 2
   ret void
 }
 
 define void @f_i16_i64_i32_i32(i16 %a, i64 %b, i32 %c, i32 %d) #0 {
 ; CHECK-LABEL: f_i16_i64_i32_i32:
 ; CHECK: mov  r12, &g_i16
   store volatile i16 %a, i16* @g_i16, align 2

llvm/test/CodeGen/Mips/v2i16tof32.ll

 ; CHECK-NEXT:    addiu $sp, $sp, -32
 ; CHECK-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-NEXT:    sw $fp, 28($sp) # 4-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset 30, -4
 ; CHECK-NEXT:    move $fp, $sp
 ; CHECK-NEXT:    .cfi_def_cfa_register 30
 ; CHECK-NEXT:    addiu $1, $zero, -16
 ; CHECK-NEXT:    and $sp, $sp, $1
-; CHECK-NEXT:    lw $1, 8($4)
-; CHECK-NEXT:    lw $2, 4($4)
-; CHECK-NEXT:    lw $3, 12($4)
-; CHECK-NEXT:    sw $3, 12($sp)
-; CHECK-NEXT:    sw $1, 8($sp)
-; CHECK-NEXT:    sw $2, 4($sp)
-; CHECK-NEXT:    lw $1, 0($4)
-; CHECK-NEXT:    sw $1, 0($sp)
-; CHECK-NEXT:    mtc1 $1, $f0
+; CHECK-NEXT:    lw $1, 12($4)
+; CHECK-NEXT:    lw $2, 0($4)
+; CHECK-NEXT:    lw $3, 8($4)
+; CHECK-NEXT:    sw $3, 8($sp)
+; CHECK-NEXT:    sw $1, 12($sp)
+; CHECK-NEXT:    sw $2, 0($sp)
+; CHECK-NEXT:    lw $1, 4($4)
+; CHECK-NEXT:    sw $1, 4($sp)
+; CHECK-NEXT:    mtc1 $2, $f0
 ; CHECK-NEXT:    move $sp, $fp
 ; CHECK-NEXT:    lw $fp, 28($sp) # 4-byte Folded Reload
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    addiu $sp, $sp, 32
-; CHECK-NEXT:    .set at
-; CHECK-NEXT:    .set macro
-; CHECK-NEXT:    .set reorder
-; CHECK-NEXT:    .end f
 entry:
   %m = alloca <8 x i16>
   %0 = load <8 x i16>, <8 x i16>* %a
   store <8 x i16> %0, <8 x i16>* %m
   %1 = bitcast <8 x i16> %0 to <4 x float>
   %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
   %3 = shufflevector <8 x float> zeroinitializer, <8 x float> %2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
   %4 = bitcast <8 x float> %3 to <8 x i32>
   %5 = extractelement <8 x i32> %4, i32 0
   %6 = bitcast i32 %5 to float
   ret float %6
 }
 

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

 
 ; Since we can only pass a max of 8 float128 value in VSX registers, ensure we
 ; store to stack if passing more.
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testStruct_03(%struct.With9fp128params* byval nocapture readonly
                             align 16 %a) {
 ; CHECK-LABEL: testStruct_03:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    std r10, 88(r1)
-; CHECK-NEXT:    std r9, 80(r1)
-; CHECK-NEXT:    std r8, 72(r1)
-; CHECK-NEXT:    std r7, 64(r1)
-; CHECK-NEXT:    std r6, 56(r1)
-; CHECK-NEXT:    std r5, 48(r1)
-; CHECK-NEXT:    std r4, 40(r1)
-; CHECK-NEXT:    std r3, 32(r1)
+; CHECK-DAG:    std r10, 88(r1)
+; CHECK-DAG:    std r9, 80(r1)
+; CHECK-DAG:    std r8, 72(r1)
+; CHECK-DAG:    std r7, 64(r1)
+; CHECK-DAG:    std r6, 56(r1)
+; CHECK-DAG:    std r5, 48(r1)
+; CHECK-DAG:    std r4, 40(r1)
+; CHECK-DAG:    std r3, 32(r1)
 ; CHECK-NEXT:    lxv v2, 128(r1)
 ; CHECK-NEXT:    blr
 
 ; CHECK-BE-LABEL: testStruct_03:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    std r10, 104(r1)
-; CHECK-BE-NEXT:    std r9, 96(r1)
-; CHECK-BE-NEXT:    std r8, 88(r1)
-; CHECK-BE-NEXT:    std r7, 80(r1)
-; CHECK-BE-NEXT:    std r6, 72(r1)
-; CHECK-BE-NEXT:    std r5, 64(r1)
-; CHECK-BE-NEXT:    std r4, 56(r1)
-; CHECK-BE-NEXT:    std r3, 48(r1)
+; CHECK-BE-DAG:    std r10, 104(r1)
+; CHECK-BE-DAG:    std r9, 96(r1)
+; CHECK-BE-DAG:    std r8, 88(r1)
+; CHECK-BE-DAG:    std r7, 80(r1)
+; CHECK-BE-DAG:    std r6, 72(r1)
+; CHECK-BE-DAG:    std r5, 64(r1)
+; CHECK-BE-DAG:    std r4, 56(r1)
+; CHECK-BE-DAG:    std r3, 48(r1)
 ; CHECK-BE-NEXT:    lxv v2, 144(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a7 = getelementptr inbounds %struct.With9fp128params,
                                %struct.With9fp128params* %a, i64 0, i32 6
   %0 = load fp128, fp128* %a7, align 16
   ret fp128 %0
 }
entry:
   ret fp128 %add3
 }
 
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @testNestedAggregate(%struct.MixedC* byval nocapture readonly align 16 %a) {
 ; CHECK-LABEL: testNestedAggregate:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    std r8, 72(r1)
-; CHECK-NEXT:    std r7, 64(r1)
-; CHECK-NEXT:    std r10, 88(r1)
-; CHECK-NEXT:    std r9, 80(r1)
-; CHECK-NEXT:    std r6, 56(r1)
-; CHECK-NEXT:    std r5, 48(r1)
-; CHECK-NEXT:    std r4, 40(r1)
-; CHECK-NEXT:    std r3, 32(r1)
+; CHECK-DAG:     std r10, 88(r1)
+; CHECK-DAG:     std r9, 80(r1)
+; CHECK-DAG:     std r8, 72(r1)
+; CHECK-DAG:     std r7, 64(r1)
+; CHECK-DAG:     std r6, 56(r1)
+; CHECK-DAG:     std r5, 48(r1)
+; CHECK-DAG:     std r4, 40(r1)
+; CHECK-DAG:     std r3, 32(r1)
 ; CHECK-NEXT:    lxv v2, 64(r1)
 ; CHECK-NEXT:    blr
 
 ; CHECK-BE-LABEL: testNestedAggregate:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    std r8, 88(r1)
-; CHECK-BE-NEXT:    std r7, 80(r1)
-; CHECK-BE-NEXT:    std r10, 104(r1)
-; CHECK-BE-NEXT:    std r9, 96(r1)
-; CHECK-BE-NEXT:    std r6, 72(r1)
-; CHECK-BE-NEXT:    std r5, 64(r1)
-; CHECK-BE-NEXT:    std r4, 56(r1)
-; CHECK-BE-NEXT:    std r3, 48(r1)
+; CHECK-BE-DAG:     std r8, 88(r1)
+; CHECK-BE-DAG:     std r7, 80(r1)
+; CHECK-BE-DAG:     std r10, 104(r1)
+; CHECK-BE-DAG:     std r9, 96(r1)
+; CHECK-BE-DAG:     std r6, 72(r1)
+; CHECK-BE-DAG:     std r5, 64(r1)
+; CHECK-BE-DAG:     std r4, 56(r1)
+; CHECK-BE-DAG:     std r3, 48(r1)
 ; CHECK-BE-NEXT:    lxv v2, 80(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %c = getelementptr inbounds %struct.MixedC, %struct.MixedC* %a, i64 0, i32 1, i32 1
   %0 = load fp128, fp128* %c, align 16
   ret fp128 %0
 }
 
entry:
   %0 = bitcast i128 %a.coerce.fca.2.extract to fp128
   ret fp128 %0
 }
 
 ; Function Attrs: nounwind
 define fp128 @sum_float128(i32 signext %count, ...) {
 ; CHECK-LABEL: sum_float128:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    std r10, 88(r1)
-; CHECK-NEXT:    std r9, 80(r1)
-; CHECK-NEXT:    std r8, 72(r1)
-; CHECK-NEXT:    std r7, 64(r1)
-; CHECK-NEXT:    std r6, 56(r1)
-; CHECK-NEXT:    cmpwi cr0, r3, 1
-; CHECK-NEXT:    std r4, 40(r1)
-; CHECK-NEXT:    addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
-; CHECK-NEXT:    addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
-; CHECK-NEXT:    lxvx v2, 0, [[REG1]]
-; CHECK-NEXT:    std r5, 48(r1)
+; CHECK-DAG:     std r10, 88(r1)
+; CHECK-DAG:     std r9, 80(r1)
+; CHECK-DAG:     std r8, 72(r1)
+; CHECK-DAG:     std r7, 64(r1)
+; CHECK-DAG:     std r6, 56(r1)
+; CHECK-DAG:     std r4, 40(r1)
+; CHECK-DAG:     cmpwi cr0, r3, 1
+; CHECK-DAG:     std r5, 48(r1)
+; CHECK-DAG:     addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
+; CHECK-DAG:     addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
+; CHECK-DAG:     lxvx v2, 0, [[REG1]]
 ; CHECK-NEXT:    bltlr cr0
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    addi r3, r1, 40
 ; CHECK-NEXT:    lxvx v3, 0, r3
 ; CHECK-NEXT:    xsaddqp v2, v3, v2
 ; CHECK-NEXT:    addi [[REG2:r[0-9]+]], r1, 72
 ; CHECK-NEXT:    std [[REG2]], -8(r1)
 ; CHECK-NEXT:    lxv v3, 16(r3)

llvm/test/CodeGen/PowerPC/ppc64-byval-align.ll

 
 define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) {
 entry:
   %x1 = getelementptr inbounds %struct.test, %struct.test* %z, i64 0, i32 0
   %0 = load i64, i64* %x1, align 16
   ret i64 %0
 }
 ; CHECK-LABEL: @callee2
-; CHECK: ld 3, 128(1)
+; CHECK: ld {{[0-9]+}}, 128(1)
 ; CHECK: blr
 
 declare i64 @test2(%struct.pad* byval, i32 signext, %struct.test* byval align 16)
 define void @caller2(i64 %z) {
 entry:
   %tmp = alloca %struct.test, align 16
   %.compoundliteral.sroa.0.0..sroa_idx = getelementptr inbounds %struct.test, %struct.test* %tmp, i64 0, i32 0
   store i64 %z, i64* %.compoundliteral.sroa.0.0..sroa_idx, align 16

llvm/test/CodeGen/Thumb/frame-access.ll

entry:
   ret i32 %call
 }
 ; CHECK-LABEL: test_varargs_vla
 ; Three incoming register varargs
 ; CHECK:       sub sp, #12
 ; Setup frame pointer
 ; CHECK:       add r7, sp, #8
 ; Register varargs stored via FP
-; CHECK:       str r3, [r7, #16]
-; CHECK-NEXT:  str r2, [r7, #12]
-; CHECK-NEXT:  str r1, [r7, #8]
+; CHECK-DAG:  str r3, [r7, #16]
+; CHECK-DAG:  str r2, [r7, #12]
+; CHECK-DAG:  str r1, [r7, #8]
 
 ; Moving SP, access via SP
 ; int test_args_moving_sp(int a, int b, int c, int d, int e) {
 ;   int v[4];
 ;   return f(v, a, b + c + d, e, s) + h(v, v+1, v+2);
 ; }
 define dso_local i32 @test_args_moving_sp(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) local_unnamed_addr  {
 entry:

llvm/test/CodeGen/Thumb/mvn.ll

 
 for.cond.cleanup:
   ret void
 }
 
 
 define void @test128(i128* %a) {
 ; CHECK-LABEL: test128:
-; CHECK:         ldr r1, [r0, #4]
+; CHECK:         ldr r1, [r0, #8]
 ; CHECK-NEXT:    ldr r2, .LCPI8_0
 ; CHECK-NEXT:    eors r2, r1
-; CHECK-NEXT:    str r2, [r0, #4]
+; CHECK-NEXT:    str r2, [r0, #8]
 ; CHECK-NEXT:    ldr r1, [r0]
 ; CHECK-NEXT:    ldr r2, .LCPI8_1
 ; CHECK-NEXT:    eors r2, r1
 ; CHECK-NEXT:    str r2, [r0]
-; CHECK-NEXT:    ldr r1, [r0, #8]
+; CHECK-NEXT:    ldr r1, [r0, #4]
 ; CHECK-NEXT:    ldr r2, .LCPI8_2
 ; CHECK-NEXT:    eors r2, r1
-; CHECK-NEXT:    str r2, [r0, #8]
+; CHECK-NEXT:    str r2, [r0, #4]
 ; CHECK-NEXT:    bx lr
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  .LCPI8_0:
-; CHECK-NEXT:    .long 4075008415
+; CHECK-NEXT:    .long 6692605
 ; CHECK-NEXT:  .LCPI8_1:
 ; CHECK-NEXT:    .long 2080661269
 ; CHECK-NEXT:  .LCPI8_2:
-; CHECK-NEXT:    .long 6692605
+; CHECK-NEXT:    .long 4075008415
   %x = load i128, i128* %a
   %xn = xor i128 %x, 123456789123456789123456789
   store i128 %xn, i128* %a
   ret void
 }
 

llvm/test/CodeGen/X86/aligned-variadic.ll

entry:
   %arraydecay1 = bitcast [1 x %struct.__va_list_tag]* %va to i8*
   call void @llvm.va_start(i8* %arraydecay1)
   %overflow_arg_area_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0, i32 2
   %overflow_arg_area = load i8*, i8** %overflow_arg_area_p, align 8
   %overflow_arg_area.next = getelementptr i8, i8* %overflow_arg_area, i64 24
   store i8* %overflow_arg_area.next, i8** %overflow_arg_area_p, align 8
 ; X32: leal    68(%esp), [[REG:%.*]]
 ; X32: movl    [[REG]], 16(%esp)
-; X64: leaq    232(%rsp), [[REG:%.*]]
+; X64: leaq    256(%rsp), [[REG:%.*]]
 ; X64: movq    [[REG]], 184(%rsp)
 ; X64: leaq    176(%rsp), %rdi
   call void @qux(%struct.__va_list_tag* %arraydecay)
   ret void
 }
 
 ; Function Attrs: nounwind
 declare void @llvm.va_start(i8*)
 
 declare void @qux(%struct.__va_list_tag*)

llvm/test/CodeGen/X86/atomic-idempotent.ll

 ; X32-NEXT:    pushl 12(%ebp)
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    calll __sync_fetch_and_or_16
 ; X32-NEXT:    addl $20, %esp
 ; X32-NEXT:    movl (%esp), %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %edi
-; X32-NEXT:    movl %edi, 12(%esi)
-; X32-NEXT:    movl %edx, 8(%esi)
-; X32-NEXT:    movl %ecx, 4(%esi)
+; X32-NEXT:    movl %edi, 8(%esi)
+; X32-NEXT:    movl %edx, 12(%esi)
 ; X32-NEXT:    movl %eax, (%esi)
+; X32-NEXT:    movl %ecx, 4(%esi)
 ; X32-NEXT:    movl %esi, %eax
 ; X32-NEXT:    leal -8(%ebp), %esp
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    popl %edi
 ; X32-NEXT:    popl %ebp
 ; X32-NEXT:    .cfi_def_cfa %esp, 4
 ; X32-NEXT:    retl $4
   %1 = atomicrmw or i128* %p, i128 0 monotonic

llvm/test/CodeGen/X86/avx-load-store.ll

cif_mixed_test_any_check:
   unreachable
 }
 
 define void @add8i32(<8 x i32>* %ret, <8 x i32>* %bp) nounwind {
 ; CHECK-LABEL: add8i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovups (%rsi), %xmm0
 ; CHECK-NEXT:    vmovups 16(%rsi), %xmm1
-; CHECK-NEXT:    vmovups %xmm0, (%rdi)
 ; CHECK-NEXT:    vmovups %xmm1, 16(%rdi)
+; CHECK-NEXT:    vmovups %xmm0, (%rdi)
 ; CHECK-NEXT:    retq
 ;
 ; CHECK_O0-LABEL: add8i32:
 ; CHECK_O0:       # %bb.0:
 ; CHECK_O0-NEXT:    vmovdqu (%rsi), %xmm0
 ; CHECK_O0-NEXT:    vmovdqu 16(%rsi), %xmm1
 ; CHECK_O0-NEXT:    # implicit-def: $ymm2
 ; CHECK_O0-NEXT:    vmovaps %xmm0, %xmm2
; CHECK_O0-NEXT:    retq
   ret void
 }
 
 define void @add4i64a16(<4 x i64>* %ret, <4 x i64>* %bp) nounwind {
 ; CHECK-LABEL: add4i64a16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovaps (%rsi), %xmm0
 ; CHECK-NEXT:    vmovaps 16(%rsi), %xmm1
-; CHECK-NEXT:    vmovaps %xmm0, (%rdi)
 ; CHECK-NEXT:    vmovaps %xmm1, 16(%rdi)
+; CHECK-NEXT:    vmovaps %xmm0, (%rdi)
 ; CHECK-NEXT:    retq
 ;
 ; CHECK_O0-LABEL: add4i64a16:
 ; CHECK_O0:       # %bb.0:
 ; CHECK_O0-NEXT:    vmovdqa (%rsi), %xmm0
 ; CHECK_O0-NEXT:    vmovdqa 16(%rsi), %xmm1
 ; CHECK_O0-NEXT:    # implicit-def: $ymm2
 ; CHECK_O0-NEXT:    vmovaps %xmm0, %xmm2

llvm/test/CodeGen/X86/btc_bts_btr.ll

 ; X86-NEXT:    testb $32, %cl
 ; X86-NEXT:    je .LBB33_2
 ; X86-NEXT:  # %bb.1:
 ; X86-NEXT:    movl %edx, %esi
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:  .LBB33_2:
 ; X86-NEXT:    notl %esi
 ; X86-NEXT:    notl %edx
-; X86-NEXT:    andl %esi, 4(%eax)
 ; X86-NEXT:    andl %edx, (%eax)
+; X86-NEXT:    andl %esi, 4(%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
   %1 = load i64, i64* %x
   %2 = shl i64 1, %n
   %3 = xor i64 %2, -1
   %4 = and i64 %1, %3
   store i64 %4, i64* %x

 ; X86-NEXT:    shldl %cl, %edx, %esi
 ; X86-NEXT:    shll %cl, %edx
 ; X86-NEXT:    testb $32, %cl
 ; X86-NEXT:    je .LBB34_2
 ; X86-NEXT:  # %bb.1:
 ; X86-NEXT:    movl %edx, %esi
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:  .LBB34_2:
-; X86-NEXT:    orl %esi, 4(%eax)
 ; X86-NEXT:    orl %edx, (%eax)
+; X86-NEXT:    orl %esi, 4(%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
   %1 = load i64, i64* %x
   %2 = shl i64 1, %n
   %3 = or i64 %1, %2
   store i64 %3, i64* %x
   ret void

 ; X86-NEXT:    shldl %cl, %edx, %esi
 ; X86-NEXT:    shll %cl, %edx
 ; X86-NEXT:    testb $32, %cl
 ; X86-NEXT:    je .LBB35_2
 ; X86-NEXT:  # %bb.1:
 ; X86-NEXT:    movl %edx, %esi
 ; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:  .LBB35_2:
-; X86-NEXT:    xorl %esi, 4(%eax)
 ; X86-NEXT:    xorl %edx, (%eax)
+; X86-NEXT:    xorl %esi, 4(%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
   %1 = load i64, i64* %x
   %2 = shl i64 1, %n
   %3 = xor i64 %1, %2
   store i64 %3, i64* %x
   ret void

llvm/test/CodeGen/X86/combine-sbb.ll

 ; X86-NEXT:    setb %bl
 ; X86-NEXT:    movl 12(%edx), %ebp
 ; X86-NEXT:    movl 8(%edx), %edx
 ; X86-NEXT:    subl 8(%ecx), %edx
 ; X86-NEXT:    sbbl 12(%ecx), %ebp
 ; X86-NEXT:    movzbl %bl, %ecx
 ; X86-NEXT:    subl %ecx, %edx
 ; X86-NEXT:    sbbl $0, %ebp
-; X86-NEXT:    movl %edi, 4(%eax)
 ; X86-NEXT:    movl %esi, (%eax)
+; X86-NEXT:    movl %edi, 4(%eax)
 ; X86-NEXT:    movl %edx, 8(%eax)
 ; X86-NEXT:    movl %ebp, 12(%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    popl %ebx
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    retl $4
 ;

llvm/test/CodeGen/X86/constant-combines.ll

 ; being useful.
 ;
 ; CHECK-LABEL: PR22524:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    movd %eax, %xmm0
 ; CHECK-NEXT:    xorps %xmm1, %xmm1
 ; CHECK-NEXT:    mulss %xmm0, %xmm1
-; CHECK-NEXT:    movq $0, (%rdi)
+; CHECK-NEXT:    movl $0, (%rdi)
 ; CHECK-NEXT:    movss %xmm1, 4(%rdi)
 ; CHECK-NEXT:    retq
 entry:
   %0 = getelementptr inbounds { float, float }, { float, float }* %arg,  i32 0, i32 1
   store float 0.000000e+00, float* %0, align 4
   %1 = getelementptr inbounds { float, float }, { float, float }* %arg, i64 0,  i32 0
   %2 = bitcast float* %1 to i64*
   %3 = load i64, i64* %2, align 8

llvm/test/CodeGen/X86/min-legal-vector-width.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl,avx512bw,avx512dq,prefer-256-bit | FileCheck %s
 
 ; This file primarily contains tests for specific places in X86ISelLowering.cpp that needed be made aware of the legalizer not allowing 512-bit vectors due to prefer-256-bit even though AVX512 is enabled.
 
 define void @add256(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="256" {
 ; CHECK-LABEL: add256:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovdqa (%rdi), %ymm0
 ; CHECK-NEXT:    vmovdqa 32(%rdi), %ymm1
-; CHECK-NEXT:    vpaddd (%rsi), %ymm0, %ymm0
 ; CHECK-NEXT:    vpaddd 32(%rsi), %ymm1, %ymm1
-; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
+; CHECK-NEXT:    vpaddd (%rsi), %ymm0, %ymm0
 ; CHECK-NEXT:    vmovdqa %ymm0, (%rdx)
+; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %d = load <16 x i32>, <16 x i32>* %a
   %e = load <16 x i32>, <16 x i32>* %b
   %f = add <16 x i32> %d, %e
   store <16 x i32> %f, <16 x i32>* %c
   ret void
 }
; CHECK-NEXT:    retq
   ret void
 }
 
 define void @pmaddwd_32_256(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="256" {
 ; CHECK-LABEL: pmaddwd_32_256:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovdqa (%rdi), %ymm0
 ; CHECK-NEXT:    vmovdqa 32(%rdi), %ymm1
-; CHECK-NEXT:    vpmaddwd (%rsi), %ymm0, %ymm0
 ; CHECK-NEXT:    vpmaddwd 32(%rsi), %ymm1, %ymm1
-; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
+; CHECK-NEXT:    vpmaddwd (%rsi), %ymm0, %ymm0
 ; CHECK-NEXT:    vmovdqa %ymm0, (%rdx)
+; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
    %A = load <32 x i16>, <32 x i16>* %APtr
    %B = load <32 x i16>, <32 x i16>* %BPtr
    %a = sext <32 x i16> %A to <32 x i32>
    %b = sext <32 x i16> %B to <32 x i32>
    %m = mul nsw <32 x i32> %a, %b
    %odd = shufflevector <32 x i32> %m, <32 x i32> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
; CHECK-NEXT:    retq
    ret void
 }
 
 define void @psubus_64i8_max_256(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="256" {
 ; CHECK-LABEL: psubus_64i8_max_256:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovdqa (%rdi), %ymm0
 ; CHECK-NEXT:    vmovdqa 32(%rdi), %ymm1
-; CHECK-NEXT:    vpsubusb (%rsi), %ymm0, %ymm0
 ; CHECK-NEXT:    vpsubusb 32(%rsi), %ymm1, %ymm1
-; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
+; CHECK-NEXT:    vpsubusb (%rsi), %ymm0, %ymm0
 ; CHECK-NEXT:    vmovdqa %ymm0, (%rdx)
+; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %x = load <64 x i8>, <64 x i8>* %xptr
   %y = load <64 x i8>, <64 x i8>* %yptr
   %cmp = icmp ult <64 x i8> %x, %y
   %max = select <64 x i1> %cmp, <64 x i8> %y, <64 x i8> %x
   %res = sub <64 x i8> %max, %y
   store <64 x i8> %res, <64 x i8>* %zptr

 
 define void @mul256(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="256" {
 ; CHECK-LABEL: mul256:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovdqa (%rdi), %ymm0
 ; CHECK-NEXT:    vmovdqa 32(%rdi), %ymm1
 ; CHECK-NEXT:    vmovdqa (%rsi), %ymm2
 ; CHECK-NEXT:    vmovdqa 32(%rsi), %ymm3
-; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm4 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
-; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm5 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
+; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm4 = ymm3[8],ymm0[8],ymm3[9],ymm0[9],ymm3[10],ymm0[10],ymm3[11],ymm0[11],ymm3[12],ymm0[12],ymm3[13],ymm0[13],ymm3[14],ymm0[14],ymm3[15],ymm0[15],ymm3[24],ymm0[24],ymm3[25],ymm0[25],ymm3[26],ymm0[26],ymm3[27],ymm0[27],ymm3[28],ymm0[28],ymm3[29],ymm0[29],ymm3[30],ymm0[30],ymm3[31],ymm0[31]
+; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm5 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
 ; CHECK-NEXT:    vpmullw %ymm4, %ymm5, %ymm4
 ; CHECK-NEXT:    vmovdqa {{.*#+}} ymm5 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
 ; CHECK-NEXT:    vpand %ymm5, %ymm4, %ymm4
-; CHECK-NEXT:    vpunpcklbw {{.*#+}} ymm2 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[16],ymm0[16],ymm2[17],ymm0[17],ymm2[18],ymm0[18],ymm2[19],ymm0[19],ymm2[20],ymm0[20],ymm2[21],ymm0[21],ymm2[22],ymm0[22],ymm2[23],ymm0[23]
-; CHECK-NEXT:    vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
-; CHECK-NEXT:    vpmullw %ymm2, %ymm0, %ymm0
-; CHECK-NEXT:    vpand %ymm5, %ymm0, %ymm0
-; CHECK-NEXT:    vpackuswb %ymm4, %ymm0, %ymm0
-; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm2 = ymm3[8],ymm0[8],ymm3[9],ymm0[9],ymm3[10],ymm0[10],ymm3[11],ymm0[11],ymm3[12],ymm0[12],ymm3[13],ymm0[13],ymm3[14],ymm0[14],ymm3[15],ymm0[15],ymm3[24],ymm0[24],ymm3[25],ymm0[25],ymm3[26],ymm0[26],ymm3[27],ymm0[27],ymm3[28],ymm0[28],ymm3[29],ymm0[29],ymm3[30],ymm0[30],ymm3[31],ymm0[31]
-; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm4 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31]
-; CHECK-NEXT:    vpmullw %ymm2, %ymm4, %ymm2
-; CHECK-NEXT:    vpand %ymm5, %ymm2, %ymm2
 ; CHECK-NEXT:    vpunpcklbw {{.*#+}} ymm3 = ymm3[0],ymm0[0],ymm3[1],ymm0[1],ymm3[2],ymm0[2],ymm3[3],ymm0[3],ymm3[4],ymm0[4],ymm3[5],ymm0[5],ymm3[6],ymm0[6],ymm3[7],ymm0[7],ymm3[16],ymm0[16],ymm3[17],ymm0[17],ymm3[18],ymm0[18],ymm3[19],ymm0[19],ymm3[20],ymm0[20],ymm3[21],ymm0[21],ymm3[22],ymm0[22],ymm3[23],ymm0[23]
 ; CHECK-NEXT:    vpunpcklbw {{.*#+}} ymm1 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23]
 ; CHECK-NEXT:    vpmullw %ymm3, %ymm1, %ymm1
 ; CHECK-NEXT:    vpand %ymm5, %ymm1, %ymm1
-; CHECK-NEXT:    vpackuswb %ymm2, %ymm1, %ymm1
-; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
+; CHECK-NEXT:    vpackuswb %ymm4, %ymm1, %ymm1
+; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm3 = ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15],ymm2[24],ymm0[24],ymm2[25],ymm0[25],ymm2[26],ymm0[26],ymm2[27],ymm0[27],ymm2[28],ymm0[28],ymm2[29],ymm0[29],ymm2[30],ymm0[30],ymm2[31],ymm0[31]
+; CHECK-NEXT:    vpunpckhbw {{.*#+}} ymm4 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
+; CHECK-NEXT:    vpmullw %ymm3, %ymm4, %ymm3
+; CHECK-NEXT:    vpand %ymm5, %ymm3, %ymm3
+; CHECK-NEXT:    vpunpcklbw {{.*#+}} ymm2 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[16],ymm0[16],ymm2[17],ymm0[17],ymm2[18],ymm0[18],ymm2[19],ymm0[19],ymm2[20],ymm0[20],ymm2[21],ymm0[21],ymm2[22],ymm0[22],ymm2[23],ymm0[23]
+; CHECK-NEXT:    vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
+; CHECK-NEXT:    vpmullw %ymm2, %ymm0, %ymm0
+; CHECK-NEXT:    vpand %ymm5, %ymm0, %ymm0
+; CHECK-NEXT:    vpackuswb %ymm3, %ymm0, %ymm0
 ; CHECK-NEXT:    vmovdqa %ymm0, (%rdx)
+; CHECK-NEXT:    vmovdqa %ymm1, 32(%rdx)
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
   %d = load <64 x i8>, <64 x i8>* %a
   %e = load <64 x i8>, <64 x i8>* %b
   %f = mul <64 x i8> %d, %e
   store <64 x i8> %f, <64 x i8>* %c
   ret void
 }

llvm/test/CodeGen/X86/musttail-varargs.ll

 ; LINUX-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movaps %xmm2, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movaps %xmm3, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movaps %xmm4, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movaps %xmm5, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movaps %xmm6, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movaps %xmm7, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:  .LBB0_2:
-; LINUX-NEXT:    movq %r15, {{[0-9]+}}(%rsp)
-; LINUX-NEXT:    movq %r12, {{[0-9]+}}(%rsp)
-; LINUX-NEXT:    movq %r13, {{[0-9]+}}(%rsp)
-; LINUX-NEXT:    movq %rbp, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movq %rbx, {{[0-9]+}}(%rsp)
+; LINUX-NEXT:    movq %rbp, {{[0-9]+}}(%rsp)
+; LINUX-NEXT:    movq %r13, {{[0-9]+}}(%rsp)
+; LINUX-NEXT:    movq %r12, {{[0-9]+}}(%rsp)
+; LINUX-NEXT:    movq %r15, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
 ; LINUX-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
 ; LINUX-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movabsq $206158430216, %rax # imm = 0x3000000008
 ; LINUX-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
 ; LINUX-NEXT:    movq %r14, %rdi
 ; LINUX-NEXT:    movaps %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill

 ; LINUX-X32-NEXT:    movaps %xmm1, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movaps %xmm2, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movaps %xmm3, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movaps %xmm4, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movaps %xmm5, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movaps %xmm6, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movaps %xmm7, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:  .LBB0_2:
-; LINUX-X32-NEXT:    movq %r15, {{[0-9]+}}(%esp)
-; LINUX-X32-NEXT:    movq %r12, {{[0-9]+}}(%esp)
-; LINUX-X32-NEXT:    movq %r13, {{[0-9]+}}(%esp)
-; LINUX-X32-NEXT:    movq %rbp, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movq %rbx, {{[0-9]+}}(%esp)
+; LINUX-X32-NEXT:    movq %rbp, {{[0-9]+}}(%esp)
+; LINUX-X32-NEXT:    movq %r13, {{[0-9]+}}(%esp)
+; LINUX-X32-NEXT:    movq %r12, {{[0-9]+}}(%esp)
+; LINUX-X32-NEXT:    movq %r15, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    leal {{[0-9]+}}(%rsp), %eax
 ; LINUX-X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    leal {{[0-9]+}}(%rsp), %eax
 ; LINUX-X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movabsq $206158430216, %rax # imm = 0x3000000008
 ; LINUX-X32-NEXT:    movq %rax, {{[0-9]+}}(%esp)
 ; LINUX-X32-NEXT:    movl %r14d, %edi
 ; LINUX-X32-NEXT:    movaps %xmm7, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill

 ; WINDOWS-NEXT:    subq $64, %rsp
 ; WINDOWS-NEXT:    .seh_stackalloc 64
 ; WINDOWS-NEXT:    .seh_endprologue
 ; WINDOWS-NEXT:    movl %eax, %r14d
 ; WINDOWS-NEXT:    movq %r9, %rsi
 ; WINDOWS-NEXT:    movq %r8, %rdi
 ; WINDOWS-NEXT:    movq %rdx, %rbx
 ; WINDOWS-NEXT:    movq %rcx, %rbp
-; WINDOWS-NEXT:    movq %r9, {{[0-9]+}}(%rsp)
-; WINDOWS-NEXT:    movq %r8, {{[0-9]+}}(%rsp)
 ; WINDOWS-NEXT:    movq %rdx, {{[0-9]+}}(%rsp)
+; WINDOWS-NEXT:    movq %r8, {{[0-9]+}}(%rsp)
+; WINDOWS-NEXT:    movq %r9, {{[0-9]+}}(%rsp)
 ; WINDOWS-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
 ; WINDOWS-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
 ; WINDOWS-NEXT:    callq get_f
 ; WINDOWS-NEXT:    movq %rax, %r10
 ; WINDOWS-NEXT:    movq %rbp, %rcx
 ; WINDOWS-NEXT:    movq %rbx, %rdx
 ; WINDOWS-NEXT:    movq %rdi, %r8
 ; WINDOWS-NEXT:    movq %rsi, %r9

llvm/test/CodeGen/X86/musttail.ll

 declare void @t3_callee(i32)
 
 ; Test that we actually copy in and out stack arguments that aren't forwarded
 ; without modification.
 define i32 @t4({}* %fn, i32 %n, i32 %r) {
 ; CHECK-LABEL: t4:
 ; CHECK: incl %[[r:.*]]
 ; CHECK: decl %[[n:.*]]
-; CHECK: movl %[[r]], {{[0-9]+}}(%esp)
-; CHECK: movl %[[n]], {{[0-9]+}}(%esp)
+; CHECK-DAG: movl %[[r]], {{[0-9]+}}(%esp)
+; CHECK-DAG: movl %[[n]], {{[0-9]+}}(%esp)
 ; CHECK: jmpl *%{{.*}}
 
 entry:
   %r1 = add i32 %r, 1
   %n1 = sub i32 %n, 1
   %fn_cast = bitcast {}* %fn to i32 ({}*, i32, i32)*
   %r2 = musttail call i32 %fn_cast({}* %fn, i32 %n1, i32 %r1)
   ret i32 %r2
 }
 
 ; Combine the complex stack frame with the parameter modification.
 define i32 @t5({}* %fn, i32 %n, i32 %r) alignstack(32) {
 ; CHECK-LABEL: t5:
 ; CHECK: pushl %ebp
 ; CHECK: movl %esp, %ebp
 ; CHECK: pushl %esi
 ;   Align the stack.
 ; CHECK: andl $-32, %esp
 ; CHECK: movl %esp, %esi
 ;   Modify the args.
 ; CHECK: incl %[[r:.*]]
 ; CHECK: decl %[[n:.*]]
 ;   Store them through ebp, since that's the only stable arg pointer.
-; CHECK: movl %[[r]], {{[0-9]+}}(%ebp)
-; CHECK: movl %[[n]], {{[0-9]+}}(%ebp)
+; CHECK-DAG: movl %[[r]], {{[0-9]+}}(%ebp)
+; CHECK-DAG: movl %[[n]], {{[0-9]+}}(%ebp)
 ;   Epilogue.
 ; CHECK: leal {{[-0-9]+}}(%ebp), %esp
 ; CHECK: popl %esi
 ; CHECK: popl %ebp
 ; CHECK: jmpl *%{{.*}}
 
 entry:
   %a = alloca i8, i32 %n
   call void @capture(i8* %a)
   %r1 = add i32 %r, 1
   %n1 = sub i32 %n, 1
   %fn_cast = bitcast {}* %fn to i32 ({}*, i32, i32)*
   %r2 = musttail call i32 %fn_cast({}* %fn, i32 %n1, i32 %r1)
   ret i32 %r2
 }

llvm/test/CodeGen/X86/nosse-vector.ll

 ; X32-NEXT:    movl %esp, %ebp
 ; X32-NEXT:    pushl %ebx
 ; X32-NEXT:    pushl %edi
 ; X32-NEXT:    pushl %esi
 ; X32-NEXT:    andl $-8, %esp
 ; X32-NEXT:    subl $48, %esp
 ; X32-NEXT:    movl 8(%ebp), %eax
 ; X32-NEXT:    movl 24(%eax), %ecx
-; X32-NEXT:    movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
+; X32-NEXT:    movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
 ; X32-NEXT:    movl 28(%eax), %ecx
 ; X32-NEXT:    movl %ecx, (%esp) # 4-byte Spill
 ; X32-NEXT:    movl 16(%eax), %esi
 ; X32-NEXT:    movl 20(%eax), %edi
 ; X32-NEXT:    movl 8(%eax), %ebx
 ; X32-NEXT:    movl 12(%eax), %edx
 ; X32-NEXT:    movl (%eax), %ecx
 ; X32-NEXT:    movl 4(%eax), %eax
 ; X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %ecx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %edx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %ebx, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %edi, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl %esi, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl (%esp), %eax # 4-byte Reload
 ; X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax # 4-byte Reload
+; X32-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
 ; X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl 12(%ebp), %eax
 ; X32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X32-NEXT:    fildll {{[0-9]+}}(%esp)
 ; X32-NEXT:    fstps 12(%eax)
 ; X32-NEXT:    fstps 8(%eax)

 ; X32-NEXT:    movl 12(%edx), %esi
 ; X32-NEXT:    movl 8(%edx), %edi
 ; X32-NEXT:    movl (%edx), %ebx
 ; X32-NEXT:    movl 4(%edx), %edx
 ; X32-NEXT:    addl (%ecx), %ebx
 ; X32-NEXT:    adcl 4(%ecx), %edx
 ; X32-NEXT:    addl 8(%ecx), %edi
 ; X32-NEXT:    adcl 12(%ecx), %esi
-; X32-NEXT:    movl %esi, 12(%eax)
 ; X32-NEXT:    movl %edi, 8(%eax)
-; X32-NEXT:    movl %edx, 4(%eax)
+; X32-NEXT:    movl %esi, 12(%eax)
 ; X32-NEXT:    movl %ebx, (%eax)
+; X32-NEXT:    movl %edx, 4(%eax)
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    popl %edi
 ; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: add_2i64_mem:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq (%rdi), %rax

llvm/test/CodeGen/X86/oddshuffles.ll

; XOP-NEXT:    retq
   store <8 x i32> %s2, <8 x i32>* %q2, align 4
   store <8 x i32> %s3, <8 x i32>* %q3, align 4
   ret void
 }
 
 define void @interleave_24i32_in(<24 x i32>* %p, <8 x i32>* %q1, <8 x i32>* %q2, <8 x i32>* %q3) nounwind {
 ; SSE2-LABEL: interleave_24i32_in:
 ; SSE2:       # %bb.0:
-; SSE2-NEXT:    movups (%rsi), %xmm5
-; SSE2-NEXT:    movups 16(%rsi), %xmm8
-; SSE2-NEXT:    movups (%rdx), %xmm6
-; SSE2-NEXT:    movups 16(%rdx), %xmm3
-; SSE2-NEXT:    movups (%rcx), %xmm0
-; SSE2-NEXT:    movups 16(%rcx), %xmm4
-; SSE2-NEXT:    movaps %xmm0, %xmm7
-; SSE2-NEXT:    shufps {{.*#+}} xmm7 = xmm7[0,0],xmm5[1,0]
-; SSE2-NEXT:    movaps %xmm5, %xmm1
-; SSE2-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1]
-; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm7[0,2]
+; SSE2-NEXT:    movups (%rsi), %xmm1
+; SSE2-NEXT:    movups 16(%rsi), %xmm0
+; SSE2-NEXT:    movups (%rdx), %xmm8
+; SSE2-NEXT:    movups 16(%rdx), %xmm5
+; SSE2-NEXT:    movups (%rcx), %xmm3
+; SSE2-NEXT:    movups 16(%rcx), %xmm6
+; SSE2-NEXT:    movaps %xmm3, %xmm7
+; SSE2-NEXT:    shufps {{.*#+}} xmm7 = xmm7[0,0],xmm1[1,0]
+; SSE2-NEXT:    movaps %xmm1, %xmm9
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm9 = xmm9[0],xmm8[0],xmm9[1],xmm8[1]
+; SSE2-NEXT:    shufps {{.*#+}} xmm9 = xmm9[0,1],xmm7[0,2]
 ; SSE2-NEXT:    movaps %xmm5, %xmm7
-; SSE2-NEXT:    shufps {{.*#+}} xmm7 = xmm7[2,0],xmm6[2,1]
-; SSE2-NEXT:    movaps %xmm0, %xmm2
-; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,0],xmm6[1,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm7 = xmm7[3,2],xmm6[3,2]
+; SSE2-NEXT:    movaps %xmm6, %xmm4
+; SSE2-NEXT:    unpckhps {{.*#+}} xmm4 = xmm4[2],xmm0[2],xmm4[3],xmm0[3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm4 = xmm4[0,3],xmm7[0,2]
+; SSE2-NEXT:    movaps %xmm0, %xmm7
+; SSE2-NEXT:    shufps {{.*#+}} xmm7 = xmm7[2,0],xmm5[2,1]
+; SSE2-NEXT:    movaps %xmm6, %xmm2
+; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[1,0],xmm5[1,0]
 ; SSE2-NEXT:    shufps {{.*#+}} xmm2 = xmm2[2,0],xmm7[0,2]
-; SSE2-NEXT:    shufps {{.*#+}} xmm6 = xmm6[3,2],xmm0[3,2]
-; SSE2-NEXT:    unpckhps {{.*#+}} xmm0 = xmm0[2],xmm5[2],xmm0[3],xmm5[3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,3],xmm6[0,2]
-; SSE2-NEXT:    movaps %xmm4, %xmm5
-; SSE2-NEXT:    shufps {{.*#+}} xmm5 = xmm5[0,0],xmm8[1,0]
-; SSE2-NEXT:    movaps %xmm8, %xmm6
-; SSE2-NEXT:    unpcklps {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[1]
-; SSE2-NEXT:    shufps {{.*#+}} xmm6 = xmm6[0,1],xmm5[0,2]
+; SSE2-NEXT:    shufps {{.*#+}} xmm6 = xmm6[0,0],xmm0[1,0]
+; SSE2-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1]
+; SSE2-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,1],xmm6[0,2]
 ; SSE2-NEXT:    movaps %xmm8, %xmm5
-; SSE2-NEXT:    shufps {{.*#+}} xmm5 = xmm5[2,0],xmm3[2,1]
-; SSE2-NEXT:    movaps %xmm4, %xmm7
-; SSE2-NEXT:    shufps {{.*#+}} xmm7 = xmm7[1,0],xmm3[1,0]
-; SSE2-NEXT:    shufps {{.*#+}} xmm7 = xmm7[2,0],xmm5[0,2]
-; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[3,2],xmm4[3,2]
-; SSE2-NEXT:    unpckhps {{.*#+}} xmm4 = xmm4[2],xmm8[2],xmm4[3],xmm8[3]
-; SSE2-NEXT:    shufps {{.*#+}} xmm4 = xmm4[0,3],xmm3[0,2]
+; SSE2-NEXT:    shufps {{.*#+}} xmm5 = xmm5[3,2],xmm3[3,2]
+; SSE2-NEXT:    movaps %xmm3, %xmm6
+; SSE2-NEXT:    unpckhps {{.*#+}} xmm6 = xmm6[2],xmm1[2],xmm6[3],xmm1[3]
+; SSE2-NEXT:    shufps {{.*#+}} xmm6 = xmm6[0,3],xmm5[0,2]
+; SSE2-NEXT:    shufps {{.*#+}} xmm1 = xmm1[2,0],xmm8[2,1]
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[1,0],xmm8[1,0]
+; SSE2-NEXT:    shufps {{.*#+}} xmm3 = xmm3[2,0],xmm1[0,2]
+; SSE2-NEXT:    movups %xmm3, 16(%rdi)
+; SSE2-NEXT:    movups %xmm6, 32(%rdi)
+; SSE2-NEXT:    movups %xmm0, 48(%rdi)
+; SSE2-NEXT:    movups %xmm2, 64(%rdi)
 ; SSE2-NEXT:    movups %xmm4, 80(%rdi)
-; SSE2-NEXT:    movups %xmm7, 64(%rdi)
-; SSE2-NEXT:    movups %xmm6, 48(%rdi)
-; SSE2-NEXT:    movups %xmm0, 32(%rdi)
-; SSE2-NEXT:    movups %xmm2, 16(%rdi)
-; SSE2-NEXT:    movups %xmm1, (%rdi)
+; SSE2-NEXT:    movups %xmm9, (%rdi)
 ; SSE2-NEXT:    retq
 ;
 ; SSE42-LABEL: interleave_24i32_in:
 ; SSE42:       # %bb.0:
-; SSE42-NEXT:    movdqu (%rsi), %xmm5
-; SSE42-NEXT:    movdqu 16(%rsi), %xmm2
-; SSE42-NEXT:    movdqu (%rdx), %xmm6
-; SSE42-NEXT:    movdqu 16(%rdx), %xmm1
-; SSE42-NEXT:    movdqu (%rcx), %xmm7
-; SSE42-NEXT:    movdqu 16(%rcx), %xmm4
-; SSE42-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[0,0,1,1]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm3 = xmm5[0,1,0,1]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm0[2,3],xmm3[4,5,6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm0 = xmm7[0,1,0,1]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5],xmm3[6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm3 = xmm6[1,1,2,2]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm7[2,3],xmm3[4,5,6,7]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm5[4,5],xmm3[6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[2,3,0,1]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm7 = xmm7[2,3,2,3]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm7 = xmm7[0,1],xmm5[2,3],xmm7[4,5,6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[2,2,3,3]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm5 = xmm7[0,1,2,3],xmm5[4,5],xmm7[6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm6 = xmm1[0,0,1,1]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm7 = xmm2[0,1,0,1]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm7 = xmm7[0,1],xmm6[2,3],xmm7[4,5,6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm6 = xmm4[0,1,0,1]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm6 = xmm7[0,1,2,3],xmm6[4,5],xmm7[6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm7 = xmm1[1,1,2,2]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm7 = xmm7[0,1],xmm4[2,3],xmm7[4,5,6,7]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm7 = xmm7[0,1,2,3],xmm2[4,5],xmm7[6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3],xmm4[4,5,6,7]
-; SSE42-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
-; SSE42-NEXT:    pblendw {{.*#+}} xmm1 = xmm4[0,1,2,3],xmm1[4,5],xmm4[6,7]
-; SSE42-NEXT:    movdqu %xmm1, 80(%rdi)
-; SSE42-NEXT:    movdqu %xmm7, 64(%rdi)
-; SSE42-NEXT:    movdqu %xmm6, 48(%rdi)
-; SSE42-NEXT:    movdqu %xmm5, 32(%rdi)
-; SSE42-NEXT:    movdqu %xmm3, 16(%rdi)
-; SSE42-NEXT:    movdqu %xmm0, (%rdi)
+; SSE42-NEXT:    movdqu (%rsi), %xmm8
+; SSE42-NEXT:    movdqu 16(%rsi), %xmm4
+; SSE42-NEXT:    movdqu (%rdx), %xmm2
+; SSE42-NEXT:    movdqu 16(%rdx), %xmm5
+; SSE42-NEXT:    movdqu (%rcx), %xmm3
+; SSE42-NEXT:    movdqu 16(%rcx), %xmm6
+; SSE42-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[0,0,1,1]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm7 = xmm8[0,1,0,1]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm7 = xmm7[0,1],xmm1[2,3],xmm7[4,5,6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm1 = xmm3[0,1,0,1]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm1 = xmm7[0,1,2,3],xmm1[4,5],xmm7[6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm7 = xmm4[2,3,0,1]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm0 = xmm6[2,3,2,3]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm7[2,3],xmm0[4,5,6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm7 = xmm5[2,2,3,3]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm7 = xmm0[0,1,2,3],xmm7[4,5],xmm0[6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm0 = xmm5[1,1,2,2]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm6[2,3],xmm0[4,5,6,7]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm4[4,5],xmm0[6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm5 = xmm5[0,0,1,1]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[0,1,0,1]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm4 = xmm4[0,1],xmm5[2,3],xmm4[4,5,6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm5 = xmm6[0,1,0,1]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm5 = xmm4[0,1,2,3],xmm5[4,5],xmm4[6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm4 = xmm8[2,3,0,1]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm6 = xmm3[2,3,2,3]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm6 = xmm6[0,1],xmm4[2,3],xmm6[4,5,6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[2,2,3,3]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm4 = xmm6[0,1,2,3],xmm4[4,5],xmm6[6,7]
+; SSE42-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[1,1,2,2]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm3[2,3],xmm2[4,5,6,7]
+; SSE42-NEXT:    pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm8[4,5],xmm2[6,7]
+; SSE42-NEXT:    movdqu %xmm2, 16(%rdi)
+; SSE42-NEXT:    movdqu %xmm4, 32(%rdi)
+; SSE42-NEXT:    movdqu %xmm5, 48(%rdi)
+; SSE42-NEXT:    movdqu %xmm0, 64(%rdi)
+; SSE42-NEXT:    movdqu %xmm7, 80(%rdi)
+; SSE42-NEXT:    movdqu %xmm1, (%rdi)
 ; SSE42-NEXT:    retq
 ;
 ; AVX1-LABEL: interleave_24i32_in:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovupd (%rsi), %ymm0
 ; AVX1-NEXT:    vmovupd (%rcx), %ymm1
-; AVX1-NEXT:    vmovups (%rdx), %xmm2
-; AVX1-NEXT:    vmovups 16(%rdx), %xmm3
-; AVX1-NEXT:    vmovups (%rsi), %xmm4
-; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[2,0],xmm2[2,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm2[1,1],xmm5[0,2]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[0,0],xmm4[0,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[2,0],xmm4[2,1]
+; AVX1-NEXT:    vmovups 16(%rcx), %xmm2
+; AVX1-NEXT:    vmovups (%rdx), %xmm3
+; AVX1-NEXT:    vmovups 16(%rdx), %xmm4
+; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[3,0],xmm2[3,0]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm2[2,1],xmm5[0,2]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[1,0],xmm4[1,0]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[2,0],xmm4[2,2]
 ; AVX1-NEXT:    vinsertf128 $1, %xmm5, %ymm2, %ymm2
-; AVX1-NEXT:    vmovddup {{.*#+}} xmm4 = xmm1[0,0]
-; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm4, %ymm4
-; AVX1-NEXT:    vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7]
-; AVX1-NEXT:    vmovups 16(%rcx), %xmm4
-; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm3[3,0],xmm4[3,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[2,1],xmm5[0,2]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm4 = xmm4[1,0],xmm3[1,0]
-; AVX1-NEXT:    vshufps {{.*#+}} xmm3 = xmm4[2,0],xmm3[2,2]
-; AVX1-NEXT:    vinsertf128 $1, %xmm5, %ymm3, %ymm3
 ; AVX1-NEXT:    vpermilpd {{.*#+}} ymm4 = ymm0[1,1,3,3]
 ; AVX1-NEXT:    vperm2f128 {{.*#+}} ymm4 = ymm4[2,3,2,3]
+; AVX1-NEXT:    vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7]
+; AVX1-NEXT:    vmovups (%rsi), %xmm4
+; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[2,0],xmm3[2,0]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm5 = xmm3[1,1],xmm5[0,2]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm3 = xmm3[0,0],xmm4[0,0]
+; AVX1-NEXT:    vshufps {{.*#+}} xmm3 = xmm3[2,0],xmm4[2,1]
+; AVX1-NEXT:    vinsertf128 $1, %xmm5, %ymm3, %ymm3
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm4 = xmm1[0,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm4, %ymm4
 ; AVX1-NEXT:    vblendps {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7]
 ; AVX1-NEXT:    vpermilpd {{.*#+}} ymm0 = ymm0[1,0,2,2]
 ; AVX1-NEXT:    vpermilpd {{.*#+}} ymm1 = ymm1[1,1,2,2]
 ; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2,3],ymm0[4],ymm1[5,6],ymm0[7]
 ; AVX1-NEXT:    vpermilps {{.*#+}} ymm1 = mem[0,0,3,3,4,4,7,7]
 ; AVX1-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7]
 ; AVX1-NEXT:    vmovups %ymm0, 32(%rdi)
-; AVX1-NEXT:    vmovups %ymm3, 64(%rdi)
-; AVX1-NEXT:    vmovups %ymm2, (%rdi)
+; AVX1-NEXT:    vmovups %ymm3, (%rdi)
+; AVX1-NEXT:    vmovups %ymm2, 64(%rdi)
 ; AVX1-NEXT:    vzeroupper
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-SLOW-LABEL: interleave_24i32_in:
 ; AVX2-SLOW:       # %bb.0:
 ; AVX2-SLOW-NEXT:    vmovups (%rsi), %ymm0
 ; AVX2-SLOW-NEXT:    vmovups (%rdx), %ymm1
 ; AVX2-SLOW-NEXT:    vmovups (%rcx), %ymm2

 ; AVX2-FAST-NEXT:    vmovups (%rdx), %ymm1
 ; AVX2-FAST-NEXT:    vmovups (%rcx), %ymm2
 ; AVX2-FAST-NEXT:    vmovaps {{.*#+}} ymm3 = [5,6,5,6,5,6,7,7]
 ; AVX2-FAST-NEXT:    vpermps %ymm1, %ymm3, %ymm3
 ; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm4 = ymm2[2,1,3,3]
 ; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm3 = ymm3[0],ymm4[1],ymm3[2,3],ymm4[4],ymm3[5,6],ymm4[7]
 ; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm4 = ymm0[0,3,3,3]
 ; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7]
-; AVX2-FAST-NEXT:    vmovaps {{.*#+}} ymm4 = [1,0,2,2,1,0,2,2]
-; AVX2-FAST-NEXT:    vpermps %ymm1, %ymm4, %ymm4
-; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm5 = ymm0[0,0,2,1]
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm4 = ymm5[0],ymm4[1],ymm5[2,3],ymm4[4],ymm5[5,6],ymm4[7]
-; AVX2-FAST-NEXT:    vbroadcastsd (%rcx), %ymm5
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm4 = ymm4[0,1],ymm5[2],ymm4[3,4],ymm5[5],ymm4[6,7]
-; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[1,1,2,2]
+; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm4 = ymm0[1,1,2,2]
 ; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm2 = ymm2[1,1,2,2]
-; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm0 = ymm2[0],ymm0[1],ymm2[2,3],ymm0[4],ymm2[5,6],ymm0[7]
-; AVX2-FAST-NEXT:    vpermilps {{.*#+}} ymm1 = ymm1[0,0,3,3,4,4,7,7]
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2,3],ymm4[4],ymm2[5,6],ymm4[7]
+; AVX2-FAST-NEXT:    vpermilps {{.*#+}} ymm4 = ymm1[0,0,3,3,4,4,7,7]
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7]
+; AVX2-FAST-NEXT:    vmovaps {{.*#+}} ymm4 = [1,0,2,2,1,0,2,2]
+; AVX2-FAST-NEXT:    vpermps %ymm1, %ymm4, %ymm1
+; AVX2-FAST-NEXT:    vpermpd {{.*#+}} ymm0 = ymm0[0,0,2,1]
+; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3],ymm1[4],ymm0[5,6],ymm1[7]
+; AVX2-FAST-NEXT:    vbroadcastsd (%rcx), %ymm1
 ; AVX2-FAST-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7]
-; AVX2-FAST-NEXT:    vmovups %ymm0, 32(%rdi)
-; AVX2-FAST-NEXT:    vmovups %ymm4, (%rdi)
+; AVX2-FAST-NEXT:    vmovups %ymm0, (%rdi)
+; AVX2-FAST-NEXT:    vmovups %ymm2, 32(%rdi)
 ; AVX2-FAST-NEXT:    vmovups %ymm3, 64(%rdi)
 ; AVX2-FAST-NEXT:    vzeroupper
 ; AVX2-FAST-NEXT:    retq
 ;
 ; XOP-LABEL: interleave_24i32_in:
 ; XOP:       # %bb.0:
 ; XOP-NEXT:    vmovupd (%rsi), %ymm0
 ; XOP-NEXT:    vmovups (%rcx), %ymm1
-; XOP-NEXT:    vmovups (%rdx), %xmm2
-; XOP-NEXT:    vmovups 16(%rdx), %xmm3
-; XOP-NEXT:    vmovups (%rsi), %xmm4
-; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[2,0],xmm2[2,0]
-; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm2[1,1],xmm5[0,2]
-; XOP-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[0,0],xmm4[0,0]
-; XOP-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[2,0],xmm4[2,1]
+; XOP-NEXT:    vmovups 16(%rcx), %xmm2
+; XOP-NEXT:    vmovups (%rdx), %xmm3
+; XOP-NEXT:    vmovups 16(%rdx), %xmm4
+; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[3,0],xmm2[3,0]
+; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm2[2,1],xmm5[0,2]
+; XOP-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[1,0],xmm4[1,0]
+; XOP-NEXT:    vshufps {{.*#+}} xmm2 = xmm2[2,0],xmm4[2,2]
 ; XOP-NEXT:    vinsertf128 $1, %xmm5, %ymm2, %ymm2
-; XOP-NEXT:    vmovddup {{.*#+}} xmm4 = xmm1[0,0]
-; XOP-NEXT:    vinsertf128 $1, %xmm4, %ymm4, %ymm4
-; XOP-NEXT:    vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7]
-; XOP-NEXT:    vmovups 16(%rcx), %xmm4
-; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm3[3,0],xmm4[3,0]
-; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[2,1],xmm5[0,2]
-; XOP-NEXT:    vshufps {{.*#+}} xmm4 = xmm4[1,0],xmm3[1,0]
-; XOP-NEXT:    vshufps {{.*#+}} xmm3 = xmm4[2,0],xmm3[2,2]
-; XOP-NEXT:    vinsertf128 $1, %xmm5, %ymm3, %ymm3
 ; XOP-NEXT:    vpermilpd {{.*#+}} ymm4 = ymm0[1,1,3,3]
 ; XOP-NEXT:    vperm2f128 {{.*#+}} ymm4 = ymm4[2,3,2,3]
+; XOP-NEXT:    vblendps {{.*#+}} ymm2 = ymm2[0,1],ymm4[2],ymm2[3,4],ymm4[5],ymm2[6,7]
+; XOP-NEXT:    vmovups (%rsi), %xmm4
+; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm4[2,0],xmm3[2,0]
+; XOP-NEXT:    vshufps {{.*#+}} xmm5 = xmm3[1,1],xmm5[0,2]
+; XOP-NEXT:    vshufps {{.*#+}} xmm3 = xmm3[0,0],xmm4[0,0]
+; XOP-NEXT:    vshufps {{.*#+}} xmm3 = xmm3[2,0],xmm4[2,1]
+; XOP-NEXT:    vinsertf128 $1, %xmm5, %ymm3, %ymm3
+; XOP-NEXT:    vmovddup {{.*#+}} xmm4 = xmm1[0,0]
+; XOP-NEXT:    vinsertf128 $1, %xmm4, %ymm4, %ymm4
 ; XOP-NEXT:    vblendps {{.*#+}} ymm3 = ymm3[0,1],ymm4[2],ymm3[3,4],ymm4[5],ymm3[6,7]
 ; XOP-NEXT:    vpermil2ps {{.*#+}} ymm0 = ymm1[2],ymm0[3],ymm1[2,3],ymm0[4],ymm1[5,4],ymm0[5]
 ; XOP-NEXT:    vpermilps {{.*#+}} ymm1 = mem[0,0,3,3,4,4,7,7]
 ; XOP-NEXT:    vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2],ymm0[3,4],ymm1[5],ymm0[6,7]
 ; XOP-NEXT:    vmovups %ymm0, 32(%rdi)
-; XOP-NEXT:    vmovups %ymm3, 64(%rdi)
-; XOP-NEXT:    vmovups %ymm2, (%rdi)
+; XOP-NEXT:    vmovups %ymm3, (%rdi)
+; XOP-NEXT:    vmovups %ymm2, 64(%rdi)
 ; XOP-NEXT:    vzeroupper
 ; XOP-NEXT:    retq
   %s1 = load <8 x i32>, <8 x i32>* %q1, align 4
   %s2 = load <8 x i32>, <8 x i32>* %q2, align 4
   %s3 = load <8 x i32>, <8 x i32>* %q3, align 4
   %t1 = shufflevector <8 x i32> %s1, <8 x i32> %s2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %t2 = shufflevector <8 x i32> %s3, <8 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %interleaved = shufflevector <16 x i32> %t1, <16 x i32> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>

llvm/test/CodeGen/X86/pr40631_deadstore_elision.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -o - %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
 %struct.sk_buff = type { i8* }
 %struct.xt_action_param = type { i8*, i8*, i8*, i32, i32, i8 }
 
 define i32 @ipt_do_table(%struct.sk_buff* noalias nocapture readonly) {
 ; CHECK-LABEL: ipt_do_table:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    subq $40, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    movq (%rdi), %rax
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movq $0, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq $170, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movaps {{.*#+}} xmm0 = [12297829382473034410,12297829382473034410]
 ; CHECK-NEXT:    movaps %xmm0, (%rsp)
 ; CHECK-NEXT:    movabsq $-6148914691236517206, %rcx # imm = 0xAAAAAAAAAAAAAAAA
 ; CHECK-NEXT:    movq %rcx, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rcx, {{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movb $-86, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movzwl 2(%rax), %ecx
 ; CHECK-NEXT:    andl $8191, %ecx # imm = 0x1FFF
 ; CHECK-NEXT:    movl %ecx, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movzbl (%rax), %eax
 ; CHECK-NEXT:    andl $15, %eax
 ; CHECK-NEXT:    movl %eax, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movb $0, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rsp, %rdi

llvm/test/CodeGen/X86/rotate.ll

 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl (%eax), %ecx
 ; X86-NEXT:    movl 4(%eax), %edx
 ; X86-NEXT:    movl %edx, %esi
 ; X86-NEXT:    shldl $31, %ecx, %esi
 ; X86-NEXT:    shldl $31, %edx, %ecx
-; X86-NEXT:    movl %ecx, 4(%eax)
 ; X86-NEXT:    movl %esi, (%eax)
+; X86-NEXT:    movl %ecx, 4(%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: rotr1_64_mem:
 ; X64:       # %bb.0:
 ; X64-NEXT:    rorq (%rdi)
 ; X64-NEXT:    retq
 

llvm/test/CodeGen/X86/rotate4.ll

 ; X86-NEXT:    pushl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 20
 ; X86-NEXT:    .cfi_offset %esi, -20
 ; X86-NEXT:    .cfi_offset %edi, -16
 ; X86-NEXT:    .cfi_offset %ebx, -12
 ; X86-NEXT:    .cfi_offset %ebp, -8
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl (%eax), %edx
+; X86-NEXT:    movl (%eax), %esi
 ; X86-NEXT:    movl 4(%eax), %ebx
-; X86-NEXT:    movl %edx, %esi
-; X86-NEXT:    shll %cl, %esi
+; X86-NEXT:    movl %esi, %edx
+; X86-NEXT:    shll %cl, %edx
 ; X86-NEXT:    movl %ebx, %edi
-; X86-NEXT:    shldl %cl, %edx, %edi
+; X86-NEXT:    shldl %cl, %esi, %edi
 ; X86-NEXT:    testb $32, %cl
 ; X86-NEXT:    je .LBB6_2
 ; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %esi, %edi
-; X86-NEXT:    xorl %esi, %esi
+; X86-NEXT:    movl %edx, %edi
+; X86-NEXT:    xorl %edx, %edx
 ; X86-NEXT:  .LBB6_2:
 ; X86-NEXT:    negb %cl
 ; X86-NEXT:    movl %ebx, %ebp
 ; X86-NEXT:    shrl %cl, %ebp
-; X86-NEXT:    shrdl %cl, %ebx, %edx
+; X86-NEXT:    shrdl %cl, %ebx, %esi
 ; X86-NEXT:    testb $32, %cl
 ; X86-NEXT:    je .LBB6_4
 ; X86-NEXT:  # %bb.3:
-; X86-NEXT:    movl %ebp, %edx
+; X86-NEXT:    movl %ebp, %esi
 ; X86-NEXT:    xorl %ebp, %ebp
 ; X86-NEXT:  .LBB6_4:
+; X86-NEXT:    orl %esi, %edx
 ; X86-NEXT:    orl %ebp, %edi
-; X86-NEXT:    orl %edx, %esi
+; X86-NEXT:    movl %edx, (%eax)
 ; X86-NEXT:    movl %edi, 4(%eax)
-; X86-NEXT:    movl %esi, (%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 16
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    popl %ebx
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa_offset 4

 ; X86-NEXT:    shll %cl, %ebp
 ; X86-NEXT:    shldl %cl, %ebx, %esi
 ; X86-NEXT:    testb $32, %cl
 ; X86-NEXT:    je .LBB7_4
 ; X86-NEXT:  # %bb.3:
 ; X86-NEXT:    movl %ebp, %esi
 ; X86-NEXT:    xorl %ebp, %ebp
 ; X86-NEXT:  .LBB7_4:
-; X86-NEXT:    orl %esi, %edx
 ; X86-NEXT:    orl %ebp, %edi
-; X86-NEXT:    movl %edx, 4(%eax)
+; X86-NEXT:    orl %esi, %edx
 ; X86-NEXT:    movl %edi, (%eax)
+; X86-NEXT:    movl %edx, 4(%eax)
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 16
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    popl %ebx
 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    .cfi_def_cfa_offset 4

llvm/test/CodeGen/X86/sadd_sat_vec.ll

 ; SSE-NEXT:    movq %xmm1, 16(%rdx)
 ; SSE-NEXT:    movdqa %xmm0, (%rdx)
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: v12i16:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovdqa (%rdi), %xmm0
 ; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT:    vpaddsw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vpaddsw 16(%rsi), %xmm1, %xmm1
-; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
+; AVX1-NEXT:    vpaddsw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vmovdqa %xmm0, (%rdx)
+; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: v12i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovdqa (%rdi), %ymm0
 ; AVX2-NEXT:    vpaddsw (%rsi), %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vmovq %xmm1, 16(%rdx)

llvm/test/CodeGen/X86/shift-and.ll

 ; X32-NEXT:    shrl %cl, %esi
 ; X32-NEXT:    shrdl %cl, %edi, %edx
 ; X32-NEXT:    testb $32, %cl
 ; X32-NEXT:    je .LBB5_2
 ; X32-NEXT:  # %bb.1:
 ; X32-NEXT:    movl %esi, %edx
 ; X32-NEXT:    xorl %esi, %esi
 ; X32-NEXT:  .LBB5_2:
-; X32-NEXT:    movl %esi, 4(%eax)
 ; X32-NEXT:    movl %edx, (%eax)
+; X32-NEXT:    movl %esi, 4(%eax)
 ; X32-NEXT:    popl %esi
 ; X32-NEXT:    popl %edi
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: t5ptr:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rcx
 ; X64-NEXT:    # kill: def $cl killed $cl killed $rcx

llvm/test/CodeGen/X86/shrink_vmul-widen.ll

 ; X86-SSE-NEXT:    movdqu (%edx,%ecx), %xmm0
 ; X86-SSE-NEXT:    movdqu 16(%edx,%ecx), %xmm1
 ; X86-SSE-NEXT:    movdqu (%eax,%ecx), %xmm2
 ; X86-SSE-NEXT:    movdqu 16(%eax,%ecx), %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X86-SSE-NEXT:    pmulhuw %xmm0, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X86-SSE-NEXT:    pmulhuw %xmm1, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X86-SSE-NEXT:    movdqu %xmm3, 48(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm1, 32(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm2, 16(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm0, (%esi,%ecx,4)
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X86-SSE-NEXT:    movdqu %xmm3, 32(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm1, 48(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm2, (%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm0, 16(%esi,%ecx,4)
 ; X86-SSE-NEXT:    popl %esi
 ; X86-SSE-NEXT:    retl
 ;
 ; X86-AVX1-LABEL: mul_16xi16:
 ; X86-AVX1:       # %bb.0: # %entry
 ; X86-AVX1-NEXT:    pushl %esi
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %ecx

 ; X64-SSE-NEXT:    movdqu (%rdi,%rdx), %xmm0
 ; X64-SSE-NEXT:    movdqu 16(%rdi,%rdx), %xmm1
 ; X64-SSE-NEXT:    movdqu (%rsi,%rdx), %xmm2
 ; X64-SSE-NEXT:    movdqu 16(%rsi,%rdx), %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X64-SSE-NEXT:    pmulhuw %xmm0, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X64-SSE-NEXT:    pmulhuw %xmm1, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X64-SSE-NEXT:    movdqu %xmm3, 48(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm1, 32(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm2, 16(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm0, (%rax,%rdx,4)
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X64-SSE-NEXT:    movdqu %xmm3, 32(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm1, 48(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm2, (%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm0, 16(%rax,%rdx,4)
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX1-LABEL: mul_16xi16:
 ; X64-AVX1:       # %bb.0: # %entry
 ; X64-AVX1-NEXT:    movq {{.*}}(%rip), %rax
 ; X64-AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
 ; X64-AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
 ; X64-AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero

 ; X86-SSE-NEXT:    movdqu (%edx,%ecx), %xmm0
 ; X86-SSE-NEXT:    movdqu 16(%edx,%ecx), %xmm1
 ; X86-SSE-NEXT:    movdqu (%eax,%ecx), %xmm2
 ; X86-SSE-NEXT:    movdqu 16(%eax,%ecx), %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X86-SSE-NEXT:    pmulhw %xmm0, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X86-SSE-NEXT:    pmulhw %xmm1, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X86-SSE-NEXT:    movdqu %xmm3, 48(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm1, 32(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm2, 16(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm0, (%esi,%ecx,4)
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X86-SSE-NEXT:    movdqu %xmm3, 32(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm1, 48(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm2, (%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm0, 16(%esi,%ecx,4)
 ; X86-SSE-NEXT:    popl %esi
 ; X86-SSE-NEXT:    retl
 ;
 ; X86-AVX1-LABEL: mul_16xi16_sext:
 ; X86-AVX1:       # %bb.0: # %entry
 ; X86-AVX1-NEXT:    pushl %esi
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %ecx

 ; X64-SSE-NEXT:    movdqu (%rdi,%rdx), %xmm0
 ; X64-SSE-NEXT:    movdqu 16(%rdi,%rdx), %xmm1
 ; X64-SSE-NEXT:    movdqu (%rsi,%rdx), %xmm2
 ; X64-SSE-NEXT:    movdqu 16(%rsi,%rdx), %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X64-SSE-NEXT:    pmulhw %xmm0, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X64-SSE-NEXT:    pmulhw %xmm1, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X64-SSE-NEXT:    movdqu %xmm3, 48(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm1, 32(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm2, 16(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm0, (%rax,%rdx,4)
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X64-SSE-NEXT:    movdqu %xmm3, 32(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm1, 48(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm2, (%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm0, 16(%rax,%rdx,4)
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX1-LABEL: mul_16xi16_sext:
 ; X64-AVX1:       # %bb.0: # %entry
 ; X64-AVX1-NEXT:    movq {{.*}}(%rip), %rax
 ; X64-AVX1-NEXT:    vpmovsxwd 16(%rdi,%rdx), %xmm0
 ; X64-AVX1-NEXT:    vpmovsxwd 24(%rdi,%rdx), %xmm1
 ; X64-AVX1-NEXT:    vpmovsxwd (%rdi,%rdx), %xmm2

llvm/test/CodeGen/X86/shrink_vmul.ll

 ; X86-SSE-NEXT:    movdqu (%edx,%ecx), %xmm0
 ; X86-SSE-NEXT:    movdqu 16(%edx,%ecx), %xmm1
 ; X86-SSE-NEXT:    movdqu (%eax,%ecx), %xmm2
 ; X86-SSE-NEXT:    movdqu 16(%eax,%ecx), %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X86-SSE-NEXT:    pmulhuw %xmm0, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X86-SSE-NEXT:    pmulhuw %xmm1, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X86-SSE-NEXT:    movdqu %xmm3, 48(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm1, 32(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm2, 16(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm0, (%esi,%ecx,4)
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X86-SSE-NEXT:    movdqu %xmm3, 32(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm1, 48(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm2, (%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm0, 16(%esi,%ecx,4)
 ; X86-SSE-NEXT:    popl %esi
 ; X86-SSE-NEXT:    retl
 ;
 ; X86-AVX1-LABEL: mul_16xi16:
 ; X86-AVX1:       # %bb.0: # %entry
 ; X86-AVX1-NEXT:    pushl %esi
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %ecx

 ; X64-SSE-NEXT:    movdqu (%rdi,%rdx), %xmm0
 ; X64-SSE-NEXT:    movdqu 16(%rdi,%rdx), %xmm1
 ; X64-SSE-NEXT:    movdqu (%rsi,%rdx), %xmm2
 ; X64-SSE-NEXT:    movdqu 16(%rsi,%rdx), %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X64-SSE-NEXT:    pmulhuw %xmm0, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X64-SSE-NEXT:    pmulhuw %xmm1, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X64-SSE-NEXT:    movdqu %xmm3, 48(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm1, 32(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm2, 16(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm0, (%rax,%rdx,4)
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X64-SSE-NEXT:    movdqu %xmm3, 32(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm1, 48(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm2, (%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm0, 16(%rax,%rdx,4)
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX1-LABEL: mul_16xi16:
 ; X64-AVX1:       # %bb.0: # %entry
 ; X64-AVX1-NEXT:    movq {{.*}}(%rip), %rax
 ; X64-AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
 ; X64-AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
 ; X64-AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero

 ; X86-SSE-NEXT:    movdqu (%edx,%ecx), %xmm0
 ; X86-SSE-NEXT:    movdqu 16(%edx,%ecx), %xmm1
 ; X86-SSE-NEXT:    movdqu (%eax,%ecx), %xmm2
 ; X86-SSE-NEXT:    movdqu 16(%eax,%ecx), %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X86-SSE-NEXT:    pmulhw %xmm0, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X86-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X86-SSE-NEXT:    pmulhw %xmm1, %xmm4
 ; X86-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X86-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X86-SSE-NEXT:    movdqu %xmm3, 48(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm1, 32(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm2, 16(%esi,%ecx,4)
-; X86-SSE-NEXT:    movdqu %xmm0, (%esi,%ecx,4)
+; X86-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X86-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X86-SSE-NEXT:    movdqu %xmm3, 32(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm1, 48(%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm2, (%esi,%ecx,4)
+; X86-SSE-NEXT:    movdqu %xmm0, 16(%esi,%ecx,4)
 ; X86-SSE-NEXT:    popl %esi
 ; X86-SSE-NEXT:    retl
 ;
 ; X86-AVX1-LABEL: mul_16xi16_sext:
 ; X86-AVX1:       # %bb.0: # %entry
 ; X86-AVX1-NEXT:    pushl %esi
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-AVX1-NEXT:    movl {{[0-9]+}}(%esp), %ecx

 ; X64-SSE-NEXT:    movdqu (%rdi,%rdx), %xmm0
 ; X64-SSE-NEXT:    movdqu 16(%rdi,%rdx), %xmm1
 ; X64-SSE-NEXT:    movdqu (%rsi,%rdx), %xmm2
 ; X64-SSE-NEXT:    movdqu 16(%rsi,%rdx), %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm4
 ; X64-SSE-NEXT:    pmulhw %xmm0, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm0, %xmm2
 ; X64-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3]
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm4
 ; X64-SSE-NEXT:    pmulhw %xmm1, %xmm4
 ; X64-SSE-NEXT:    pmullw %xmm1, %xmm3
 ; X64-SSE-NEXT:    movdqa %xmm3, %xmm1
-; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
-; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
-; X64-SSE-NEXT:    movdqu %xmm3, 48(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm1, 32(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm2, 16(%rax,%rdx,4)
-; X64-SSE-NEXT:    movdqu %xmm0, (%rax,%rdx,4)
+; X64-SSE-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
+; X64-SSE-NEXT:    punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
+; X64-SSE-NEXT:    movdqu %xmm3, 32(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm1, 48(%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm2, (%rax,%rdx,4)
+; X64-SSE-NEXT:    movdqu %xmm0, 16(%rax,%rdx,4)
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX1-LABEL: mul_16xi16_sext:
 ; X64-AVX1:       # %bb.0: # %entry
 ; X64-AVX1-NEXT:    movq {{.*}}(%rip), %rax
 ; X64-AVX1-NEXT:    vpmovsxwd 16(%rdi,%rdx), %xmm0
 ; X64-AVX1-NEXT:    vpmovsxwd 24(%rdi,%rdx), %xmm1
 ; X64-AVX1-NEXT:    vpmovsxwd (%rdi,%rdx), %xmm2

llvm/test/CodeGen/X86/ssub_sat_vec.ll

 ; SSE-NEXT:    movq %xmm1, 16(%rdx)
 ; SSE-NEXT:    movdqa %xmm0, (%rdx)
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: v12i16:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovdqa (%rdi), %xmm0
 ; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT:    vpsubsw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vpsubsw 16(%rsi), %xmm1, %xmm1
-; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
+; AVX1-NEXT:    vpsubsw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vmovdqa %xmm0, (%rdx)
+; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: v12i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovdqa (%rdi), %ymm0
 ; AVX2-NEXT:    vpsubsw (%rsi), %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vmovq %xmm1, 16(%rdx)

llvm/test/CodeGen/X86/uadd_sat_vec.ll

 ; SSE-NEXT:    movq %xmm1, 16(%rdx)
 ; SSE-NEXT:    movdqa %xmm0, (%rdx)
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: v12i16:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovdqa (%rdi), %xmm0
 ; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT:    vpaddusw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vpaddusw 16(%rsi), %xmm1, %xmm1
-; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
+; AVX1-NEXT:    vpaddusw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vmovdqa %xmm0, (%rdx)
+; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: v12i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovdqa (%rdi), %ymm0
 ; AVX2-NEXT:    vpaddusw (%rsi), %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vmovq %xmm1, 16(%rdx)

llvm/test/CodeGen/X86/usub_sat_vec.ll

 ; SSE-NEXT:    movq %xmm1, 16(%rdx)
 ; SSE-NEXT:    movdqa %xmm0, (%rdx)
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: v12i16:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmovdqa (%rdi), %xmm0
 ; AVX1-NEXT:    vmovdqa 16(%rdi), %xmm1
-; AVX1-NEXT:    vpsubusw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vpsubusw 16(%rsi), %xmm1, %xmm1
-; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
+; AVX1-NEXT:    vpsubusw (%rsi), %xmm0, %xmm0
 ; AVX1-NEXT:    vmovdqa %xmm0, (%rdx)
+; AVX1-NEXT:    vmovq %xmm1, 16(%rdx)
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: v12i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovdqa (%rdi), %ymm0
 ; AVX2-NEXT:    vpsubusw (%rsi), %ymm0, %ymm0
 ; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
 ; AVX2-NEXT:    vmovq %xmm1, 16(%rdx)

llvm/test/CodeGen/X86/vastart-defs-eflags.ll

 ; CHECK-NEXT:    movaps %xmm1, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movaps %xmm2, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movaps %xmm3, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movaps %xmm4, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movaps %xmm5, (%rsp)
 ; CHECK-NEXT:    movaps %xmm6, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movaps %xmm7, {{[0-9]+}}(%rsp)
 ; CHECK-NEXT:  LBB0_2: ## %entry
-; CHECK-NEXT:    movq %r9, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movq %r8, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movq %rcx, -{{[0-9]+}}(%rsp)
-; CHECK-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    movq %rsi, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq %rcx, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq %r8, -{{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq %r9, -{{[0-9]+}}(%rsp)
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testl $512, %edi ## imm = 0x200
 ; CHECK-NEXT:    je LBB0_4
 ; CHECK-NEXT:  ## %bb.3: ## %if.then
 ; CHECK-NEXT:    leaq -{{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    movq %rax, 16
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    movq %rax, 8

llvm/test/CodeGen/X86/vec_fpext.ll

entry:
   ret void
 }
 
 define void @fpext_frommem8(<8 x float>* %in, <8 x double>* %out) {
 ; X32-SSE-LABEL: fpext_frommem8:
 ; X32-SSE:       # %bb.0: # %entry
 ; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
 ; X32-SSE-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
-; X32-SSE-NEXT:    cvtps2pd (%ecx), %xmm0 # encoding: [0x0f,0x5a,0x01]
-; X32-SSE-NEXT:    cvtps2pd 8(%ecx), %xmm1 # encoding: [0x0f,0x5a,0x49,0x08]
-; X32-SSE-NEXT:    cvtps2pd 16(%ecx), %xmm2 # encoding: [0x0f,0x5a,0x51,0x10]
-; X32-SSE-NEXT:    cvtps2pd 24(%ecx), %xmm3 # encoding: [0x0f,0x5a,0x59,0x18]
-; X32-SSE-NEXT:    movups %xmm3, 48(%eax) # encoding: [0x0f,0x11,0x58,0x30]
-; X32-SSE-NEXT:    movups %xmm2, 32(%eax) # encoding: [0x0f,0x11,0x50,0x20]
-; X32-SSE-NEXT:    movups %xmm1, 16(%eax) # encoding: [0x0f,0x11,0x48,0x10]
-; X32-SSE-NEXT:    movups %xmm0, (%eax) # encoding: [0x0f,0x11,0x00]
+; X32-SSE-NEXT:    cvtps2pd 8(%ecx), %xmm0 # encoding: [0x0f,0x5a,0x41,0x08]
+; X32-SSE-NEXT:    cvtps2pd (%ecx), %xmm1 # encoding: [0x0f,0x5a,0x09]
+; X32-SSE-NEXT:    cvtps2pd 24(%ecx), %xmm2 # encoding: [0x0f,0x5a,0x51,0x18]
+; X32-SSE-NEXT:    cvtps2pd 16(%ecx), %xmm3 # encoding: [0x0f,0x5a,0x59,0x10]
+; X32-SSE-NEXT:    movups %xmm3, 32(%eax) # encoding: [0x0f,0x11,0x58,0x20]
+; X32-SSE-NEXT:    movups %xmm2, 48(%eax) # encoding: [0x0f,0x11,0x50,0x30]
+; X32-SSE-NEXT:    movups %xmm1, (%eax) # encoding: [0x0f,0x11,0x08]
+; X32-SSE-NEXT:    movups %xmm0, 16(%eax) # encoding: [0x0f,0x11,0x40,0x10]
 ; X32-SSE-NEXT:    retl # encoding: [0xc3]
 ;
 ; X32-AVX-LABEL: fpext_frommem8:
 ; X32-AVX:       # %bb.0: # %entry
 ; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
 ; X32-AVX-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
 ; X32-AVX-NEXT:    vcvtps2pd (%ecx), %ymm0 # encoding: [0xc5,0xfc,0x5a,0x01]
 ; X32-AVX-NEXT:    vcvtps2pd 16(%ecx), %ymm1 # encoding: [0xc5,0xfc,0x5a,0x49,0x10]
 ; X32-AVX-NEXT:    vmovups %ymm1, 32(%eax) # encoding: [0xc5,0xfc,0x11,0x48,0x20]
 ; X32-AVX-NEXT:    vmovups %ymm0, (%eax) # encoding: [0xc5,0xfc,0x11,0x00]
 ; X32-AVX-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
 ; X32-AVX-NEXT:    retl # encoding: [0xc3]
 ;
 ; X32-AVX512VL-LABEL: fpext_frommem8:
 ; X32-AVX512VL:       # %bb.0: # %entry
 ; X32-AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
 ; X32-AVX512VL-NEXT:    movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04]
 ; X32-AVX512VL-NEXT:    vcvtps2pd (%ecx), %zmm0 # encoding: [0x62,0xf1,0x7c,0x48,0x5a,0x01]
 ; X32-AVX512VL-NEXT:    vmovups %zmm0, (%eax) # encoding: [0x62,0xf1,0x7c,0x48,0x11,0x00]
 ; X32-AVX512VL-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
 ; X32-AVX512VL-NEXT:    retl # encoding: [0xc3]
 ;
 ; X64-SSE-LABEL: fpext_frommem8:
 ; X64-SSE:       # %bb.0: # %entry
-; X64-SSE-NEXT:    cvtps2pd (%rdi), %xmm0 # encoding: [0x0f,0x5a,0x07]
-; X64-SSE-NEXT:    cvtps2pd 8(%rdi), %xmm1 # encoding: [0x0f,0x5a,0x4f,0x08]
-; X64-SSE-NEXT:    cvtps2pd 16(%rdi), %xmm2 # encoding: [0x0f,0x5a,0x57,0x10]
-; X64-SSE-NEXT:    cvtps2pd 24(%rdi), %xmm3 # encoding: [0x0f,0x5a,0x5f,0x18]
-; X64-SSE-NEXT:    movups %xmm3, 48(%rsi) # encoding: [0x0f,0x11,0x5e,0x30]
-; X64-SSE-NEXT:    movups %xmm2, 32(%rsi) # encoding: [0x0f,0x11,0x56,0x20]
-; X64-SSE-NEXT:    movups %xmm1, 16(%rsi) # encoding: [0x0f,0x11,0x4e,0x10]
-; X64-SSE-NEXT:    movups %xmm0, (%rsi) # encoding: [0x0f,0x11,0x06]
+; X64-SSE-NEXT:    cvtps2pd 8(%rdi), %xmm0 # encoding: [0x0f,0x5a,0x47,0x08]
+; X64-SSE-NEXT:    cvtps2pd (%rdi), %xmm1 # encoding: [0x0f,0x5a,0x0f]
+; X64-SSE-NEXT:    cvtps2pd 24(%rdi), %xmm2 # encoding: [0x0f,0x5a,0x57,0x18]
+; X64-SSE-NEXT:    cvtps2pd 16(%rdi), %xmm3 # encoding: [0x0f,0x5a,0x5f,0x10]
+; X64-SSE-NEXT:    movups %xmm3, 32(%rsi) # encoding: [0x0f,0x11,0x5e,0x20]
+; X64-SSE-NEXT:    movups %xmm2, 48(%rsi) # encoding: [0x0f,0x11,0x56,0x30]
+; X64-SSE-NEXT:    movups %xmm1, (%rsi) # encoding: [0x0f,0x11,0x0e]
+; X64-SSE-NEXT:    movups %xmm0, 16(%rsi) # encoding: [0x0f,0x11,0x46,0x10]
 ; X64-SSE-NEXT:    retq # encoding: [0xc3]
 ;
 ; X64-AVX-LABEL: fpext_frommem8:
 ; X64-AVX:       # %bb.0: # %entry
 ; X64-AVX-NEXT:    vcvtps2pd (%rdi), %ymm0 # encoding: [0xc5,0xfc,0x5a,0x07]
 ; X64-AVX-NEXT:    vcvtps2pd 16(%rdi), %ymm1 # encoding: [0xc5,0xfc,0x5a,0x4f,0x10]
 ; X64-AVX-NEXT:    vmovups %ymm1, 32(%rsi) # encoding: [0xc5,0xfc,0x11,0x4e,0x20]
 ; X64-AVX-NEXT:    vmovups %ymm0, (%rsi) # encoding: [0xc5,0xfc,0x11,0x06]

llvm/test/CodeGen/X86/widen_cast-2.ll

 ; CHECK-NEXT:    movl (%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    shll $5, %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; CHECK-NEXT:    movdqa (%edx,%eax), %xmm1
 ; CHECK-NEXT:    movdqa 16(%edx,%eax), %xmm2
 ; CHECK-NEXT:    psubw %xmm0, %xmm1
 ; CHECK-NEXT:    psubw %xmm0, %xmm2
-; CHECK-NEXT:    pextrd $2, %xmm2, 24(%ecx,%eax)
-; CHECK-NEXT:    pextrd $1, %xmm2, 20(%ecx,%eax)
 ; CHECK-NEXT:    movd %xmm2, 16(%ecx,%eax)
+; CHECK-NEXT:    pextrd $1, %xmm2, 20(%ecx,%eax)
+; CHECK-NEXT:    pextrd $2, %xmm2, 24(%ecx,%eax)
 ; CHECK-NEXT:    movdqa %xmm1, (%ecx,%eax)
 ; CHECK-NEXT:    incl (%esp)
 ; CHECK-NEXT:    cmpl $3, (%esp)
 ; CHECK-NEXT:    jle .LBB0_2
 ; CHECK-NEXT:  .LBB0_3: # %afterfor
 ; CHECK-NEXT:    popl %eax
 ; CHECK-NEXT:    retl
 entry:

llvm/test/CodeGen/X86/widen_load-2.ll

 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; X86-NEXT:    pinsrd $1, 4(%edx), %xmm0
 ; X86-NEXT:    pinsrd $2, 8(%edx), %xmm0
 ; X86-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; X86-NEXT:    pinsrd $1, 4(%ecx), %xmm1
 ; X86-NEXT:    pinsrd $2, 8(%ecx), %xmm1
 ; X86-NEXT:    paddd %xmm0, %xmm1
-; X86-NEXT:    pextrd $2, %xmm1, 8(%eax)
 ; X86-NEXT:    pextrd $1, %xmm1, 4(%eax)
+; X86-NEXT:    pextrd $2, %xmm1, 8(%eax)
 ; X86-NEXT:    movd %xmm1, (%eax)
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: add3i32_2:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
 ; X64-NEXT:    pinsrd $2, 8(%rsi), %xmm0

 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movdqa (%edx), %xmm0
 ; X86-NEXT:    movdqa 16(%edx), %xmm1
 ; X86-NEXT:    paddd (%ecx), %xmm0
 ; X86-NEXT:    paddd 16(%ecx), %xmm1
-; X86-NEXT:    pextrd $2, %xmm1, 24(%eax)
-; X86-NEXT:    pextrd $1, %xmm1, 20(%eax)
 ; X86-NEXT:    movd %xmm1, 16(%eax)
+; X86-NEXT:    pextrd $1, %xmm1, 20(%eax)
+; X86-NEXT:    pextrd $2, %xmm1, 24(%eax)
 ; X86-NEXT:    movdqa %xmm0, (%eax)
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: add7i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movdqa (%rsi), %xmm0
 ; X64-NEXT:    movdqa 16(%rsi), %xmm1
 ; X64-NEXT:    paddd (%rdx), %xmm0
 ; X64-NEXT:    paddd 16(%rdx), %xmm1
-; X64-NEXT:    pextrd $2, %xmm1, 24(%rdi)
 ; X64-NEXT:    movq %xmm1, 16(%rdi)
+; X64-NEXT:    pextrd $2, %xmm1, 24(%rdi)
 ; X64-NEXT:    movdqa %xmm0, (%rdi)
 ; X64-NEXT:    retq
   %a = load %i32vec7, %i32vec7* %ap, align 16
   %b = load %i32vec7, %i32vec7* %bp, align 16
   %x = add %i32vec7 %a, %b
   store %i32vec7 %x, %i32vec7* %ret, align 16
   ret void
 }
 
 %i32vec12 = type <12 x i32>
 define void @add12i32(%i32vec12*  sret %ret, %i32vec12* %ap, %i32vec12* %bp)  {
 ; X86-LABEL: add12i32:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movdqa 32(%edx), %xmm0
 ; X86-NEXT:    movdqa (%edx), %xmm1
 ; X86-NEXT:    movdqa 16(%edx), %xmm2
 ; X86-NEXT:    paddd (%ecx), %xmm1
-; X86-NEXT:    paddd 16(%ecx), %xmm2
 ; X86-NEXT:    paddd 32(%ecx), %xmm0
-; X86-NEXT:    movdqa %xmm0, 32(%eax)
+; X86-NEXT:    paddd 16(%ecx), %xmm2
 ; X86-NEXT:    movdqa %xmm2, 16(%eax)
+; X86-NEXT:    movdqa %xmm0, 32(%eax)
 ; X86-NEXT:    movdqa %xmm1, (%eax)
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: add12i32:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movdqa (%rsi), %xmm0
 ; X64-NEXT:    movdqa 16(%rsi), %xmm1
 ; X64-NEXT:    movdqa 32(%rsi), %xmm2
 ; X64-NEXT:    paddd (%rdx), %xmm0
-; X64-NEXT:    paddd 16(%rdx), %xmm1
 ; X64-NEXT:    paddd 32(%rdx), %xmm2
-; X64-NEXT:    movdqa %xmm2, 32(%rdi)
+; X64-NEXT:    paddd 16(%rdx), %xmm1
 ; X64-NEXT:    movdqa %xmm1, 16(%rdi)
+; X64-NEXT:    movdqa %xmm2, 32(%rdi)
 ; X64-NEXT:    movdqa %xmm0, (%rdi)
 ; X64-NEXT:    retq
   %a = load %i32vec12, %i32vec12* %ap, align 16
   %b = load %i32vec12, %i32vec12* %bp, align 16
   %x = add %i32vec12 %a, %b
   store %i32vec12 %x, %i32vec12* %ret, align 16
   ret void
 }

 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movdqa (%edx), %xmm0
 ; X86-NEXT:    movdqa 16(%edx), %xmm1
 ; X86-NEXT:    paddw (%ecx), %xmm0
 ; X86-NEXT:    paddw 16(%ecx), %xmm1
-; X86-NEXT:    pextrd $1, %xmm1, 20(%eax)
 ; X86-NEXT:    movd %xmm1, 16(%eax)
+; X86-NEXT:    pextrd $1, %xmm1, 20(%eax)
 ; X86-NEXT:    movdqa %xmm0, (%eax)
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: add12i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movdqa (%rsi), %xmm0
 ; X64-NEXT:    movdqa 16(%rsi), %xmm1

 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movdqa 32(%edx), %xmm0
 ; X86-NEXT:    movdqa (%edx), %xmm1
 ; X86-NEXT:    movdqa 16(%edx), %xmm2
 ; X86-NEXT:    paddw (%ecx), %xmm1
-; X86-NEXT:    paddw 16(%ecx), %xmm2
 ; X86-NEXT:    paddw 32(%ecx), %xmm0
-; X86-NEXT:    movd %xmm0, 32(%eax)
+; X86-NEXT:    paddw 16(%ecx), %xmm2
 ; X86-NEXT:    movdqa %xmm2, 16(%eax)
+; X86-NEXT:    movd %xmm0, 32(%eax)
 ; X86-NEXT:    movdqa %xmm1, (%eax)
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: add18i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movdqa (%rsi), %xmm0
 ; X64-NEXT:    movdqa 16(%rsi), %xmm1
 ; X64-NEXT:    movdqa 32(%rsi), %xmm2
 ; X64-NEXT:    paddw (%rdx), %xmm0
-; X64-NEXT:    paddw 16(%rdx), %xmm1
 ; X64-NEXT:    paddw 32(%rdx), %xmm2
-; X64-NEXT:    movd %xmm2, 32(%rdi)
+; X64-NEXT:    paddw 16(%rdx), %xmm1
 ; X64-NEXT:    movdqa %xmm1, 16(%rdi)
+; X64-NEXT:    movd %xmm2, 32(%rdi)
 ; X64-NEXT:    movdqa %xmm0, (%rdi)
 ; X64-NEXT:    retq
   %a = load %i16vec18, %i16vec18* %ap, align 16
   %b = load %i16vec18, %i16vec18* %bp, align 16
   %x = add %i16vec18 %a, %b
   store %i16vec18 %x, %i16vec18* %ret, align 16
   ret void
 }

 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movdqa (%edx), %xmm0
 ; X86-NEXT:    movdqa 16(%edx), %xmm1
 ; X86-NEXT:    paddb (%ecx), %xmm0
 ; X86-NEXT:    paddb 16(%ecx), %xmm1
-; X86-NEXT:    pextrb $14, %xmm1, 30(%eax)
-; X86-NEXT:    pextrw $6, %xmm1, 28(%eax)
-; X86-NEXT:    pextrd $2, %xmm1, 24(%eax)
-; X86-NEXT:    pextrd $1, %xmm1, 20(%eax)
 ; X86-NEXT:    movd %xmm1, 16(%eax)
+; X86-NEXT:    pextrd $1, %xmm1, 20(%eax)
+; X86-NEXT:    pextrd $2, %xmm1, 24(%eax)
+; X86-NEXT:    pextrw $6, %xmm1, 28(%eax)
+; X86-NEXT:    pextrb $14, %xmm1, 30(%eax)
 ; X86-NEXT:    movdqa %xmm0, (%eax)
 ; X86-NEXT:    retl $4
 ;
 ; X64-LABEL: add31i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
 ; X64-NEXT:    movdqa (%rsi), %xmm0
 ; X64-NEXT:    movdqa 16(%rsi), %xmm1
 ; X64-NEXT:    paddb (%rdx), %xmm0
 ; X64-NEXT:    paddb 16(%rdx), %xmm1
-; X64-NEXT:    pextrb $14, %xmm1, 30(%rdi)
-; X64-NEXT:    pextrw $6, %xmm1, 28(%rdi)
-; X64-NEXT:    pextrd $2, %xmm1, 24(%rdi)
 ; X64-NEXT:    movq %xmm1, 16(%rdi)
+; X64-NEXT:    pextrd $2, %xmm1, 24(%rdi)
+; X64-NEXT:    pextrw $6, %xmm1, 28(%rdi)
+; X64-NEXT:    pextrb $14, %xmm1, 30(%rdi)
 ; X64-NEXT:    movdqa %xmm0, (%rdi)
 ; X64-NEXT:    retq
   %a = load %i8vec31, %i8vec31* %ap, align 16
   %b = load %i8vec31, %i8vec31* %bp, align 16
   %x = add %i8vec31 %a, %b
   store %i8vec31 %x, %i8vec31* %ret, align 16
   ret void
 }

llvm/test/CodeGen/X86/win64_frame.ll

 ; ALL:       # %bb.0:
 ; ALL-NEXT:    pushq %rbp
 ; ALL-NEXT:    .seh_pushreg 5
 ; ALL-NEXT:    pushq %rax
 ; ALL-NEXT:    .seh_stackalloc 8
 ; ALL-NEXT:    movq %rsp, %rbp
 ; ALL-NEXT:    .seh_setframe 5, 0
 ; ALL-NEXT:    .seh_endprologue
-; ALL-NEXT:    movq %r9, 48(%rbp)
-; ALL-NEXT:    movq %r8, 40(%rbp)
 ; ALL-NEXT:    movq %rdx, 32(%rbp)
+; ALL-NEXT:    movq %r8, 40(%rbp)
+; ALL-NEXT:    movq %r9, 48(%rbp)
 ; ALL-NEXT:    leaq 32(%rbp), %rax
 ; ALL-NEXT:    movq %rax, (%rbp)
 ; ALL-NEXT:    addq $8, %rsp
 ; ALL-NEXT:    popq %rbp
 ; ALL-NEXT:    retq
 ; ALL-NEXT:    .seh_handlerdata
 ; ALL-NEXT:    .text
 ; ALL-NEXT:    .seh_endproc

llvm/test/CodeGen/X86/win64_vararg.ll

 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-win32 | FileCheck %s
 
 ; Verify that the var arg parameters which are passed in registers are stored
 ; in home stack slots allocated by the caller and that AP is correctly
 ; calculated.
 define void @average_va(i32 %count, ...) nounwind {
 entry:
 ; CHECK: pushq
-; CHECK: movq   %r9, 40(%rsp)
-; CHECK: movq   %r8, 32(%rsp)
-; CHECK: movq   %rdx, 24(%rsp)
+; CHECK-DAG: movq   %r9, 40(%rsp)
+; CHECK-DAG: movq   %r8, 32(%rsp)
+; CHECK-DAG: movq   %rdx, 24(%rsp)
 ; CHECK: leaq   24(%rsp), %rax
 
   %ap = alloca i8*, align 8                       ; <i8**> [#uses=1]
   %ap1 = bitcast i8** %ap to i8*                  ; <i8*> [#uses=1]
   call void @llvm.va_start(i8* %ap1)
   ret void
 }
 

llvm/test/CodeGen/X86/x86-64-ms_abi-vararg.ll

 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-linux-gnu | FileCheck %s
 
 ; Verify that the var arg parameters which are passed in registers are stored
 ; in home stack slots allocated by the caller and that AP is correctly
 ; calculated.
 define win64cc void @average_va(i32 %count, ...) nounwind {
 entry:
 ; CHECK: pushq
-; CHECK: movq   %r9, 40(%rsp)
-; CHECK: movq   %r8, 32(%rsp)
-; CHECK: movq   %rdx, 24(%rsp)
+; CHECK-DAG: movq   %r9, 40(%rsp)
+; CHECK-DAG: movq   %r8, 32(%rsp)
+; CHECK-DAG: movq   %rdx, 24(%rsp)
 ; CHECK: leaq   24(%rsp), %rax
 
   %ap = alloca i8*, align 8                       ; <i8**> [#uses=1]
   %ap.0 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap.0)
   ret void
 }
 
entry:
   ret i8** %ap
 }
 
 ; WinX86_64 uses char* for va_list. Verify that the correct amount of bytes
 ; are copied using va_copy.
 
 ; CHECK-LABEL: copy1:
 ; CHECK: leaq 32(%rsp), [[REG_copy1:%[a-z]+]]
-; CHECK: movq [[REG_copy1]], 8(%rsp)
-; CHECK: movq [[REG_copy1]], (%rsp)
+; CHECK-DAG: movq [[REG_copy1]], 8(%rsp)
+; CHECK-DAG: movq [[REG_copy1]], (%rsp)
 ; CHECK: ret
 define win64cc void @copy1(i64 %a0, ...) nounwind {
 entry:
   %ap = alloca i8*, align 8
   %cp = alloca i8*, align 8
   %ap.0 = bitcast i8** %ap to i8*
   %cp.0 = bitcast i8** %cp to i8*
   call void @llvm.va_start(i8* %ap.0)

llvm/test/CodeGen/XCore/byVal.ll

entry:
   call void @f1(%struct.st1* %s1) nounwind
   ret i32 %i
 }
 
 ; CHECK-LABEL: f2Test
 ; CHECK: extsp 4
 ; CHECK: stw lr, sp[1]
 ; CHECK: mov r11, r1
-; CHECK: stw r2, sp[3]
-; CHECK: stw r3, sp[4]
+; CHECK-DAG: stw r2, sp[3]
+; CHECK-DAG: stw r3, sp[4]
 ; CHECK: ldw r0, r0[0]
 ; CHECK: stw r0, sp[2]
 ; CHECK: ldaw r1, sp[2]
 ; CHECK: mov r0, r11
 ; CHECK: bl f2
 ; CHECK: ldw lr, sp[1]
 ; CHECK: ldaw sp, sp[4]
 ; CHECK: retsp 0