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[AMDGPU] Use three- and five-dword result type in image ops
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Authored by tpr on Mar 4 2019, 7:17 AM.

Details

Summary

Some image ops return three or five dwords. Previously, we modeled that
with a 4 or 8 dword register class. The register allocator could
cleverly spot that some subregs were dead and allocate something else
there, but that caused the de-optimization that waitcnt insertion would
think that the result was used immediately.

This commit allows such an image op to have a result with a three or
five dword result, avoiding the above de-optimization.

Change-Id: I3651211bbd7ed22721ee7b9fefd7bcc60a809d8b

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Repository
rL LLVM

Event Timeline

tpr created this revision.Mar 4 2019, 7:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 4 2019, 7:17 AM
arsenm accepted this revision.Mar 11 2019, 9:14 AM

LGTM

This revision is now accepted and ready to land.Mar 11 2019, 9:14 AM
This revision was automatically updated to reflect the committed changes.