AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This

commit does not add them, but makes preparatory changes:

- Exclude non-legal non-power-of-2 vector types from ComputeRegisterProp mechanism in TargetLoweringBase::getTypeConversion.

- Cope with SETCC and VSELECT for odd-width i1 vector when the other vectors are legal type.

- Fixed an assumption of power-of-2 vector type in ARM.

- Fixed assumptions of power-of-2 vector type in AMDGPU kernel arg handling.

- Fixed AMDGPU cost analysis to behave the same.

Some of this patch is from Matt Arsenault, also of AMD.

Change-Id: Ib5f23377dbef511be3a936211a0b9f94e46331f8