[AMDGPU] Prepare for introduction of v3 and v5 MVTs

[tpr]

Summary

AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, but makes preparatory changes:

• Fixed assumptions of power-of-2 vector type in kernel arg handling, and added v5 kernel arg tests.

• Added v5 tests for cost analysis.

Some of this patch is from Matt Arsenault, also of AMD.

Change-Id: I7279d6b4841464d2080eb255ef3c589e268eabcd

[rampitec]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

1036 ↗

(On Diff #189215)

It will be an empty block in release and compiler will complain.

[tpr]

V2: Addressed Stas's review comment about empty block.

[arsenm]

Could also use the vector tests for the shader arguments

test/CodeGen/AMDGPU/kernel-args.ll

443 ↗

(On Diff #189292)

i64/f64

[tpr]

In D58928#1418559, @arsenm wrote:

Could also use the vector tests for the shader arguments

Could you explain what you're suggesting I do please?

[tpr]

V3: Fixed new cost tests so they work with and without legal v3/v5
types. Added v5i64/v5f64 kernarg test cases as suggested by Matt.

[arsenm]

In D58928#1424393, @tpr wrote:

In D58928#1418559, @arsenm wrote:

Could also use the vector tests for the shader arguments

Could you explain what you're suggesting I do please?

You added tests for kernel arguments, but the calling convention lowering path is quite different for regular functions as well as shaders. The tests for the othercalling convention argument types should also be tested. V3 may already be tested, but v5 probably is not

[tpr]

V4: Added vec3/vec5 shader arg test cases.

[arsenm]

Missed call-argument-types.ll/call-return-types.ll. These have tests for <3 x i32>/<3 x float>, but missing the 5xs. Those could also use some byval/sret, and stack passed cases since I suspect they are going to break since we have to maintain a list of specific MVTs for those

[tpr]

V5: Added vec3/vec5 non-shader arg and ret type test cases, including passing by stack.

[arsenm]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

for (unsigned Value = 0, NumValues = ValueVTs.size();
           llvm_unreachable("cannot deduce memory type.");
         }
       }
 
       // Convert one element vectors to scalar.
       if (MemVT.isVector() && MemVT.getVectorNumElements() == 1)
         MemVT = MemVT.getScalarType();
 
-      if (MemVT.isExtended()) {
-        // This should really only happen if we have vec3 arguments
-        assert(MemVT.isVector() && MemVT.getVectorNumElements() == 3);
+      // Round up vec3/vec5 argument.
+      if (MemVT.isVector() && !MemVT.isPow2VectorType()) {
+        assert(MemVT.getVectorNumElements() == 3 ||
+               MemVT.getVectorNumElements() == 5);
         MemVT = MemVT.getPow2VectorType(State.getContext());
       }
 
       unsigned PartOffset = 0;
       for (unsigned i = 0; i != NumRegs; ++i) {
         State.addLoc(CCValAssign::getCustomMem(InIndex++, RegisterVT,
                                                BasePartOffset + PartOffset,
                                                MemVT.getSimpleVT(),

llvm/trunk/test/Analysis/CostModel/AMDGPU/add-sub.ll

 define amdgpu_kernel void @add_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %vaddr, <2 x i32> %b) #0 {
   %vec = load <2 x i32>, <2 x i32> addrspace(1)* %vaddr
   %add = add <2 x i32> %vec, %b
   store <2 x i32> %add, <2 x i32> addrspace(1)* %out
   ret void
 }
 
 ; CHECK: 'add_v3i32'
-; CHECK: estimated cost of 3 for {{.*}} add <3 x i32>
+; Allow for 4 when v3i32 is illegal and TargetLowering thinks it needs widening,
+; and 3 when it is legal.
+; CHECK: estimated cost of {{[34]}} for {{.*}} add <3 x i32>
 define amdgpu_kernel void @add_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %vaddr, <3 x i32> %b) #0 {
   %vec = load <3 x i32>, <3 x i32> addrspace(1)* %vaddr
   %add = add <3 x i32> %vec, %b
   store <3 x i32> %add, <3 x i32> addrspace(1)* %out
   ret void
 }
 
 ; CHECK: 'add_v4i32'
 ; CHECK: estimated cost of 4 for {{.*}} add <4 x i32>
 define amdgpu_kernel void @add_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %vaddr, <4 x i32> %b) #0 {
   %vec = load <4 x i32>, <4 x i32> addrspace(1)* %vaddr
   %add = add <4 x i32> %vec, %b
   store <4 x i32> %add, <4 x i32> addrspace(1)* %out
   ret void
 }
 
+; CHECK: 'add_v5i32'
+; Allow for 8 when v3i32 is illegal and TargetLowering thinks it needs widening,
+; and 5 when it is legal.
+; CHECK: estimated cost of {{[58]}} for {{.*}} add <5 x i32>
+define amdgpu_kernel void @add_v5i32(<5 x i32> addrspace(1)* %out, <5 x i32> addrspace(1)* %vaddr, <5 x i32> %b) #0 {
+  %vec = load <5 x i32>, <5 x i32> addrspace(1)* %vaddr
+  %add = add <5 x i32> %vec, %b
+  store <5 x i32> %add, <5 x i32> addrspace(1)* %out
+  ret void
+}
+
 ; CHECK: 'add_i64'
 ; CHECK: estimated cost of 2 for {{.*}} add i64
 define amdgpu_kernel void @add_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %vaddr, i64 %b) #0 {
   %vec = load i64, i64 addrspace(1)* %vaddr
   %add = add i64 %vec, %b
   store i64 %add, i64 addrspace(1)* %out
   ret void
 }

llvm/trunk/test/Analysis/CostModel/AMDGPU/extractelement.ll

 ; GCN: estimated cost of 0 for {{.*}} extractelement <4 x i32>
 define amdgpu_kernel void @extractelement_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %vaddr) {
   %vec = load <4 x i32>, <4 x i32> addrspace(1)* %vaddr
   %elt = extractelement <4 x i32> %vec, i32 1
   store i32 %elt, i32 addrspace(1)* %out
   ret void
 }
 
+; GCN: 'extractelement_v5i32'
+; GCN: estimated cost of 0 for {{.*}} extractelement <5 x i32>
+define amdgpu_kernel void @extractelement_v5i32(i32 addrspace(1)* %out, <5 x i32> addrspace(1)* %vaddr) {
+  %vec = load <5 x i32>, <5 x i32> addrspace(1)* %vaddr
+  %elt = extractelement <5 x i32> %vec, i32 1
+  store i32 %elt, i32 addrspace(1)* %out
+  ret void
+}
+
 ; GCN: 'extractelement_v8i32'
 ; GCN: estimated cost of 0 for {{.*}} extractelement <8 x i32>
 define amdgpu_kernel void @extractelement_v8i32(i32 addrspace(1)* %out, <8 x i32> addrspace(1)* %vaddr) {
   %vec = load <8 x i32>, <8 x i32> addrspace(1)* %vaddr
   %elt = extractelement <8 x i32> %vec, i32 1
   store i32 %elt, i32 addrspace(1)* %out
   ret void
 }

llvm/trunk/test/Analysis/CostModel/AMDGPU/fabs.ll

 ; CHECK: estimated cost of 0 for {{.*}} call <3 x float> @llvm.fabs.v3f32
 define amdgpu_kernel void @fabs_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr) #0 {
   %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
   %fabs = call <3 x float> @llvm.fabs.v3f32(<3 x float> %vec) #1
   store <3 x float> %fabs, <3 x float> addrspace(1)* %out
   ret void
 }
 
+; CHECK: 'fabs_v5f32'
+; CHECK: estimated cost of 0 for {{.*}} call <5 x float> @llvm.fabs.v5f32
+define amdgpu_kernel void @fabs_v5f32(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr) #0 {
+  %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr
+  %fabs = call <5 x float> @llvm.fabs.v5f32(<5 x float> %vec) #1
+  store <5 x float> %fabs, <5 x float> addrspace(1)* %out
+  ret void
+}
+
 ; CHECK: 'fabs_f64'
 ; CHECK: estimated cost of 0 for {{.*}} call double @llvm.fabs.f64
 define amdgpu_kernel void @fabs_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr) #0 {
   %vec = load double, double addrspace(1)* %vaddr
   %fabs = call double @llvm.fabs.f64(double %vec) #1
   store double %fabs, double addrspace(1)* %out
   ret void
 }
define amdgpu_kernel void @fabs_v3f16(<3 x half> addrspace(1)* %out, <3 x half> addrspace(1)* %vaddr) #0 {
   %fabs = call <3 x half> @llvm.fabs.v3f16(<3 x half> %vec) #1
   store <3 x half> %fabs, <3 x half> addrspace(1)* %out
   ret void
 }
 
 declare float @llvm.fabs.f32(float) #1
 declare <2 x float> @llvm.fabs.v2f32(<2 x float>) #1
 declare <3 x float> @llvm.fabs.v3f32(<3 x float>) #1
+declare <5 x float> @llvm.fabs.v5f32(<5 x float>) #1
 
 declare double @llvm.fabs.f64(double) #1
 declare <2 x double> @llvm.fabs.v2f64(<2 x double>) #1
 declare <3 x double> @llvm.fabs.v3f64(<3 x double>) #1
 
 declare half @llvm.fabs.f16(half) #1
 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1
 declare <3 x half> @llvm.fabs.v3f16(<3 x half>) #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }

llvm/trunk/test/Analysis/CostModel/AMDGPU/fadd.ll

 define amdgpu_kernel void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
   %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
   %add = fadd <2 x float> %vec, %b
   store <2 x float> %add, <2 x float> addrspace(1)* %out
   ret void
 }
 
 ; ALL: 'fadd_v3f32'
-; ALL: estimated cost of 3 for {{.*}} fadd <3 x float>
+; Allow for 4 when v3f32 is illegal and TargetLowering thinks it needs widening,
+; and 3 when it is legal.
+; ALL: estimated cost of {{[34]}} for {{.*}} fadd <3 x float>
 define amdgpu_kernel void @fadd_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
   %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
   %add = fadd <3 x float> %vec, %b
   store <3 x float> %add, <3 x float> addrspace(1)* %out
   ret void
 }
 
+; ALL: 'fadd_v5f32'
+; Allow for 8 when v5f32 is illegal and TargetLowering thinks it needs widening,
+; and 5 when it is legal.
+; ALL: estimated cost of {{[58]}} for {{.*}} fadd <5 x float>
+define amdgpu_kernel void @fadd_v5f32(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr, <5 x float> %b) #0 {
+  %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr
+  %add = fadd <5 x float> %vec, %b
+  store <5 x float> %add, <5 x float> addrspace(1)* %out
+  ret void
+}
+
 ; ALL: 'fadd_f64'
 ; FASTF64: estimated cost of 2 for {{.*}} fadd double
 ; SLOWF64: estimated cost of 3 for {{.*}} fadd double
 define amdgpu_kernel void @fadd_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
   %vec = load double, double addrspace(1)* %vaddr
   %add = fadd double %vec, %b
   store double %add, double addrspace(1)* %out
   ret void

llvm/trunk/test/Analysis/CostModel/AMDGPU/fdiv.ll

 define amdgpu_kernel void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
   %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
   %add = fdiv <2 x float> %vec, %b
   store <2 x float> %add, <2 x float> addrspace(1)* %out
   ret void
 }
 
 ; ALL: 'fdiv_v3f32'
-; NOFP32DENORM: estimated cost of 36 for {{.*}} fdiv <3 x float>
-; FP32DENORMS: estimated cost of 30 for {{.*}} fdiv <3 x float>
+; Allow for 48/40 when v3f32 is illegal and TargetLowering thinks it needs widening,
+; and 36/30 when it is legal.
+; NOFP32DENORM: estimated cost of {{36|48}} for {{.*}} fdiv <3 x float>
+; FP32DENORMS: estimated cost of {{30|40}} for {{.*}} fdiv <3 x float>
 define amdgpu_kernel void @fdiv_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
   %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
   %add = fdiv <3 x float> %vec, %b
   store <3 x float> %add, <3 x float> addrspace(1)* %out
   ret void
 }
 
+; ALL: 'fdiv_v5f32'
+; Allow for 96/80 when v5f32 is illegal and TargetLowering thinks it needs widening,
+; and 60/50 when it is legal.
+; NOFP32DENORM: estimated cost of {{96|60}} for {{.*}} fdiv <5 x float>
+; FP32DENORMS: estimated cost of {{80|50}} for {{.*}} fdiv <5 x float>
+define amdgpu_kernel void @fdiv_v5f32(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr, <5 x float> %b) #0 {
+  %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr
+  %add = fdiv <5 x float> %vec, %b
+  store <5 x float> %add, <5 x float> addrspace(1)* %out
+  ret void
+}
+
 ; ALL: 'fdiv_f64'
 ; CIFASTF64: estimated cost of 29 for {{.*}} fdiv double
 ; CISLOWF64: estimated cost of 33 for {{.*}} fdiv double
 ; SIFASTF64: estimated cost of 32 for {{.*}} fdiv double
 ; SISLOWF64: estimated cost of 36 for {{.*}} fdiv double
 define amdgpu_kernel void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
   %vec = load double, double addrspace(1)* %vaddr
   %add = fdiv double %vec, %b

llvm/trunk/test/Analysis/CostModel/AMDGPU/fmul.ll

 define amdgpu_kernel void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
   %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
   %add = fmul <2 x float> %vec, %b
   store <2 x float> %add, <2 x float> addrspace(1)* %out
   ret void
 }
 
 ; ALL: 'fmul_v3f32'
-; ALL: estimated cost of 3 for {{.*}} fmul <3 x float>
+; Allow for 4 when v3f32 is illegal and TargetLowering thinks it needs widening,
+; and 3 when it is legal.
+; ALL: estimated cost of {{[34]}} for {{.*}} fmul <3 x float>
 define amdgpu_kernel void @fmul_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
   %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
   %add = fmul <3 x float> %vec, %b
   store <3 x float> %add, <3 x float> addrspace(1)* %out
   ret void
 }
 
+; ALL: 'fmul_v5f32'
+; Allow for 8 when v5f32 is illegal and TargetLowering thinks it needs widening,
+; and 5 when it is legal.
+; ALL: estimated cost of {{[58]}} for {{.*}} fmul <5 x float>
+define amdgpu_kernel void @fmul_v5f32(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr, <5 x float> %b) #0 {
+  %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr
+  %add = fmul <5 x float> %vec, %b
+  store <5 x float> %add, <5 x float> addrspace(1)* %out
+  ret void
+}
+
 ; ALL: 'fmul_f64'
 ; FASTF64: estimated cost of 2 for {{.*}} fmul double
 ; SLOWF64: estimated cost of 3 for {{.*}} fmul double
 define amdgpu_kernel void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
   %vec = load double, double addrspace(1)* %vaddr
   %add = fmul double %vec, %b
   store double %add, double addrspace(1)* %out
   ret void

llvm/trunk/test/Analysis/CostModel/AMDGPU/fsub.ll

 define amdgpu_kernel void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %vaddr, <2 x float> %b) #0 {
   %vec = load <2 x float>, <2 x float> addrspace(1)* %vaddr
   %add = fsub <2 x float> %vec, %b
   store <2 x float> %add, <2 x float> addrspace(1)* %out
   ret void
 }
 
 ; ALL: 'fsub_v3f32'
-; ALL: estimated cost of 3 for {{.*}} fsub <3 x float>
+; Allow for 4 when v3f32 is illegal and TargetLowering thinks it needs widening,
+; and 3 when it is legal.
+; ALL: estimated cost of {{[34]}} for {{.*}} fsub <3 x float>
 define amdgpu_kernel void @fsub_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %vaddr, <3 x float> %b) #0 {
   %vec = load <3 x float>, <3 x float> addrspace(1)* %vaddr
   %add = fsub <3 x float> %vec, %b
   store <3 x float> %add, <3 x float> addrspace(1)* %out
   ret void
 }
 
+; ALL: 'fsub_v5f32'
+; Allow for 8 when v5f32 is illegal and TargetLowering thinks it needs widening,
+; and 5 when it is legal.
+; ALL: estimated cost of {{[58]}} for {{.*}} fsub <5 x float>
+define amdgpu_kernel void @fsub_v5f32(<5 x float> addrspace(1)* %out, <5 x float> addrspace(1)* %vaddr, <5 x float> %b) #0 {
+  %vec = load <5 x float>, <5 x float> addrspace(1)* %vaddr
+  %add = fsub <5 x float> %vec, %b
+  store <5 x float> %add, <5 x float> addrspace(1)* %out
+  ret void
+}
+
 ; ALL: 'fsub_f64'
 ; FASTF64: estimated cost of 2 for {{.*}} fsub double
 ; SLOWF64: estimated cost of 3 for {{.*}} fsub double
 define amdgpu_kernel void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %vaddr, double %b) #0 {
   %vec = load double, double addrspace(1)* %vaddr
   %add = fsub double %vec, %b
   store double %add, double addrspace(1)* %out
   ret void

llvm/trunk/test/Analysis/CostModel/AMDGPU/mul.ll

 define amdgpu_kernel void @mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %vaddr, <2 x i32> %b) #0 {
   %vec = load <2 x i32>, <2 x i32> addrspace(1)* %vaddr
   %mul = mul <2 x i32> %vec, %b
   store <2 x i32> %mul, <2 x i32> addrspace(1)* %out
   ret void
 }
 
 ; CHECK: 'mul_v3i32'
-; CHECK: estimated cost of 9 for {{.*}} mul <3 x i32>
+; Allow for 12 when v3i32 is illegal and TargetLowering thinks it needs widening,
+; and 9 when it is legal.
+; CHECK: estimated cost of {{9|12}} for {{.*}} mul <3 x i32>
 define amdgpu_kernel void @mul_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %vaddr, <3 x i32> %b) #0 {
   %vec = load <3 x i32>, <3 x i32> addrspace(1)* %vaddr
   %mul = mul <3 x i32> %vec, %b
   store <3 x i32> %mul, <3 x i32> addrspace(1)* %out
   ret void
 }
 
+; CHECK: 'mul_v5i32'
+; Allow for 24 when v5i32 is illegal and TargetLowering thinks it needs widening,
+; and 15 when it is legal.
+; CHECK: estimated cost of {{15|24}} for {{.*}} mul <5 x i32>
+define amdgpu_kernel void @mul_v5i32(<5 x i32> addrspace(1)* %out, <5 x i32> addrspace(1)* %vaddr, <5 x i32> %b) #0 {
+  %vec = load <5 x i32>, <5 x i32> addrspace(1)* %vaddr
+  %mul = mul <5 x i32> %vec, %b
+  store <5 x i32> %mul, <5 x i32> addrspace(1)* %out
+  ret void
+}
+
 ; CHECK: 'mul_v4i32'
 ; CHECK: estimated cost of 12 for {{.*}} mul <4 x i32>
 define amdgpu_kernel void @mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %vaddr, <4 x i32> %b) #0 {
   %vec = load <4 x i32>, <4 x i32> addrspace(1)* %vaddr
   %mul = mul <4 x i32> %vec, %b
   store <4 x i32> %mul, <4 x i32> addrspace(1)* %out
   ret void
 }

llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll

 declare hidden void @external_void_func_v3i64(<3 x i64>) #0
 declare hidden void @external_void_func_v4i64(<4 x i64>) #0
 
 declare hidden void @external_void_func_f16(half) #0
 declare hidden void @external_void_func_f32(float) #0
 declare hidden void @external_void_func_f64(double) #0
 declare hidden void @external_void_func_v2f32(<2 x float>) #0
 declare hidden void @external_void_func_v2f64(<2 x double>) #0
+declare hidden void @external_void_func_v3f32(<3 x float>) #0
 declare hidden void @external_void_func_v3f64(<3 x double>) #0
+declare hidden void @external_void_func_v5f32(<5 x float>) #0
 
 declare hidden void @external_void_func_v2i16(<2 x i16>) #0
 declare hidden void @external_void_func_v2f16(<2 x half>) #0
 declare hidden void @external_void_func_v3i16(<3 x i16>) #0
 declare hidden void @external_void_func_v3f16(<3 x half>) #0
 declare hidden void @external_void_func_v4i16(<4 x i16>) #0
 declare hidden void @external_void_func_v4f16(<4 x half>) #0
 
 declare hidden void @external_void_func_v2i32(<2 x i32>) #0
 declare hidden void @external_void_func_v3i32(<3 x i32>) #0
 declare hidden void @external_void_func_v3i32_i32(<3 x i32>, i32) #0
 declare hidden void @external_void_func_v4i32(<4 x i32>) #0
+declare hidden void @external_void_func_v5i32(<5 x i32>) #0
 declare hidden void @external_void_func_v8i32(<8 x i32>) #0
 declare hidden void @external_void_func_v16i32(<16 x i32>) #0
 declare hidden void @external_void_func_v32i32(<32 x i32>) #0
 declare hidden void @external_void_func_v32i32_i32(<32 x i32>, i32) #0
 
 ; return value and argument
 declare hidden i32 @external_i32_func_i32(i32) #0
 

 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @test_call_external_void_func_v2f32_imm() #0 {
   call void @external_void_func_v2f32(<2 x float> <float 1.0, float 2.0>)
   ret void
 }
 
+; GCN-LABEL: {{^}}test_call_external_void_func_v3f32_imm:
+; GCN-DAG: v_mov_b32_e32 v0, 1.0
+; GCN-DAG: v_mov_b32_e32 v1, 2.0
+; GCN-DAG: v_mov_b32_e32 v2, 4.0
+; GCN-NOT: v3,
+; GCN: s_swappc_b64
+define amdgpu_kernel void @test_call_external_void_func_v3f32_imm() #0 {
+  call void @external_void_func_v3f32(<3 x float> <float 1.0, float 2.0, float 4.0>)
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_call_external_void_func_v5f32_imm:
+; GCN-DAG: v_mov_b32_e32 v0, 1.0
+; GCN-DAG: v_mov_b32_e32 v1, 2.0
+; GCN-DAG: v_mov_b32_e32 v2, 4.0
+; GCN-DAG: v_mov_b32_e32 v3, -1.0
+; GCN-DAG: v_mov_b32_e32 v4, 0.5
+; GCN-NOT: v5,
+; GCN: s_swappc_b64
+define amdgpu_kernel void @test_call_external_void_func_v5f32_imm() #0 {
+  call void @external_void_func_v5f32(<5 x float> <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>)
+  ret void
+}
+
 ; GCN-LABEL: {{^}}test_call_external_void_func_f64_imm:
 ; GCN: v_mov_b32_e32 v0, 0{{$}}
 ; GCN: v_mov_b32_e32 v1, 0x40100000
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @test_call_external_void_func_f64_imm() #0 {
   call void @external_void_func_f64(double 4.0)
   ret void
 }

 ; GCN-DAG: v_mov_b32_e32 v2, 3
 ; GCN-DAG: v_mov_b32_e32 v3, 4
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @test_call_external_void_func_v4i32_imm() #0 {
   call void @external_void_func_v4i32(<4 x i32> <i32 1, i32 2, i32 3, i32 4>)
   ret void
 }
 
+; GCN-LABEL: {{^}}test_call_external_void_func_v5i32_imm:
+; GCN-DAG: v_mov_b32_e32 v0, 1
+; GCN-DAG: v_mov_b32_e32 v1, 2
+; GCN-DAG: v_mov_b32_e32 v2, 3
+; GCN-DAG: v_mov_b32_e32 v3, 4
+; GCN-DAG: v_mov_b32_e32 v4, 5
+; GCN-NOT v5,
+; GCN: s_swappc_b64
+define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
+  call void @external_void_func_v5i32(<5 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5>)
+  ret void
+}
+
 ; GCN-LABEL: {{^}}test_call_external_void_func_v8i32:
 ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
 ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
 ; GCN: s_waitcnt
 ; GCN-NEXT: s_swappc_b64
 define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
   %ptr = load <8 x i32> addrspace(1)*, <8 x i32> addrspace(1)* addrspace(4)* undef
   %val = load <8 x i32>, <8 x i32> addrspace(1)* %ptr

 ; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:16 ; 4-byte Folded Reload
 ; GCN: s_setpc_b64
 define void @tail_call_stack_passed_arg_alignment_v32i32_f64(<32 x i32> %val, double %tmp) #0 {
 entry:
   tail call void @stack_passed_f64_arg(<32 x i32> %val, double %tmp)
   ret void
 }
 
+; GCN-LABEL: {{^}}stack_12xv3i32:
+; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
+; GCN: buffer_store_dword [[REG15]], {{.*}} offset:16
+; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
+; GCN: buffer_store_dword [[REG14]], {{.*}} offset:12
+; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
+; GCN: buffer_store_dword [[REG13]], {{.*}} offset:8
+; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
+; GCN: buffer_store_dword [[REG12]], {{.*}} offset:4
+; GCN: v_mov_b32_e32 v31, 11
+; GCN: s_getpc
+define void @stack_12xv3i32() #0 {
+entry:
+  call void @external_void_func_12xv3i32(
+      <3 x i32><i32 0, i32 0, i32 0>,
+      <3 x i32><i32 1, i32 1, i32 1>,
+      <3 x i32><i32 2, i32 2, i32 2>,
+      <3 x i32><i32 3, i32 3, i32 3>,
+      <3 x i32><i32 4, i32 4, i32 4>,
+      <3 x i32><i32 5, i32 5, i32 5>,
+      <3 x i32><i32 6, i32 6, i32 6>,
+      <3 x i32><i32 7, i32 7, i32 7>,
+      <3 x i32><i32 8, i32 8, i32 8>,
+      <3 x i32><i32 9, i32 9, i32 9>,
+      <3 x i32><i32 10, i32 11, i32 12>,
+      <3 x i32><i32 13, i32 14, i32 15>)
+  ret void
+}
+
+; GCN-LABEL: {{^}}stack_12xv3f32:
+; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000
+; GCN: buffer_store_dword [[REG15]], {{.*}} offset:16
+; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000
+; GCN: buffer_store_dword [[REG14]], {{.*}} offset:12
+; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000
+; GCN: buffer_store_dword [[REG13]], {{.*}} offset:8
+; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000
+; GCN: buffer_store_dword [[REG12]], {{.*}} offset:4
+; GCN: v_mov_b32_e32 v31, 0x41300000
+; GCN: s_getpc
+define void @stack_12xv3f32() #0 {
+entry:
+  call void @external_void_func_12xv3f32(
+      <3 x float><float 0.0, float 0.0, float 0.0>,
+      <3 x float><float 1.0, float 1.0, float 1.0>,
+      <3 x float><float 2.0, float 2.0, float 2.0>,
+      <3 x float><float 3.0, float 3.0, float 3.0>,
+      <3 x float><float 4.0, float 4.0, float 4.0>,
+      <3 x float><float 5.0, float 5.0, float 5.0>,
+      <3 x float><float 6.0, float 6.0, float 6.0>,
+      <3 x float><float 7.0, float 7.0, float 7.0>,
+      <3 x float><float 8.0, float 8.0, float 8.0>,
+      <3 x float><float 9.0, float 9.0, float 9.0>,
+      <3 x float><float 10.0, float 11.0, float 12.0>,
+      <3 x float><float 13.0, float 14.0, float 15.0>)
+  ret void
+}
+
+; GCN-LABEL: {{^}}stack_8xv5i32:
+; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 15
+; GCN: buffer_store_dword [[REG15]], {{.*}} offset:32
+; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 14
+; GCN: buffer_store_dword [[REG14]], {{.*}} offset:28
+; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 13
+; GCN: buffer_store_dword [[REG13]], {{.*}} offset:24
+; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 12
+; GCN: buffer_store_dword [[REG12]], {{.*}} offset:20
+; GCN: v_mov_b32_e32 [[REG11:v[0-9]+]], 11
+; GCN: buffer_store_dword [[REG11]], {{.*}} offset:16
+; GCN: v_mov_b32_e32 [[REG10:v[0-9]+]], 10
+; GCN: buffer_store_dword [[REG10]], {{.*}} offset:12
+; GCN: v_mov_b32_e32 [[REG9:v[0-9]+]], 9
+; GCN: buffer_store_dword [[REG9]], {{.*}} offset:8
+; GCN: v_mov_b32_e32 [[REG8:v[0-9]+]], 8
+; GCN: buffer_store_dword [[REG8]], {{.*}} offset:4
+; GCN: v_mov_b32_e32 v31, 7
+; GCN: s_getpc
+define void @stack_8xv5i32() #0 {
+entry:
+  call void @external_void_func_8xv5i32(
+      <5 x i32><i32 0, i32 0, i32 0, i32 0, i32 0>,
+      <5 x i32><i32 1, i32 1, i32 1, i32 1, i32 1>,
+      <5 x i32><i32 2, i32 2, i32 2, i32 2, i32 2>,
+      <5 x i32><i32 3, i32 3, i32 3, i32 3, i32 3>,
+      <5 x i32><i32 4, i32 4, i32 4, i32 4, i32 4>,
+      <5 x i32><i32 5, i32 5, i32 5, i32 5, i32 5>,
+      <5 x i32><i32 6, i32 7, i32 8, i32 9, i32 10>,
+      <5 x i32><i32 11, i32 12, i32 13, i32 14, i32 15>)
+  ret void
+}
+
+; GCN-LABEL: {{^}}stack_8xv5f32:
+; GCN: v_mov_b32_e32 [[REG15:v[0-9]+]], 0x41700000
+; GCN: buffer_store_dword [[REG15]], {{.*}} offset:32
+; GCN: v_mov_b32_e32 [[REG14:v[0-9]+]], 0x41600000
+; GCN: buffer_store_dword [[REG14]], {{.*}} offset:28
+; GCN: v_mov_b32_e32 [[REG13:v[0-9]+]], 0x41500000
+; GCN: buffer_store_dword [[REG13]], {{.*}} offset:24
+; GCN: v_mov_b32_e32 [[REG12:v[0-9]+]], 0x41400000
+; GCN: buffer_store_dword [[REG12]], {{.*}} offset:20
+; GCN: v_mov_b32_e32 [[REG11:v[0-9]+]], 0x41300000
+; GCN: buffer_store_dword [[REG11]], {{.*}} offset:16
+; GCN: v_mov_b32_e32 [[REG10:v[0-9]+]], 0x41200000
+; GCN: buffer_store_dword [[REG10]], {{.*}} offset:12
+; GCN: v_mov_b32_e32 [[REG9:v[0-9]+]], 0x41100000
+; GCN: buffer_store_dword [[REG9]], {{.*}} offset:8
+; GCN: v_mov_b32_e32 [[REG8:v[0-9]+]], 0x41000000
+; GCN: buffer_store_dword [[REG8]], {{.*}} offset:4
+; GCN: v_mov_b32_e32 v31, 0x40e00000
+; GCN: s_getpc
+define void @stack_8xv5f32() #0 {
+entry:
+  call void @external_void_func_8xv5f32(
+      <5 x float><float 0.0, float 0.0, float 0.0, float 0.0, float 0.0>,
+      <5 x float><float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>,
+      <5 x float><float 2.0, float 2.0, float 2.0, float 2.0, float 2.0>,
+      <5 x float><float 3.0, float 3.0, float 3.0, float 3.0, float 3.0>,
+      <5 x float><float 4.0, float 4.0, float 4.0, float 4.0, float 4.0>,
+      <5 x float><float 5.0, float 5.0, float 5.0, float 5.0, float 5.0>,
+      <5 x float><float 6.0, float 7.0, float 8.0, float 9.0, float 10.0>,
+      <5 x float><float 11.0, float 12.0, float 13.0, float 14.0, float 15.0>)
+  ret void
+}
+
 declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval align 16) #0
 declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0
-
+declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>,
+    <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0
+declare hidden void @external_void_func_8xv5i32(<5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>,
+    <5 x i32>, <5 x i32>, <5 x i32>, <5 x i32>) #0
+declare hidden void @external_void_func_12xv3f32(<3 x float>, <3 x float>, <3 x float>, <3 x float>,
+    <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>, <3 x float>) #0
+declare hidden void @external_void_func_8xv5f32(<5 x float>, <5 x float>, <5 x float>, <5 x float>,
+    <5 x float>, <5 x float>, <5 x float>, <5 x float>) #0
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }
 attributes #2 = { nounwind noinline }

llvm/trunk/test/CodeGen/AMDGPU/call-return-types.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX89 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX89 %s
 
 declare void @external_void_func_void() #0
 
 declare i1 @external_i1_func_void() #0
 declare zeroext i1 @external_i1_zeroext_func_void() #0
 declare signext i1 @external_i1_signext_func_void() #0
 
 declare i8 @external_i8_func_void() #0

 declare i32 @external_i32_func_void() #0
 declare i64 @external_i64_func_void() #0
 declare half @external_f16_func_void() #0
 declare float @external_f32_func_void() #0
 declare double @external_f64_func_void() #0
 
 declare <2 x half> @external_v2f16_func_void() #0
 declare <4 x half> @external_v4f16_func_void() #0
+declare <3 x float> @external_v3f32_func_void() #0
+declare <5 x float> @external_v5f32_func_void() #0
 declare <2 x double> @external_v2f64_func_void() #0
 
 declare <2 x i32> @external_v2i32_func_void() #0
 declare <3 x i32> @external_v3i32_func_void() #0
 declare <4 x i32> @external_v4i32_func_void() #0
 declare <5 x i32> @external_v5i32_func_void() #0
 declare <8 x i32> @external_v8i32_func_void() #0
 declare <16 x i32> @external_v16i32_func_void() #0

 ; GCN-LABEL: {{^}}test_call_external_v2i32_func_void:
 define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {
   %val = call <2 x i32> @external_v2i32_func_void()
   store volatile <2 x i32> %val, <2 x i32> addrspace(1)* undef
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_v3i32_func_void:
+; GCN: s_swappc
+; GFX7-DAG: flat_store_dwordx2 {{.*}}, v[0:1]
+; GFX7-DAG: flat_store_dword {{.*}}, v2
+; GFX89-DAG: buffer_store_dwordx2 v[0:1]
+; GFX89-DAG: buffer_store_dword v2
 define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {
   %val = call <3 x i32> @external_v3i32_func_void()
   store volatile <3 x i32> %val, <3 x i32> addrspace(1)* undef, align 8
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_v4i32_func_void:
 define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {
   %val = call <4 x i32> @external_v4i32_func_void()
   store volatile <4 x i32> %val, <4 x i32> addrspace(1)* undef, align 8
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_v5i32_func_void:
+; GCN: s_swappc
+; GFX7-DAG: flat_store_dwordx4 {{.*}}, v[0:3]
+; GFX7-DAG: flat_store_dword {{.*}}, v4
+; GFX89-DAG: buffer_store_dwordx4 v[0:3]
+; GFX89-DAG: buffer_store_dword v4
 define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {
   %val = call <5 x i32> @external_v5i32_func_void()
   store volatile <5 x i32> %val, <5 x i32> addrspace(1)* undef, align 8
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_call_external_v8i32_func_void:
 define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {

 
 ; GCN-LABEL: {{^}}test_call_external_v4f16_func_void:
 define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {
   %val = call <4 x half> @external_v4f16_func_void()
   store volatile <4 x half> %val, <4 x half> addrspace(1)* undef
   ret void
 }
 
+; GCN-LABEL: {{^}}test_call_external_v3f32_func_void:
+; GCN: s_swappc
+; GFX7-DAG: flat_store_dwordx2 {{.*}}, v[0:1]
+; GFX7-DAG: flat_store_dword {{.*}}, v2
+; GFX89-DAG: buffer_store_dwordx2 v[0:1]
+; GFX89-DAG: buffer_store_dword v2
+define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {
+  %val = call <3 x float> @external_v3f32_func_void()
+  store volatile <3 x float> %val, <3 x float> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_call_external_v5f32_func_void:
+; GCN: s_swappc
+; GFX7-DAG: flat_store_dwordx4 {{.*}}, v[0:3]
+; GFX7-DAG: flat_store_dword {{.*}}, v4
+; GFX89-DAG: buffer_store_dwordx4 v[0:3]
+; GFX89-DAG: buffer_store_dword v4
+define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {
+  %val = call <5 x float> @external_v5f32_func_void()
+  store volatile <5 x float> %val, <5 x float> addrspace(1)* undef
+  ret void
+}
+
 ; GCN-LABEL: {{^}}test_call_external_i32_i64_func_void:
 define amdgpu_kernel void @test_call_external_i32_i64_func_void() #0 {
   %val = call { i32, i64 } @external_i32_i64_func_void()
   %val.0 = extractvalue { i32, i64 } %val, 0
   %val.1 = extractvalue { i32, i64 } %val, 1
   store volatile i32 %val.0, i32 addrspace(1)* undef
   store volatile i64 %val.1, i64 addrspace(1)* undef
   ret void

llvm/trunk/test/CodeGen/AMDGPU/calling-conventions.ll

 ; SI: s_and_b32 s0, s0, 0xffff
 ; SI: s_or_b32 s0, s0, s1
 define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {
   %add = add <2 x i16> %arg0, <i16 1, i16 1>
   store <2 x i16> %add, <2 x i16> addrspace(1)* undef
   ret void
 }
 
+; GCN-LABEL: {{^}}ps_mesa_inreg_v3i32:
+; GCN-DAG: s_add_i32 s0, s0, 1
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
+define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {
+  %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
+  store <3 x i32> %add, <3 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_v3f32:
+; GCN-DAG: v_add_f32{{.*}}, s0, 1.0
+; GCN-DAG: v_add_f32{{.*}}, s1, 2.0
+; GCN-DAG: v_add_f32{{.*}}, s2, 4.0
+define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) {
+  %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
+  store <3 x float> %add, <3 x float> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_v5i32:
+; GCN-DAG: s_add_i32 s0, s0, 1
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s1, 2
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s3, 4
+; GCN-DAG: s_add_i32 s{{[0-9]*}}, s4, 5
+define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) {
+  %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
+  store <5 x i32> %add, <5 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_inreg_v5f32:
+; GCN-DAG: v_add_f32{{.*}}, s0, 1.0
+; GCN-DAG: v_add_f32{{.*}}, s1, 2.0
+; GCN-DAG: v_add_f32{{.*}}, s2, 4.0
+; GCN-DAG: v_add_f32{{.*}}, s3, -1.0
+; GCN-DAG: v_add_f32{{.*}}, s4, 0.5
+define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) {
+  %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
+  store <5 x float> %add, <5 x float> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v3i32:
+; GCN-DAG: v_add_{{.*}}, 1, v0
+; GCN-DAG: v_add_{{.*}}, 2, v1
+; GCN-DAG: v_add_{{.*}}, 3, v2
+define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) {
+  %add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
+  store <3 x i32> %add, <3 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v3f32:
+; GCN-DAG: v_add_{{.*}}, 1.0, v0
+; GCN-DAG: v_add_{{.*}}, 2.0, v1
+; GCN-DAG: v_add_{{.*}}, 4.0, v2
+define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) {
+  %add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
+  store <3 x float> %add, <3 x float> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v5i32:
+; GCN-DAG: v_add_{{.*}}, 1, v0
+; GCN-DAG: v_add_{{.*}}, 2, v1
+; GCN-DAG: v_add_{{.*}}, 3, v2
+; GCN-DAG: v_add_{{.*}}, 4, v3
+; GCN-DAG: v_add_{{.*}}, 5, v4
+define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) {
+  %add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
+  store <5 x i32> %add, <5 x i32> addrspace(1)* undef
+  ret void
+}
+
+; GCN-LABEL: {{^}}ps_mesa_v5f32:
+; GCN-DAG: v_add_f32{{.*}}, 1.0, v0
+; GCN-DAG: v_add_f32{{.*}}, 2.0, v1
+; GCN-DAG: v_add_f32{{.*}}, 4.0, v2
+; GCN-DAG: v_add_f32{{.*}}, -1.0, v3
+; GCN-DAG: v_add_f32{{.*}}, 0.5, v4
+define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {
+  %add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
+  store <5 x float> %add, <5 x float> addrspace(1)* undef
+  ret void
+}
+
+
+
 attributes #0 = { nounwind noinline }

llvm/trunk/test/CodeGen/AMDGPU/kernel-args.ll

 ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
 ; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
 define amdgpu_kernel void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind {
 entry:
   store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4
   ret void
 }
 
+; FUNC-LABEL: {{^}}v5i8_arg:
+; HSA-GFX9: kernarg_segment_byte_size = 16
+; HSA-GFX9: kernarg_segment_alignment = 4
+
+; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
+; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
+; EGCM-DAG: VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 46
+
+; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
+
+; VI-MESA: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+; VI-HSA: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8
+define amdgpu_kernel void @v5i8_arg(<5 x i8> addrspace(1)* nocapture %out, <5 x i8> %in) nounwind {
+entry:
+  store <5 x i8> %in, <5 x i8> addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v5i16_arg:
+; HSA-GFX9: kernarg_segment_byte_size = 32
+; HSA-GFX9: kernarg_segment_alignment = 4
+
+; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 58
+; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 58
+; EGCM-DAG: VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 58
+
+; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
+
+; VI-HSA: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x8
+; VI-MESA: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
+define amdgpu_kernel void @v5i16_arg(<5 x i16> addrspace(1)* nocapture %out, <5 x i16> %in) nounwind {
+entry:
+  store <5 x i16> %in, <5 x i16> addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v5i32_arg:
+; HSA-GFX9: kernarg_segment_byte_size = 64
+; HSA-GFX9: kernarg_segment_alignment = 5
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
+; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
+; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x44
+; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20
+define amdgpu_kernel void @v5i32_arg(<5 x i32> addrspace(1)* nocapture %out, <5 x i32> %in) nounwind {
+entry:
+  store <5 x i32> %in, <5 x i32> addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v5f32_arg:
+; HSA-GFX9: kernarg_segment_byte_size = 64
+; HSA-GFX9: kernarg_segment_alignment = 5
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W
+; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x11
+; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x44
+; HSA-GFX9: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x20
+define amdgpu_kernel void @v5f32_arg(<5 x float> addrspace(1)* nocapture %out, <5 x float> %in) nounwind {
+entry:
+  store <5 x float> %in, <5 x float> addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v5i64_arg:
+; HSA-GFX9: kernarg_segment_byte_size = 128
+; HSA-GFX9: kernarg_segment_alignment = 6
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
+; SI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
+; SI-DAG: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x21
+; MESA-VI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
+; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x84
+; HSA-GFX9-DAG: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
+; HSA-GFX9-DAG: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x60
+define amdgpu_kernel void @v5i64_arg(<5 x i64> addrspace(1)* nocapture %out, <5 x i64> %in) nounwind {
+entry:
+  store <5 x i64> %in, <5 x i64> addrspace(1)* %out, align 8
+  ret void
+}
+
+; FUNC-LABEL: {{^}}v5f64_arg:
+; HSA-GFX9: kernarg_segment_byte_size = 128
+; HSA-GFX9: kernarg_segment_alignment = 6
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y
+; EGCM-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z
+; SI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x19
+; SI-DAG: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x21
+; MESA-VI-DAG: s_load_dwordx8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x64
+; MESA-VI-DAG: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x84
+; HSA-GFX9-DAG: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x40
+; HSA-GFX9-DAG: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x60
+define amdgpu_kernel void @v5f64_arg(<5 x double> addrspace(1)* nocapture %out, <5 x double> %in) nounwind {
+entry:
+  store <5 x double> %in, <5 x double> addrspace(1)* %out, align 8
+  ret void
+}
+
 ; FIXME: Lots of unpack and re-pack junk on VI
 ; FUNC-LABEL: {{^}}v8i8_arg:
 ; HSA-GFX9: kernarg_segment_byte_size = 16
 ; HSA-GFX9: kernarg_segment_alignment = 4
 ; EGCM: VTX_READ_8
 ; EGCM: VTX_READ_8
 ; EGCM: VTX_READ_8
 ; EGCM: VTX_READ_8