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[AMDGPU] Added v5i32 and v5f32 register classes
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Authored by tpr on Mar 4 2019, 7:14 AM.

Details

Summary

They are not used by anything yet, but a subsequent commit will start
using them for image ops that return 5 dwords.

Change-Id: I63e1904081e39a6d66e4eb96d51df25ad399d271

Diff Detail

Repository
rL LLVM

Event Timeline

tpr created this revision.Mar 4 2019, 7:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 4 2019, 7:14 AM
arsenm added inline comments.Mar 4 2019, 7:41 AM
lib/Target/AMDGPU/SIRegisterInfo.td
584 ↗(On Diff #189145)

Allocation priorities probably need to be shifted around again so it's ordered <all SGPRs in decreasing size, all VGPRs in decreasing size>

arsenm added a comment.Mar 4 2019, 7:42 AM

Also needs a spill test

tpr updated this revision to Diff 189575.Mar 6 2019, 1:27 PM

V2: Fixed missing part of change, including defaulting v5 operations to
expand. Fixed broken v5f32 select. Fixed reg class priorities.
Fixed spilling and asm constraints, and added sgpr spill test.

arsenm accepted this revision.Mar 6 2019, 1:38 PM

LGTM

This revision is now accepted and ready to land.Mar 6 2019, 1:38 PM
This revision was automatically updated to reflect the committed changes.