[RISCV] Add implied zero offset load/store alias patterns

[jrtc27]

Summary

Allow load/store instructions with implied zero offset for compatibility with GNU assembler.

[lewis-revill]

lib/Target/RISCV/RISCVInstrInfo.td

538

LW should not be guarded by IsRV64.

541

LD is missing here.

[lewis-revill]

Some basic tests should probably be included for completeness.

[jrtc27]

Ah, I already did this in my fork, covering all the compressed and floating-point instructions too, with a complete set of tests. Probably easiest if I just post that rather than you working to produce what would turn out to be nearly-identical code?

[apazos]

Yes James, please post your patch and tests. Kito quickly posted this one to unblock me.

[kito-cheng]

@jrtc27 feel free to upload your one, it's just a 5 minute quick patch :P

[jrtc27]

Support all memory instructions; add test coverage

[asb]

Thanks, this looks good to me. Needs a small fixup to apply cleanly to the previous patches in the queue (TODO comments in RISCVInstrInfo{F,D}.td were removed).

[jrtc27]

D50496 in the stack has now landed, so other than the TODO comments having been dropped this is now ready. Alex, are you happy to do that rebasing when you commit this, or would you like me to?

[asb]

In D57141#1404697, @jrtc27 wrote:

D50496 in the stack has now landed, so other than the TODO comments having been dropped this is now ready. Alex, are you happy to do that rebasing when you commit this, or would you like me to?

Committing now - thanks James!

lib/Target/RISCV/RISCVInstrInfo.td

 def PseudoLH  : PseudoLoad<"lh">;
 def PseudoLHU : PseudoLoad<"lhu">;
 def PseudoLW  : PseudoLoad<"lw">;
 
 def PseudoSB  : PseudoStore<"sb">;
 def PseudoSH  : PseudoStore<"sh">;
 def PseudoSW  : PseudoStore<"sw">;
 
+def : InstAlias<"lb  $rd, (${rs1})", (LB   GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lbu $rd, (${rs1})", (LBU  GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lh  $rd, (${rs1})", (LH   GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lhu $rd, (${rs1})", (LHU  GPR:$rd,  GPR:$rs1,     0), 0>;
+
+def : InstAlias<"sb $rs2, (${rs1})", (SB  GPR:$rs2,  GPR:$rs1,     0), 0>;
+def : InstAlias<"sh $rs2, (${rs1})", (SH  GPR:$rs2,  GPR:$rs1,     0), 0>;
+def : InstAlias<"sw $rs2, (${rs1})", (SW  GPR:$rs2,  GPR:$rs1,     0), 0>;
+
 let Predicates = [IsRV64] in {
 def PseudoLWU : PseudoLoad<"lwu">;
 def PseudoLD  : PseudoLoad<"ld">;
 def PseudoSD  : PseudoStore<"sd">;
+
+def : InstAlias<"lw  $rd, (${rs1})", (LW   GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"lwu $rd, (${rs1})", (LWU  GPR:$rd,  GPR:$rs1,     0), 0>;
+def : InstAlias<"sd $rs2, (${rs1})", (SD   GPR:$rs2, GPR:$rs1,     0), 0>;
+
 } // Predicates = [IsRV64]
 
 def : InstAlias<"mv $rd, $rs",   (ADDI GPR:$rd, GPR:$rs,       0)>;
 def : InstAlias<"not $rd, $rs",  (XORI GPR:$rd, GPR:$rs,      -1)>;
 def : InstAlias<"neg $rd, $rs",  (SUB  GPR:$rd,      X0, GPR:$rs)>;
 
 let Predicates = [IsRV64] in {
 def : InstAlias<"negw $rd, $rs",   (SUBW  GPR:$rd,      X0, GPR:$rs)>;