[RISCV] Add lowering of global TLS addresses

[lewis-revill]

Summary

This patch adds lowering for global TLS addresses for the TLS models of InitialExec, GlobalDynamic, LocalExec and LocalDynamic.

LocalExec support required using a 4-operand add instruction, which uses the fourth operand to express a relocation on the symbol. The necessary fixup is emitted when the instruction is emitted.

[jrtc27]

I'd rather see all the local-exec support moved into D55306; I don't think it makes much sense to add things here that don't yet work. Alternatively, to avoid lines that are then going to be modified again in D55306, you could merge the two? There aren't many extra changes in D55306.

[asb]

Thanks for sharing this patch series Lewis. As it happens @luismarques has been finishing off his own implementation of TLS support which this unfortunately clashes with. The upside is that we're in a good position to review this work!

Could you please refactor the patches so that MC layer changes occur separately to codegen. e.g. having one patch that adds the MC layer changes for for TLS and a second which adds the codegen changes.

[lewis-revill]

In D55305#1319651, @jrtc27 wrote:

I'd rather see all the local-exec support moved into D55306; I don't think it makes much sense to add things here that don't yet work. Alternatively, to avoid lines that are then going to be modified again in D55306, you could merge the two? There aren't many extra changes in D55306.

Yes sorry about that, I can do that.

In D55305#1319850, @asb wrote:

Thanks for sharing this patch series Lewis. As it happens @luismarques has been finishing off his own implementation of TLS support which this unfortunately clashes with. The upside is that we're in a good position to review this work!

Could you please refactor the patches so that MC layer changes occur separately to codegen. e.g. having one patch that adds the MC layer changes for for TLS and a second which adds the codegen changes.

OK, I'll look at doing that and incorporating existing MC patches where they exist.

[lewis-revill]

Merging D55306 into this, then splitting this patch into MC layer and Codegen

[lewis-revill]

Merged D55306 into this patch.

[lewis-revill]

Split into MC layer (patches D55341 D55342) and codegen (this patch)

[lewis-revill]

Rebased with updated dependencies.

[lewis-revill]

Rebase with updated dependencies. Use and expand the la.tls.ie and la.tls.gd pseudo instructions.

[lewis-revill]

Rebased and fixed FileCheck lines.

[lewis-revill]

lib/Target/RISCV/RISCVISelLowering.cpp

523

Am I correct in thinking this sequence should actually be opaque here, it causes a DAG with multiple load/stores of the same GlobalTLSAddress to only duplicate the ADDI relative to a single AddTPRel node... I know this would be safe for absolute addressing, but not for thread-pointer relative addressing?

[lewis-revill]

lib/Target/RISCV/RISCVISelLowering.cpp

523

Actually it appears GCC will do common subexpression elimination on this sequence with optimizations enabled so I would take that to mean it is safe to emit as it is.

[rogfer01]

lib/Target/RISCV/RISCVISelLowering.cpp

500

Because we run BranchRelaxation in addPreEmitPass but the expansion of these pseudos happens in addPreEmitPass2 I think we need to update RISCVInstrInfo::getInstSizeInBytes to state that PseudoLA_TLS_IE and PseudoLA_TLS_GD will take 8 bytes (otherwise we run into "fixup errors" because the relaxation has been done using an underestimation).

(Alternatively we could use the Size attribute in tablegen but currently only PseudoLI does this and we don't use that one in codegen, so that is probably OK)

Also I wonder if the attribute isAsmParserOnly = 1 should be updated to 0 so we are more honest with the current usage of these pseudos. That said from a cursory check in tablegen, that attribute does not seem very important at the moment.

[lewis-revill]

lib/Target/RISCV/RISCVISelLowering.cpp

500

Thanks, I'll make that change, I did the same for the PIC PseudoLA so I must have forgotten it for this.

The isAsmParser attribute seems to enforce that the pseudo instruction doesn't cross the barrier between CodeGen and MC. Might be worth removing it to prevent confusion, I could do that in a later patch since there are now a couple of pseudos like this.

[lewis-revill]

Add pseudo instructions to getInstSizeInBytes.

[rogfer01]

lib/Target/RISCV/RISCVISelLowering.cpp

528

I'm curious, is there a reason to have this unused parameter here? (other than symmetry with getStaticTLSAddr, that is).

Removing it could allow you to combine the two cases in lowerGlobalTLSAddress. That could make more obvious that in RISC-V we use the same sequence in both cases.

[lewis-revill]

Added nounwind to test functions.

[asb]

I added some very minor nits in comments, but other than those I think this is looking good to land. Thanks! It's also worth checking @rogfer01's suggestion before committing https://reviews.llvm.org/D55305#inline-553463

lib/Target/RISCV/RISCVISelLowering.cpp

500

Line is longer than 80 chars, git clang-format will reformat niclely (assuming you have the git-clang-format helper on your PATH)

538

Line is longer than 80 chars, git clang-format will reformat niclely (assuming you have the git-clang-format helper on your PATH)

574

The enumeration is fully covered, so we shouldn't have the default case here: https://llvm.org/docs/CodingStandards.html#don-t-use-default-labels-in-fully-covered-switches-over-enumerations

[lewis-revill]

Updated to address comments

lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

bool expandAuipcInstPair(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator &NextMBBI,
                            unsigned FlagsHi, unsigned SecondOpcode);
   bool expandLoadLocalAddress(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MBBI,
                               MachineBasicBlock::iterator &NextMBBI);
   bool expandLoadAddress(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MBBI,
                          MachineBasicBlock::iterator &NextMBBI);
+  bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator MBBI,
+                              MachineBasicBlock::iterator &NextMBBI);
+  bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator MBBI,
+                              MachineBasicBlock::iterator &NextMBBI);
 };
 
 char RISCVExpandPseudo::ID = 0;
 
 bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
   TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
   bool Modified = false;
   for (auto &MBB : MF)
bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
   case RISCV::PseudoCmpXchg64:
     return expandAtomicCmpXchg(MBB, MBBI, false, 64, NextMBBI);
   case RISCV::PseudoMaskedCmpXchg32:
     return expandAtomicCmpXchg(MBB, MBBI, true, 32, NextMBBI);
   case RISCV::PseudoLLA:
     return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA:
     return expandLoadAddress(MBB, MBBI, NextMBBI);
+  case RISCV::PseudoLA_TLS_IE:
+    return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
+  case RISCV::PseudoLA_TLS_GD:
+    return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
   }
 
   return false;
 }
 
 static unsigned getLRForRMW32(AtomicOrdering Ordering) {
   switch (Ordering) {
   default:
if (MF->getTarget().isPositionIndependent()) {
     FlagsHi = RISCVII::MO_GOT_HI;
   } else {
     SecondOpcode = RISCV::ADDI;
     FlagsHi = RISCVII::MO_PCREL_HI;
   }
   return expandAuipcInstPair(MBB, MBBI, NextMBBI, FlagsHi, SecondOpcode);
 }
 
+bool RISCVExpandPseudo::expandLoadTLSIEAddress(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI) {
+  MachineFunction *MF = MBB.getParent();
+
+  const auto &STI = MF->getSubtarget<RISCVSubtarget>();
+  unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
+  return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
+                             SecondOpcode);
+}
+
+bool RISCVExpandPseudo::expandLoadTLSGDAddress(
+    MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+    MachineBasicBlock::iterator &NextMBBI) {
+  return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
+                             RISCV::ADDI);
+}
+
 } // end of anonymous namespace
 
 INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
                 RISCV_EXPAND_PSEUDO_NAME, false, false)
 namespace llvm {
 
 FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
 
 } // end of namespace llvm

lib/Target/RISCV/RISCVISelLowering.h

private:
   bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                          Type *Ty) const override {
     return true;
   }
 
   template <class NodeTy>
   SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
 
+  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
+                           bool UseGOT) const;
+  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
+                            bool UseGOT) const;
+
   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
 
   bool isEligibleForTailCallOptimization(

lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.hasStdExtD()) {
     for (auto Op : FPOpToExtend)
       setOperationAction(Op, MVT::f64, Expand);
   }
 
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
 
+  setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
+
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
     setMinCmpXchgSizeInBits(32);
   } else {
     setMaxAtomicSizeInBitsSupported(0);
   }
 
   setBooleanContents(ZeroOrOneBooleanContent);
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   default:
     report_fatal_error("unimplemented operand");
   case ISD::GlobalAddress:
     return lowerGlobalAddress(Op, DAG);
   case ISD::BlockAddress:
     return lowerBlockAddress(Op, DAG);
   case ISD::ConstantPool:
     return lowerConstantPool(Op, DAG);
+  case ISD::GlobalTLSAddress:
+    return lowerGlobalTLSAddress(Op, DAG);
   case ISD::SELECT:
     return lowerSELECT(Op, DAG);
   case ISD::VASTART:
     return lowerVASTART(Op, DAG);
   case ISD::FRAMEADDR:
     return lowerFRAMEADDR(Op, DAG);
   case ISD::RETURNADDR:
     return lowerRETURNADDR(Op, DAG);

 
 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
                                                SelectionDAG &DAG) const {
   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
 
   return getAddr(N, DAG);
 }
 
+SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
+                                              SelectionDAG &DAG,
+                                              bool UseGOT) const {
+  SDLoc DL(N);
+  EVT Ty = getPointerTy(DAG.getDataLayout());
+  const GlobalValue *GV = N->getGlobal();
+  MVT XLenVT = Subtarget.getXLenVT();
+
+  if (UseGOT) {
+    // Use PC-relative addressing to access the GOT for this TLS symbol, then
+    // load the address from the GOT and add the thread pointer. This generates
+    // the pattern (PseudoLA_TLS_IE sym), which expands to
+    // (ld (auipc %tls_ie_pcrel_hi(sym)) %pcrel_lo(auipc)).
+    SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);
+    SDValue Load = SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_IE, DL, Ty, Addr), 0);
+
+    // Add the thread pointer.
+    SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
+    return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg);
+  }
+
+  // Generate a sequence for accessing the address relative to the thread
+  // pointer, with the appropriate adjustment for the thread pointer offset.
+  // This generates the pattern
+  // (add (add_tprel (lui %tprel_hi(sym)) tp %tprel_add(sym)) %tprel_lo(sym))
+  SDValue AddrHi =
+      DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_HI);
+  SDValue AddrAdd =
+      DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_ADD);
+  SDValue AddrLo =
+      DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_TPREL_LO);
+
+  SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
+  SDValue TPReg = DAG.getRegister(RISCV::X4, XLenVT);
+  SDValue MNAdd = SDValue(
+      DAG.getMachineNode(RISCV::PseudoAddTPRel, DL, Ty, MNHi, TPReg, AddrAdd),
+      0);
+  return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNAdd, AddrLo), 0);
+}
+
+SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
+                                               SelectionDAG &DAG,
+                                               bool UseGOT) const {
+  SDLoc DL(N);
+  EVT Ty = getPointerTy(DAG.getDataLayout());
+  IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());
+  const GlobalValue *GV = N->getGlobal();
+
+  // Use a PC-relative addressing mode to access the global dynamic GOT address.
+  // This generates the pattern (PseudoLA_TLS_GD sym), which expands to
+  // (addi (auipc %tls_gd_pcrel_hi(sym)) %pcrel_lo(auipc)).
+  SDValue Addr = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, 0);
+  SDValue Load = SDValue(DAG.getMachineNode(RISCV::PseudoLA_TLS_GD, DL, Ty, Addr), 0);
+
+  // Prepare argument list to generate call.
+  ArgListTy Args;
+  ArgListEntry Entry;
+  Entry.Node = Load;
+  Entry.Ty = CallTy;
+  Args.push_back(Entry);
+
+  // Setup call to __tls_get_addr.
+  TargetLowering::CallLoweringInfo CLI(DAG);
+  CLI.setDebugLoc(DL)
+      .setChain(DAG.getEntryNode())
+      .setLibCallee(CallingConv::C, CallTy,
+                    DAG.getExternalSymbol("__tls_get_addr", Ty),
+                    std::move(Args));
+
+  return LowerCallTo(CLI).first;
+}
+
+SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
+                                                   SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  EVT Ty = Op.getValueType();
+  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
+  int64_t Offset = N->getOffset();
+  MVT XLenVT = Subtarget.getXLenVT();
+
+  // Non-PIC TLS lowering should always use the LocalExec model.
+  TLSModel::Model Model = isPositionIndependent()
+                              ? getTargetMachine().getTLSModel(N->getGlobal())
+                              : TLSModel::LocalExec;
+
+  SDValue Addr;
+  switch (Model) {
+  default:
+    report_fatal_error("Unsupported TLS model");
+  case TLSModel::LocalExec:
+    Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
+    break;
+  case TLSModel::InitialExec:
+    Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
+    break;
+  case TLSModel::LocalDynamic:
+    Addr = getDynamicTLSAddr(N, DAG, /*UseGOT=*/false);
+    break;
+  case TLSModel::GeneralDynamic:
+    Addr = getDynamicTLSAddr(N, DAG, /*UseGOT=*/true);
+    break;
+  }
+
+  // In order to maximise the opportunity for common subexpression elimination,
+  // emit a separate ADD node for the global address offset instead of folding
+  // it in the global address node. Later peephole optimisations may choose to
+  // fold it back in when profitable.
+  if (Offset != 0)
+    return DAG.getNode(ISD::ADD, DL, Ty, Addr,
+                       DAG.getConstant(Offset, DL, XLenVT));
+  return Addr;
+}
+
 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   SDValue CondV = Op.getOperand(0);
   SDValue TrueV = Op.getOperand(1);
   SDValue FalseV = Op.getOperand(2);
   SDLoc DL(Op);
   MVT XLenVT = Subtarget.getXLenVT();
 
   // If the result type is XLenVT and CondV is the output of a SETCC node

lib/Target/RISCV/RISCVInstrInfo.cpp

unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL:
   case TargetOpcode::DBG_VALUE:
     return 0;
   case RISCV::PseudoCALL:
   case RISCV::PseudoTAIL:
   case RISCV::PseudoLLA:
   case RISCV::PseudoLA:
+  case RISCV::PseudoLA_TLS_IE:
+  case RISCV::PseudoLA_TLS_GD:
     return 8;
   case TargetOpcode::INLINEASM:
   case TargetOpcode::INLINEASM_BR: {
     const MachineFunction &MF = *MI.getParent()->getParent();
     const auto &TM = static_cast<const RISCVTargetMachine &>(MF.getTarget());
     return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
                               *TM.getMCAsmInfo());
   }

lib/Target/RISCV/RISCVMCInstLower.cpp

case RISCVII::MO_PCREL_LO:
     Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
     break;
   case RISCVII::MO_PCREL_HI:
     Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
     break;
   case RISCVII::MO_GOT_HI:
     Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
     break;
+  case RISCVII::MO_TPREL_LO:
+    Kind = RISCVMCExpr::VK_RISCV_TPREL_LO;
+    break;
+  case RISCVII::MO_TPREL_HI:
+    Kind = RISCVMCExpr::VK_RISCV_TPREL_HI;
+    break;
+  case RISCVII::MO_TPREL_ADD:
+    Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD;
+    break;
+  case RISCVII::MO_TLS_GOT_HI:
+    Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI;
+    break;
+  case RISCVII::MO_TLS_GD_HI:
+    Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
+    break;
   }
 
   const MCExpr *ME =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
 
   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
     ME = MCBinaryExpr::createAdd(
         ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);

lib/Target/RISCV/Utils/RISCVBaseInfo.h

 enum {
   MO_None,
   MO_CALL,
   MO_LO,
   MO_HI,
   MO_PCREL_LO,
   MO_PCREL_HI,
   MO_GOT_HI,
+  MO_TPREL_LO,
+  MO_TPREL_HI,
+  MO_TPREL_ADD,
+  MO_TLS_GOT_HI,
+  MO_TLS_GD_HI,
 };
 } // namespace RISCVII
 
 // Describes the predecessor/successor bits used in the FENCE instruction.
 namespace RISCVFenceField {
 enum FenceField {
   I = 8,
   O = 4,

test/CodeGen/RISCV/tls-models.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -relocation-model=pic < %s \
+; RUN:     | FileCheck -check-prefix=RV32-PIC %s
+; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s \
+; RUN:     | FileCheck -check-prefix=RV64-PIC %s
+; RUN: llc -mtriple=riscv32 < %s | FileCheck -check-prefix=NOPIC %s
+; RUN: llc -mtriple=riscv64 < %s | FileCheck -check-prefix=NOPIC %s
+
+; Check that TLS symbols are lowered correctly based on the specified
+; model.
+
+@unspecified = thread_local global i32 42
+@ld = thread_local(localdynamic) global i32 42
+@ie = thread_local(initialexec) global i32 42
+@le = thread_local(localexec) global i32 42
+
+
+; No model specified
+
+define i32* @f1() nounwind {
+; RV32-PIC-LABEL: f1:
+; RV32-PIC:       # %bb.0: # %entry
+; RV32-PIC-NEXT:    addi sp, sp, -16
+; RV32-PIC-NEXT:    sw ra, 12(sp)
+; RV32-PIC-NEXT:  .LBB0_1: # %entry
+; RV32-PIC-NEXT:    # Label of block must be emitted
+; RV32-PIC-NEXT:    auipc a0, %tls_gd_pcrel_hi(unspecified)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB0_1)
+; RV32-PIC-NEXT:    call __tls_get_addr@plt
+; RV32-PIC-NEXT:    lw ra, 12(sp)
+; RV32-PIC-NEXT:    addi sp, sp, 16
+; RV32-PIC-NEXT:    ret
+;
+; RV64-PIC-LABEL: f1:
+; RV64-PIC:       # %bb.0: # %entry
+; RV64-PIC-NEXT:    addi sp, sp, -16
+; RV64-PIC-NEXT:    sd ra, 8(sp)
+; RV64-PIC-NEXT:  .LBB0_1: # %entry
+; RV64-PIC-NEXT:    # Label of block must be emitted
+; RV64-PIC-NEXT:    auipc a0, %tls_gd_pcrel_hi(unspecified)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB0_1)
+; RV64-PIC-NEXT:    call __tls_get_addr@plt
+; RV64-PIC-NEXT:    ld ra, 8(sp)
+; RV64-PIC-NEXT:    addi sp, sp, 16
+; RV64-PIC-NEXT:    ret
+;
+; NOPIC-LABEL: f1:
+; NOPIC:       # %bb.0: # %entry
+; NOPIC-NEXT:    lui a0, %tprel_hi(unspecified)
+; NOPIC-NEXT:    add a0, a0, tp, %tprel_add(unspecified)
+; NOPIC-NEXT:    addi a0, a0, %tprel_lo(unspecified)
+; NOPIC-NEXT:    ret
+entry:
+  ret i32* @unspecified
+}
+
+
+; localdynamic specified
+
+define i32* @f2() nounwind {
+; RV32-PIC-LABEL: f2:
+; RV32-PIC:       # %bb.0: # %entry
+; RV32-PIC-NEXT:    addi sp, sp, -16
+; RV32-PIC-NEXT:    sw ra, 12(sp)
+; RV32-PIC-NEXT:  .LBB1_1: # %entry
+; RV32-PIC-NEXT:    # Label of block must be emitted
+; RV32-PIC-NEXT:    auipc a0, %tls_gd_pcrel_hi(ld)
+; RV32-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV32-PIC-NEXT:    call __tls_get_addr@plt
+; RV32-PIC-NEXT:    lw ra, 12(sp)
+; RV32-PIC-NEXT:    addi sp, sp, 16
+; RV32-PIC-NEXT:    ret
+;
+; RV64-PIC-LABEL: f2:
+; RV64-PIC:       # %bb.0: # %entry
+; RV64-PIC-NEXT:    addi sp, sp, -16
+; RV64-PIC-NEXT:    sd ra, 8(sp)
+; RV64-PIC-NEXT:  .LBB1_1: # %entry
+; RV64-PIC-NEXT:    # Label of block must be emitted
+; RV64-PIC-NEXT:    auipc a0, %tls_gd_pcrel_hi(ld)
+; RV64-PIC-NEXT:    addi a0, a0, %pcrel_lo(.LBB1_1)
+; RV64-PIC-NEXT:    call __tls_get_addr@plt
+; RV64-PIC-NEXT:    ld ra, 8(sp)
+; RV64-PIC-NEXT:    addi sp, sp, 16
+; RV64-PIC-NEXT:    ret
+;
+; NOPIC-LABEL: f2:
+; NOPIC:       # %bb.0: # %entry
+; NOPIC-NEXT:    lui a0, %tprel_hi(ld)
+; NOPIC-NEXT:    add a0, a0, tp, %tprel_add(ld)
+; NOPIC-NEXT:    addi a0, a0, %tprel_lo(ld)
+; NOPIC-NEXT:    ret
+entry:
+  ret i32* @ld
+}
+
+
+; initialexec specified
+
+define i32* @f3() nounwind {
+; RV32-PIC-LABEL: f3:
+; RV32-PIC:       # %bb.0: # %entry
+; RV32-PIC-NEXT:  .LBB2_1: # %entry
+; RV32-PIC-NEXT:    # Label of block must be emitted
+; RV32-PIC-NEXT:    auipc a0, %tls_ie_pcrel_hi(ie)
+; RV32-PIC-NEXT:    lw a0, %pcrel_lo(.LBB2_1)(a0)
+; RV32-PIC-NEXT:    add a0, a0, tp
+; RV32-PIC-NEXT:    ret
+;
+; RV64-PIC-LABEL: f3:
+; RV64-PIC:       # %bb.0: # %entry
+; RV64-PIC-NEXT:  .LBB2_1: # %entry
+; RV64-PIC-NEXT:    # Label of block must be emitted
+; RV64-PIC-NEXT:    auipc a0, %tls_ie_pcrel_hi(ie)
+; RV64-PIC-NEXT:    ld a0, %pcrel_lo(.LBB2_1)(a0)
+; RV64-PIC-NEXT:    add a0, a0, tp
+; RV64-PIC-NEXT:    ret
+;
+; NOPIC-LABEL: f3:
+; NOPIC:       # %bb.0: # %entry
+; NOPIC-NEXT:    lui a0, %tprel_hi(ie)
+; NOPIC-NEXT:    add a0, a0, tp, %tprel_add(ie)
+; NOPIC-NEXT:    addi a0, a0, %tprel_lo(ie)
+; NOPIC-NEXT:    ret
+entry:
+  ret i32* @ie
+}
+
+
+; localexec specified
+
+define i32* @f4() nounwind {
+; RV32-PIC-LABEL: f4:
+; RV32-PIC:       # %bb.0: # %entry
+; RV32-PIC-NEXT:    lui a0, %tprel_hi(le)
+; RV32-PIC-NEXT:    add a0, a0, tp, %tprel_add(le)
+; RV32-PIC-NEXT:    addi a0, a0, %tprel_lo(le)
+; RV32-PIC-NEXT:    ret
+;
+; RV64-PIC-LABEL: f4:
+; RV64-PIC:       # %bb.0: # %entry
+; RV64-PIC-NEXT:    lui a0, %tprel_hi(le)
+; RV64-PIC-NEXT:    add a0, a0, tp, %tprel_add(le)
+; RV64-PIC-NEXT:    addi a0, a0, %tprel_lo(le)
+; RV64-PIC-NEXT:    ret
+;
+; NOPIC-LABEL: f4:
+; NOPIC:       # %bb.0: # %entry
+; NOPIC-NEXT:    lui a0, %tprel_hi(le)
+; NOPIC-NEXT:    add a0, a0, tp, %tprel_add(le)
+; NOPIC-NEXT:    addi a0, a0, %tprel_lo(le)
+; NOPIC-NEXT:    ret
+entry:
+  ret i32* @le
+}