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[RISCV] Add inline asm constraints I, J & K for RISC-V
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Authored by lewis-revill on Nov 5 2018, 1:42 AM.

Details

Summary

This allows the constraints I, J & K to be used in inline asm for RISC-V, with the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Integer zero only.
K: Any 5-bit unsigned immediate.

See the GCC definitions here: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html

Note that GCC also implements 'f' for floating point register and 'A' for address-only operand. These are not implemented here because:

  1. It appears trivial to implement the floating point register constraint, however since floating point registers are not yet recognised by the calling convention the call to the inline asm node cannot be lowered.
  1. I'm not yet certain how to implement an 'address-only' operand and I'd rather get the above constraints done first and add it later.

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Repository
rL LLVM

Event Timeline

lewis-revill created this revision.Nov 5 2018, 1:42 AM
asb requested changes to this revision.Nov 16 2018, 2:59 AM

Thanks for the patch Lewis. Could I please request the following changes:

  • It would be handy to link to https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html in the patch summary, so people can easily double-check the constraint definitions for themselves
  • Could you add tests for values outside of the expected range. AArch64 and X86 do this in test/Sema/inline-asm-validate-{aarch64,x86}.c
  • It would be worth expanding riscv-inline-asm.c to provide simple sanity checks for "m" and "r"
This revision now requires changes to proceed.Nov 16 2018, 2:59 AM
lewis-revill edited the summary of this revision. (Show Details)

Updated to reflect desired changes (and fix an incorrect boundary). I didn't add r & m to riscv-inline-asm.c as I wasn't clear what exactly was desired.

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asb accepted this revision.Jun 6 2019, 5:50 AM

This looks good to me, but is blocked on the dependent patch being updated. I added a minor comment on riscv-inline-asm.c

test/CodeGen/riscv-inline-asm.c
1 ↗(On Diff #174360)

No need to enable +f for the test, as written.

This revision is now accepted and ready to land.Jun 6 2019, 5:50 AM
lewis-revill edited the summary of this revision. (Show Details)
  • Rebased and fixed test run line
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This revision was automatically updated to reflect the committed changes.