AMDGPU: Use generic tables instead of SearchableTable

[nhaehnle]

Summary

Change-Id: I1d6e080c380242e358fbd1e1ff3a152b4b3cc3f7

[rampitec]

LGTM

[nhaehnle]

Rebased.

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.h

 
 namespace AMDGPU {
 
 struct RsrcIntrinsic {
   unsigned Intr;
   uint8_t RsrcArg;
   bool IsImage;
 };
-const RsrcIntrinsic *lookupRsrcIntrinsicByIntr(unsigned Intr);
+const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
 
 struct D16ImageDimIntrinsic {
   unsigned Intr;
   unsigned D16HelperIntr;
 };
-const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsicByIntr(unsigned Intr);
+const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
 
 } // end AMDGPU namespace
 } // End llvm namespace
 
 #endif

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp

 
 using namespace llvm;
 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "AMDGPUGenInstrInfo.inc"
 
 namespace llvm {
 namespace AMDGPU {
-#define GET_RSRCINTRINSIC_IMPL
+#define GET_RsrcIntrinsics_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 
-#define GET_D16IMAGEDIMINTRINSIC_IMPL
+#define GET_D16ImageDimIntrinsics_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 }
 }
 
 // Pin the vtable to this file.
 void AMDGPUInstrInfo::anchor() {}
 
 AMDGPUInstrInfo::AMDGPUInstrInfo(const AMDGPUSubtarget &ST)

llvm/trunk/lib/Target/AMDGPU/AMDGPUSearchableTables.td

 //===-- AMDGPUSearchableTables.td - ------------------------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 include "llvm/TableGen/SearchableTable.td"
 
 //===----------------------------------------------------------------------===//
 // Resource intrinsics table.
 //===----------------------------------------------------------------------===//
 
-class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> : SearchableTable {
-  let SearchableFields = ["Intr"];
-  let EnumNameField = ?;
-
+class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> {
   Intrinsic Intr = !cast<Intrinsic>(intr);
   bits<8> RsrcArg = intr.RsrcArg;
   bit IsImage = intr.IsImage;
 }
 
+def RsrcIntrinsics : GenericTable {
+  let FilterClass = "RsrcIntrinsic";
+  let Fields = ["Intr", "RsrcArg", "IsImage"];
+
+  let PrimaryKey = ["Intr"];
+  let PrimaryKeyName = "lookupRsrcIntrinsic";
+}
+
 foreach intr = !listconcat(AMDGPUBufferIntrinsics,
                            AMDGPUImageIntrinsics,
                            AMDGPUImageDimIntrinsics,
                            AMDGPUImageDimGatherIntrinsics,
                            AMDGPUImageDimGetResInfoIntrinsics,
                            AMDGPUImageDimAtomicIntrinsics) in {
   def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
 }
 
-class SourceOfDivergence<Intrinsic intr> : SearchableTable {
-  let SearchableFields = ["Intr"];
-  let EnumNameField = ?;
-
+class SourceOfDivergence<Intrinsic intr> {
   Intrinsic Intr = intr;
 }
 
+def SourcesOfDivergence : GenericTable {
+  let FilterClass = "SourceOfDivergence";
+  let Fields = ["Intr"];
+
+  let PrimaryKey = ["Intr"];
+  let PrimaryKeyName = "lookupSourceOfDivergence";
+}
+
 def : SourceOfDivergence<int_amdgcn_workitem_id_x>;
 def : SourceOfDivergence<int_amdgcn_workitem_id_y>;
 def : SourceOfDivergence<int_amdgcn_workitem_id_z>;
 def : SourceOfDivergence<int_amdgcn_interp_mov>;
 def : SourceOfDivergence<int_amdgcn_interp_p1>;
 def : SourceOfDivergence<int_amdgcn_interp_p2>;
 def : SourceOfDivergence<int_amdgcn_mbcnt_hi>;
 def : SourceOfDivergence<int_amdgcn_mbcnt_lo>;

 def : SourceOfDivergence<int_amdgcn_buffer_atomic_xor>;
 def : SourceOfDivergence<int_amdgcn_buffer_atomic_cmpswap>;
 def : SourceOfDivergence<int_amdgcn_ps_live>;
 def : SourceOfDivergence<int_amdgcn_ds_swizzle>;
 
 foreach intr = AMDGPUImageDimAtomicIntrinsics in
 def : SourceOfDivergence<intr>;
 
-class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> : SearchableTable {
-  let SearchableFields = ["Intr"];
-  let EnumNameField = ?;
-
+class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> {
   Intrinsic Intr = intr;
   code D16HelperIntr =
       !cast<code>("AMDGPUIntrinsic::SI_image_d16helper_" # intr.P.OpMod # intr.P.Dim.Name);
 }
 
+def D16ImageDimIntrinsics : GenericTable {
+  let FilterClass = "D16ImageDimIntrinsic";
+  let Fields = ["Intr", "D16HelperIntr"];
+
+  let PrimaryKey = ["Intr"];
+  let PrimaryKeyName = "lookupD16ImageDimIntrinsic";
+}
+
 foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
                            AMDGPUImageDimGatherIntrinsics) in {
   def : D16ImageDimIntrinsic<intr>;
 }

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
   return false;
 }
 
 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
                                           const CallInst &CI,
                                           MachineFunction &MF,
                                           unsigned IntrID) const {
   if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
-          AMDGPU::lookupRsrcIntrinsicByIntr(IntrID)) {
+          AMDGPU::lookupRsrcIntrinsic(IntrID)) {
     AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
                                                   (Intrinsic::ID)IntrID);
     if (Attr.hasFnAttribute(Attribute::ReadNone))
       return false;
 
     SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 
     if (RsrcIntr->IsImage) {
case Intrinsic::amdgcn_image_gather4_c_lz_o: {
 
     return SDValue();
   }
   default:
     if (Subtarget->hasUnpackedD16VMem() &&
         Op.getValueType().isVector() &&
         Op.getValueType().getScalarSizeInBits() == 16) {
       if (const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
-            AMDGPU::lookupD16ImageDimIntrinsicByIntr(IntrID)) {
+            AMDGPU::lookupD16ImageDimIntrinsic(IntrID)) {
         return adjustLoadValueType(D16ImageDimIntr->D16HelperIntr,
                                    cast<MemSDNode>(Op), DAG, true);
       }
     }
 
     return SDValue();
   }
 }
if (Subtarget->hasUnpackedD16VMem() &&
       return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops,
                                      M->getMemoryVT(), M->getMemOperand());
     }
 
     return SDValue();
   }
   default: {
     const AMDGPU::D16ImageDimIntrinsic *D16ImageDimIntr =
-        AMDGPU::lookupD16ImageDimIntrinsicByIntr(IntrinsicID);
+        AMDGPU::lookupD16ImageDimIntrinsic(IntrinsicID);
     if (D16ImageDimIntr) {
       SDValue VData = Op.getOperand(2);
       EVT StoreVT = VData.getValueType();
       if (Subtarget->hasUnpackedD16VMem() &&
           StoreVT.isVector() &&
           StoreVT.getScalarSizeInBits() == 16) {
         SmallVector<SDValue, 12> Ops(Op.getNode()->op_values());
 

llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

AMDGPUAS getAMDGPUAS(const Module &M) {
   return getAMDGPUAS(Triple(M.getTargetTriple()));
 }
 
 namespace {
 
 struct SourceOfDivergence {
   unsigned Intr;
 };
-const SourceOfDivergence *lookupSourceOfDivergenceByIntr(unsigned Intr);
+const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
 
-#define GET_SOURCEOFDIVERGENCE_IMPL
+#define GET_SourcesOfDivergence_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 
 } // end anonymous namespace
 
 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
-  return lookupSourceOfDivergenceByIntr(IntrID);
+  return lookupSourceOfDivergence(IntrID);
 }
 } // namespace AMDGPU
 } // namespace llvm